JP5489205B2 - Electric circuit and method for controlling electric circuit - Google Patents

Description

  The present invention relates to a technique for suppressing an influence of an inrush current to a main circuit that occurs when a power supply is turned on in a power supply circuit.

  When the device is turned on, a much larger current (inrush current) than the steady state may flow through the device. This inrush current may adversely affect the device, such as welding a switch contact in the device, blowing a fuse, or cutting a breaker.

  As a circuit for reducing the influence of the inrush current, there is a power supply circuit disclosed in Patent Document 1. A circuit diagram of this power supply circuit is shown in FIG. The power supply circuit described in FIG. 4 includes a drive pulse generating means for generating a drive pulse, a push-pull configuration switching means having a transistor, capacitors 92, 94, 104, and 106, and a charge / discharge means having a diode. And having. Further, this power supply circuit is provided with a power supply E and a capacitor 58 for boosting the charge / discharge means.

  In this power supply circuit, at the moment when the power supply E is turned on, an inrush current for rapidly charging the capacitor 58 flows. After the operation starts, each time the output of the drive pulse generating means is inverted, the capacitors 92, 94, 102, and 106 are charged stepwise as shown in Patent Document 1.

  In this configuration, if the capacitances of the capacitors 92 and 94 are made smaller than the capacitance of the capacitor 58, the capacitors 92, 94 and 58 are charged and discharged each time the drive pulse generating means is reversed after the operation starts. Energy can be reduced. The same applies to a circuit constituted by the capacitors 102 and 106 and a diode attached thereto.

  However, in this power supply circuit, the peak value of the inrush current is limited only by the sum of the on-resistance of the transistor in the line and the resistance of the diode in the line. For this reason, when the capacitance of the capacitor is large, the peak value of the inrush current can be a large value. In this case, the power supply circuit may not be able to prevent the influence of the inrush current.

  There is a power supply circuit described in Patent Document 2 as a circuit that suppresses the influence of the occurrence of an inrush current having a high peak value. A circuit diagram of this power supply circuit is shown in FIG. As shown in FIG. 5, the power supply circuit includes resistors R1 and R2 and a capacitor C2 in addition to a power-on switch, a bypass capacitor C1, a main circuit, and an FET. One end of the resistor R1 is connected to a switch for turning on the power, and the other end is connected to a gate terminal of an FET (Field Effect Transistor) and a capacitor C2. The bypass capacitor C1 is inserted in parallel with the main circuit, and one end thereof is connected to the drain terminal of the FET. The resistor R2 is connected in parallel with the capacitor C2.

  In such a configuration, when the switch is turned on, the gate voltage of the FET gradually increases with time, and the FET gradually changes from the cutoff state (off state) to the conductive state (on state) as the gate voltage increases. To move on. For this reason, in the power supply circuit, the FET is in a cut-off state immediately after the power is turned on, and gradually shifts to the conductive state. The Therefore, the circuit can prevent an inrush current having a high peak value from flowing into the main circuit.

JP-A-1-243847 Japanese Utility Model Publication No. 5-71910

  However, in the circuit described in Patent Document 2, there is a case where the influence of the inrush current cannot be prevented.

  In this circuit, in order to gradually increase the gate voltage of the FET, it is necessary to take a large time constant in the RC circuit including the resistor R1 and the capacitor C2. Specifically, a large time constant of at least several hundred mS, preferably several seconds is required, and for example, a value of several hundreds KΩ and a value of several μF to several tens of μF are required as the value of the resistor R1.

  On the other hand, when the switch is turned off, it is necessary to quickly discharge the capacitor C2 in preparation for the next power-on. For this reason, it is desirable to reduce the time constant in the RC circuit including the capacitor C2 and R2 connected in parallel to C2.

  However, the height of the gate voltage in the steady state when the power is turned on depends on the ratio of the resistors R1 and R2. For this reason, in order to obtain a gate voltage equal to or higher than the on-voltage, the value of the resistor R2 must be set to a certain value or higher.

  Also, the capacitor C2 must have a sufficiently high capacity so that the FET can be turned on by discharging.

  Since the value of the resistor R2 cannot be reduced and the capacitor C2 must have a large capacity, it is difficult to reduce the time constant based on the resistor R2 and the capacitor C2.

  Therefore, it takes time until the capacitor C2 is sufficiently discharged. Then, when the switch is turned on / off / on in a short time, the capacitor C2 may not be discharged in time, and the FET may already be turned on when the power is turned on again. This cannot prevent the inrush current from flowing into the main circuit.

  An object of the present invention is to reliably suppress the influence of an inrush current even when the power is turned on and off repeatedly in a short time.

To achieve the above object, an electric circuit of the present invention includes a power supply for supplying a constant voltage, operates after the power is turned on, an oscillating means for generating a Rupa pulse signal to increase with the duty ratio of time , comprising a first capacitor and a first resistor, said oscillating means and is electrically connected, by integrating the voltage of the pulse signal generated by said oscillation means, the integration circuit for generating a dc voltage signal And a switching circuit that is electrically connected to the first capacitor and the first resistor and applies a voltage from the power source to the main circuit based on a voltage value of the DC voltage signal generated by the integration circuit. And a discharge means for discharging the first capacitor with a time constant shorter than the time constant based on the first capacitor and the first resistance when the power source is cut off.

Control method for an electric circuit of the present invention, the oscillation means is operated after the power is turned on, generates a Rupa pulse signal to increase with the duty ratio of time, comprising a first capacitor and a first resistor, the oscillation means and electrically connected to the integrated circuit, by integrating the voltage of the generated the pulse signal by the pre-Symbol oscillation means to produce a dc voltage signal, said first capacitor and said first resistance electrically connected to the switching element, based on the voltage value of the generated the DC voltage signal by the integrating circuit, a voltage from the power supply is applied to the main circuit, the discharge means, the power supply is cut off When this is done, the electric circuit is controlled by discharging the first capacitor with a time constant shorter than the time constant based on the first capacitor and the first resistor.

  According to the present invention, the integration circuit generates a DC voltage signal by integrating the voltage of the pulse signal whose duty ratio increases with time, and the switching element is released from the cut-off state in response to an increase in the voltage value of the DC voltage signal. Gradually transitions to the conducting state, applies voltage to the main circuit, and discharges the capacitor with a time constant shorter than the time constant based on the capacitor and resistance of the integrating circuit, so the electric circuit can discharge the capacitor quickly and for a short time Even when the power is turned on and off repeatedly, the inrush current can be reliably prevented from flowing into the main circuit.

It is a circuit diagram which shows one structural example of the power supply circuit of this embodiment. It is a graph which shows an example of the time change of the gate voltage of this embodiment, and a drain current. It is a circuit diagram which shows one structural example of the power supply circuit of the modification of this invention. It is a circuit diagram of a general power supply circuit. It is a circuit diagram of a general charging circuit.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration example of the power supply circuit 10 of the present embodiment. Referring to FIG. 1, the power supply circuit 10 is connected to the main circuit 20. The power supply circuit 10 includes a power supply V1, a switch S1, an oscillator OSC, resistors R1 and R2, a capacitor C2, a transistor Q1, and a bypass capacitor C1.

  The main circuit 20 is a circuit such as a switching power supply, a fluorescent lamp transfer circuit, and a motor drive circuit. A bypass capacitor C1 is connected to the main circuit 20 in parallel. The bypass capacitor C1 bypasses and removes unnecessary noise and signals from the signal supplied to the main circuit 20.

  The power supply V1 supplies power to the main circuit 20. One end of the switch S1 is connected to the main circuit 20, and the other end is connected to the main circuit 20. The switch S1 opens or closes the line according to a user operation or the like to turn on the power to the main circuit 20 or cut off the power.

  The oscillator OSC is an oscillation circuit that can vary the duty ratio of a pulse. The oscillator OSC is connected to the switch S1 through a signal line (not shown), and operates according to the open / closed state of the switch S1. The oscillator OSC starts an oscillating operation at a predetermined frequency immediately after the switch S1 is closed or after a predetermined time has elapsed since the switch S1 is closed, and generates a pulse signal. For example, the duty ratio of the pulse signal at the start of oscillation of the oscillator OSC is set to a sufficiently small value so that the transistor Q1 is not turned on at that time. Then, the oscillator OSC increases the duty ratio of the pulse signal with time until it reaches a predetermined maximum value.

  When the switch S1 is in the open state, the oscillator OSC immediately stops the oscillation operation.

  One end of the resistor R1 is connected to the oscillator OSC, and the other end is connected to the capacitor C2 and the transistor Q1. Capacitor C2 is connected to resistor R1 and transistor Q1.

  The RC integration circuit including the resistor R1 and the capacitor C2 time-integrates the voltage of the pulse signal output from the oscillator OSC to convert it into a DC voltage, and applies the DC voltage to the transistor Q1.

  The resistor R2 is connected in parallel with the capacitor C2. Here, the resistance value of the resistor R2 is set to a sufficiently small value compared to the resistor R1. By reducing the resistance value of the resistor R2, the capacitor C2 is quickly discharged with a small time constant obtained by multiplying R2 and C2 when the power is shut off.

  The transistor Q1 is an FET. The gate terminal of the transistor Q1 is connected to the resistor R1 and the capacitor C2, the source terminal is grounded, and the drain terminal is connected to the main circuit 20 and the bypass capacitor C1.

  The operation of the power supply circuit 10 will be described. After the switch S1 is closed, the oscillator OSC starts an oscillation operation. The resistor R1 and the capacitor C2 integrate the pulse voltage to convert it into a DC voltage, and apply it to the gate terminal of the transistor Q1.

  As described above, when the oscillation of the oscillator OSC starts, the duty ratio of the pulse is set so that the DC voltage after integration is smaller than the ON voltage of the transistor Q1. Therefore, immediately after the switch S1 is closed, the transistor Q1 is off. In the off state, the drain-source resistance of the transistor Q1 is very high compared to the on state, so that the drain current to the main circuit 20 is limited.

  The oscillator OSC increases the duty ratio of the pulse as time passes. As the duty ratio increases, the gate voltage of the transistor Q1 also gradually increases. As the gate voltage increases, the transistor Q1 gradually shifts from the off state to the on state.

  As described above, the transistor Q1 is in the OFF state from the time immediately after the switch S1 is in the closed state to the predetermined period, and the current flowing into the main circuit 20 is limited. This prevents an inrush current having a high peak value from flowing into the main circuit 20 when the power is turned on.

  Next, when the switch S1 is opened, the power to the main circuit 20 is cut off and the oscillator OSC stops oscillating, so that the charge accumulated in the capacitor C2 is discharged via the resistor R2. .

  The resistance value of the resistor R2 is not limited to a certain value or more unlike the general circuit described with reference to FIG. 5, and can be set to a sufficiently small value. Specifically, it is only necessary to have a time constant for integrating the pulse signal generated by the oscillator OSC and converting it to direct current. Therefore, the time constant can be reduced as the oscillation frequency of the pulse signal increases. For this reason, the time constant based on the resistor R2 and the capacitor C2 can be made small by appropriately selecting the oscillation frequency of the pulse signal generated by the oscillator OSC, and the power supply circuit 10 rapidly discharges the capacitor C2. be able to.

  Therefore, even when the power is turned on and off repeatedly in a short time, the power circuit 10 can suppress the inrush current from flowing into the main circuit 20 when the power is turned on again.

  FIG. 2 is a graph illustrating an example of temporal changes in the current I1 and the gate voltage VG in the power supply circuit 10. The current I1 is a current supplied from the power supply V1. The gate voltage VG is the gate voltage of the transistor Q1.

  The vertical axis in FIG. 2 is the drain current I1 or the gate voltage VG of the transistor Q1, and the horizontal axis is time. When the switch S1 is closed at time “t0”, the oscillator OSC starts an oscillation operation. The duty ratio of the pulse signal increases from an initial value (for example, 0%) to a maximum value. At the start of oscillation, since the duty ratio of the pulse signal is small, the initial value of the gate voltage VG is smaller than the on-voltage “Von”. Until VG changes from the initial value to Von, the resistance value between the drain and source of the transistor Q1 is much larger than that in the on state, so that an inrush current with a high peak value flows into the main circuit 20. It is suppressed.

  As time passes, the duty ratio of the pulse increases and the gate voltage VG also increases. When the time “t1” is reached, the gate voltage VG reaches the ON voltage “Von”. During the period from time “t0” to time “t1”, the transistor Q1 is in the off state, so that the bypass capacitor C1 is slowly charged by the drain current limited by the high resistance in the off state.

  Then, after the transistor Q1 is turned on at time “t1”, the drain current (charging current) has a peak at time “t2”. However, since the bypass capacitor C1 has been charged to some extent until then, the peak value of the charging current is small compared to the case where the transistor Q1 is turned on immediately after the power is turned on.

  In the present embodiment, the pulse is generated by the oscillator OSC. However, the pulse may be generated by other methods. For example, in the power supply circuit 10, instead of the oscillator OSC, as shown in FIG. A microcomputer 11 is provided. The microcomputer 11 generates a pulse whose duty ratio gradually increases according to the program.

  If the apparatus including the power supply circuit 10 originally includes the microcomputer 11, the microcomputer can be used for the power supply circuit 10, and an oscillation circuit need not be provided. For this reason, an increase in cost can be minimized. Furthermore, the variable speed of the duty ratio can be arbitrarily changed by changing the program.

  In this embodiment, the resistor R2 is provided in order to quickly discharge the capacitor C2. However, if the capacitor C2 can be discharged through the oscillator OSC and the resistor R1, the resistor R2 is not connected. You can also.

  In the present embodiment, an FET is used as the transistor Q1, but any switching element may be used as long as the voltage obtained by integrating the voltage of the pulse signal becomes equal to or higher than a threshold, and is not limited to the FET. For example, a bipolar transistor can be used as the transistor Q1.

  The power supply circuit 10 of this embodiment corresponds to the electric circuit of the present invention. The switch S1 of the present embodiment is an example of the input unit of the present invention, and the oscillator OSC of the present embodiment is an example of the oscillation unit of the present invention. The circuit composed of the resistor R1 (first resistor) and the capacitor C2 (first capacitor) according to this embodiment corresponds to the integrating circuit of the present invention. The transistor Q1 of this embodiment is an example of the switching element of the present invention. The resistor R2 (second resistor) of the present embodiment is an example of the discharge unit of the present invention.

  As described above, according to the present embodiment, the integration circuit generates a DC voltage signal by integrating the voltage of the pulse signal whose duty ratio increases with time, and the switching element increases the voltage value of the DC voltage signal. In response, the electric circuit gradually changes from the cut-off state to the conductive state, applies a voltage to the main circuit, and discharges the capacitor with a time constant shorter than the time constant based on the capacitor and resistance of the integration circuit. Even if the power can be discharged quickly and the power is turned on and off repeatedly in a short time, the inrush current can be reliably prevented from flowing into the main circuit.

  Further, since the oscillator OSC gradually increases the duty ratio with time to gradually shift the transistor from the off state to the on state, in the process, the bypass capacitor C1 is limited by the current limited by the drain-source resistance of the FET. Is charged. Therefore, the electric circuit can prevent an inrush current having a high peak value from flowing into the main circuit when the power is turned on.

10 power supply circuit 11 microcomputer 20 main circuit V1 power supply S1 switch OSC oscillator R1, R2 resistor C1 bypass capacitor C2 capacitor Q1 transistor

Claims (7)

A power supply for supplying a constant voltage;
And oscillating means for said power supply operates after being turned on, to generate a Rupa pulse signal to increase with the duty ratio of time,
Comprising a first capacitor and a first resistor, said oscillating means and is electrically connected, by integrating the voltage of the pulse signal generated by said oscillation means, an integrating circuit for generating a dc voltage signal ,
A switching element that is electrically connected to the first capacitor and the first resistor and applies a voltage from the power source to the main circuit based on a voltage value of the DC voltage signal generated by the integrating circuit; ,
Discharging means for discharging the first capacitor with a time constant shorter than the time constant based on the first capacitor and the first resistor when the power source is shut off;
Having an electrical circuit.   The electric circuit according to claim 1, wherein the oscillating means includes an oscillator capable of changing a duty ratio of a pulse signal.   The electric circuit according to claim 1, wherein the oscillating means includes a microcomputer that generates a pulse signal having a constant period with a duty ratio increasing with time.   4. The electric circuit according to claim 1, wherein the switching element is a field effect transistor having a gate electrode connected to the integration circuit and a drain electrode connected to the main circuit. 5.   5. The electricity according to claim 1, wherein the discharging unit includes a second resistor connected in parallel to the first capacitor and having a resistance value smaller than a resistance value of the first resistor. circuit.   The electric circuit according to claim 1, further comprising a second capacitor connected in parallel to the main circuit. Oscillating means operates after the power is turned on, generates a Rupa pulse signal to increase with the duty ratio of time,
Comprising a first capacitor and a first resistor, by said oscillating means and electrically connected to the integration circuit integrates the voltage of the generated the pulse signal by the pre-Symbol oscillating means, a dc voltage signal Generate
A switching element electrically connected to the first capacitor and the first resistor applies a voltage from the power source to the main circuit based on a voltage value of the DC voltage signal generated by the integrating circuit. And
An electrical circuit control method for discharging the first capacitor with a time constant shorter than a time constant based on the first capacitor and the first resistor when the power source is cut off.

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