JP5489787B2 - Receiver - Google Patents

Description

  The present invention relates to a receiving apparatus that can improve the accuracy of decoding of a received signal.

  In general, when performing communication, it is necessary to recognize a signal format, a modulation method, a multiplexing method, a transmission / reception frequency, and the like on both the transmission side and the reception side. In particular, in the digital communication system, the signal may not be correctly received unless the transmission side recognizes the timing at which the signal is transmitted. For this reason, it is essential that the transmitting side correctly conveys necessary control information to the receiving side, and that the receiving side accurately identifies the signal based on the control information.

  In order to realize this, there is a method of periodically multiplexing and transmitting the control information as data as a control signal. This control signal is generally called a preamble or a postamble. Usually, when an information signal is transmitted from a transmitter, the control signal is transmitted in a multiplexed manner in time or frequency in distinction from the information signal. In the following description, a method of transmitting the control signal by multiplexing it in the preamble in time will be described.

  In this method, the receiving side can perform authentication for recognizing a communication partner, and determine communication means such as a frequency, a modulation method, and a multiplexing method used when performing communication. This method can also be used effectively for specifying the start time of a control signal or information signal (that is, frame synchronization). For this reason, this method has already been incorporated into various communication protocols.

  Further, by inserting a known signal into the preamble and monitoring the change of the known signal in the receiver, it is possible to detect a deviation in frequency and phase used between the transceivers. For this reason, a known signal may be utilized in order to obtain frequency synchronization between transmitters / receivers (for example, see Non-Patent Document 1 and Non-Patent Document 2).

  When considering a communication system in which the preamble and data are transmitted alternately in time and continuously, generally, the control signal is analyzed each time a preamble is detected, and frame synchronization or frequency synchronization is performed. In many cases, signal processing is performed.

  When constructing a communication system, if there is no strong constraint on the circuit scale or computation scale of the system, frame synchronization and frequency synchronization are predetermined by introducing independent signal processing for performing synchronization processing as described above. Accuracy can be maintained. In addition, if the signal processing is performed such that the control signal is analyzed over two or more preambles, the accuracy can be further improved.

  However, when constructing a communication system in which the circuit scale and the computation scale are limited, it is not always possible to perform frame synchronization and frequency synchronization with high accuracy as described above. In particular, in the case of a simple communication system with a small amount of data to be transmitted / received, there is a problem that the transmission efficiency deteriorates because the ratio of the control signal to the total transmission data is relatively large.

  In addition, in the case of an intermittent communication system in which transmission and reception are performed by temporally intermittently combining a preamble and data as a set, the preamble cannot be received periodically. In addition, it is not easy to analyze the control signal over two or more preambles to improve the accuracy of synchronization.

  As a means to solve such problems, a method of simplifying signal processing by introducing a mechanism for performing frame synchronization and frequency synchronization at the same time, and reducing the control signal in the preamble to improve transmission efficiency Has been proposed. More specifically, the frequency synchronization is performed based on the timing at which frame synchronization is established in the receiver.

  By adopting such a method, signal processing for frequency synchronization is unnecessary, so the circuit scale and computation scale can be reduced, and control signals required for frequency synchronization are also unnecessary. Therefore, the preamble is shortened and the transmission efficiency is improved (for example, see Non-Patent Document 3).

  In such a communication system, the frame synchronization position in the receiver can maintain a predetermined accuracy, but some errors usually remain in the frequency synchronization. Therefore, when data reception is continued after the frame synchronization is established, the frequency error accumulates with time and the received signal quality deteriorates.

  With respect to such a problem, in Patent Document 1, the offset phase angle of the data signal with respect to the replica signal is sequentially detected, and this is cumulatively added so that the phase of the data signal follows the replica signal. A method of enabling data decoding without being affected by a frequency deviation between transmitters and receivers by equivalently realizing a function corresponding to is disclosed.

Japanese Patent No. 3348661 (paragraph 0022, FIG. 1)

Hideaki Matsue et al., “High-Speed Wireless Access Technology”, The Institute of Electronics, Information and Communication Engineers, March 2004, pp. 211-218 Shiro Sakata, “Wireless Ubiquitous”, Hidekazu System, August 2004, pp. 62-68 Takao Yamashita et al., “Clock Frequency Synchronization Using High-Speed Digital Network”, IEICE Transactions (DI), August 1996, pp. 522-529

  However, when the method disclosed in Patent Document 1 is employed, an unexpected offset phase angle is detected when data demodulation is erroneous, and the phase of the data signal is updated by accumulating the detected offset phase angle. The follow-up performance is degraded. In addition, when the reception environment is such that the reliability of the reference signal deteriorates due to the influence of noise or the like, the reliability of the decoded data signal is also reduced as compared with the replica signal, so that there is a possibility that the replica signal cannot be tracked. is there.

  Furthermore, in an environment where there is an undesired signal having strong power such as impulsive noise, the phase of the data signal may instantaneously change suddenly. There is a possibility that the phase of the data signal cannot instantaneously follow the replica signal.

  Patent Document 1 discloses means for changing the response characteristics of a digital filter by monitoring the received signal level and the bit error rate in order to reduce the influence of signal quality degradation due to noise. However, such a method requires not only another signal processing to monitor the received signal level and bit error rate, but also complicated signal processing to configure a digital filter. However, problems still remain when communication systems with restrictions on circuit scale and computation scale are targeted.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a receiving apparatus that can improve the accuracy of decoding of a received signal.

A receiving apparatus according to an aspect of the present invention receives a reference signal and a reference correction signal detected from a synchronization signal sequence in a received signal sequence, and selects either the reference signal or the reference correction signal as a reference. An input selector that selectively outputs as a signal; and a selector that outputs a selection signal that causes the input selector to selectively output either the reference signal or the reference correction signal as the reference selection signal; A phase shifter that outputs a replica signal of N systems (N is an integer of 2 or more) by rotating the phase of the reference selection signal, an information signal sequence in the received signal sequence, and the N replica signals In comparison, an error calculator for outputting N error signals based on the result of the comparison, and detecting a minimum value among the N error signals, and corresponding to the detected error signal of the minimum value. Minimum error number A minimum value detector to output, a recombination unit to output a preparation signal generated by rotating the phase of the information signal sequence according to the value of the minimum error number, and the value according to the value of the minimum error number. Analyzing the error signal, generating a feedback control signal based on the result of this analysis, and applying the weighting based on the value of the feedback control signal to the preparation signal and the reference selection signal And a feedback controller that updates a reference correction signal and supplies the updated reference correction signal to the input switch.

A receiving apparatus according to another aspect of the present invention receives a reference signal and a reference correction signal detected from a synchronization signal sequence in a received signal sequence, and uses either the reference signal or the reference correction signal as a reference. An input selector that selectively outputs as a selection signal; and a selector that outputs a selection signal that causes the input selector to selectively output either the reference signal or the reference correction signal as the reference selection signal; A phase shifter that rotates the phase of the reference selection signal and outputs N-system (N is an integer of 2 or more) replica signals; an information signal sequence in the received signal sequence; and the N-system replica signals; And an error calculator for outputting N error signals based on the comparison result, and detecting a minimum value among the N error signals and corresponding to the detected error signal of the minimum value Minimum error number A minimum value detector that outputs, a recombination unit that outputs a preparation signal generated by rotating the phase of the information signal sequence according to the value of the minimum error number, the reference selection signal, and the preparation signal, Analyzing the error signal according to the value of the minimum error number and generating a feedback control signal based on the result of the analysis, the feedback control signal with respect to the preparation signal and the reference selection signal And a feedback controller that updates the reference correction signal by applying weighting based on the value of and supplies the updated reference correction signal to the input switch.

  According to the receiving apparatus of the present invention, the diversity effect can be obtained by accumulating the received signal with respect to the reference signal. Therefore, regardless of the signal level of the thermal noise component and the impulsive noise included in the reference signal, This can reduce the influence of the signal and improve the signal quality of the replica signal.

  Further, according to the receiving apparatus of the present invention, a replica signal is obtained using only a highly reliable received signal by applying a coefficient based on the reliability of the demodulated signal to the received signal and accumulating this coefficient to the reference signal. Therefore, it is possible to efficiently improve the signal quality of the replica signal.

  In addition, according to the receiving apparatus of the present invention, by applying a coefficient based on the reliability of the demodulated signal to the received signal and referring to the phase change of the demodulated signal when cumulatively adding the coefficient to the reference signal, the impulse characteristics There is an effect that noise can be detected and its influence can be reduced, and the signal quality of the replica signal can be improved.

  Further, according to the receiving apparatus according to the present invention, when a coefficient based on the reliability of the demodulated signal is given to the received signal, the coefficient can be controlled automatically or manually, and stability and followability can be improved accordingly. Since it can be controlled, there is an effect that a flexible design of the communication system can be performed.

  Furthermore, according to the receiving apparatus of the present invention, the signal processing necessary for correcting the replica signal can be limited to signal addition / subtraction, comparison, recombination, and switching. Even if it is a certain communication system, there exists an effect that this function can be implement | achieved easily.

It is a block diagram which shows roughly the structural example of the receiver of Embodiment 1 which concerns on this invention. 6 is a timing diagram illustrating an example of a relationship of signals input to the receiving device of Embodiment 1. FIG. FIG. 2 is a timing chart showing an example of the operation of the input switch shown in FIG. 1. FIG. 2 is a block diagram schematically showing a configuration example of a phase shifter shown in FIG. 1. It is a wave form diagram which shows an example of operation | movement of the phase shifter shown by FIG. FIG. 2 is a block diagram schematically showing a configuration example of an error calculator shown in FIG. 1. FIG. 7 is a block diagram schematically showing a configuration example of a comparison arithmetic unit shown in FIG. 6. It is a figure which shows operation | movement of the comparison arithmetic unit shown by FIG. It is a block diagram which shows roughly the structural example of the recombination machine shown by FIG. It is a figure which shows operation | movement of the recombination machine shown by FIG. It is a block diagram which shows roughly the structural example of the signal quality determination device shown by FIG. It is a figure which shows operation | movement of the signal quality determination device shown by FIG. FIG. 12 is a block diagram schematically showing a configuration example of a determiner shown in FIG. 11. FIG. 2 is a block diagram schematically showing a configuration example of a feedback controller shown in FIG. 1. 6 is a diagram for explaining an effect of the receiving apparatus according to Embodiment 1. FIG. It is a block diagram which shows roughly the structural example of the receiver of Embodiment 2 which concerns on this invention. FIG. 17 is a block diagram schematically showing a configuration example of a signal quality determiner shown in FIG. 16. FIG. 18 is a block diagram schematically showing a configuration example of a determiner shown in FIG. 17. FIG. 10 is a diagram for explaining an effect of the receiving apparatus according to the second embodiment. It is a block diagram which shows roughly the structural example of the receiver of Embodiment 3 which concerns on this invention. FIG. 21 is a block diagram schematically showing a configuration example of a signal quality determiner shown in FIG. 20. FIG. 10 is a diagram for explaining an effect of the receiving apparatus according to the third embodiment. It is a block diagram which shows roughly the structural example of the receiver of Embodiment 4 which concerns on this invention. FIG. 24 is a block diagram schematically showing a configuration example of a feedback controller shown in FIG. 23.

Embodiment 1 FIG.
FIG. 1 is a block diagram schematically showing a configuration example of a receiving apparatus 10 according to the first embodiment of the present invention. The receiving apparatus 10 can detect the reference signal when receiving the synchronization signal sequence and can correct the replica signal when receiving the information signal sequence. The receiving apparatus 10 can more efficiently correct the replica signal by adaptively changing the feedback control signal by determining the signal quality of the error signal of N systems (N is an integer of 2 or more). it can.

As shown in FIG. 1, the receiving apparatus 10 includes an input switch 11, a selector 12, a phase shifter 13, an error calculator 14, a minimum value detector 15, a recombiner 16, a signal A quality determiner 17 and a feedback controller 18 are provided. In FIG. 1, S ₀ (t) is an information signal sequence, and S ₁ (t) is a synchronization signal sequence. Both the signal sequences S ₀ (t) and S ₁ (t) have a signal X () obtained by digitally converting a received signal received using a means (not shown) for receiving a wired signal or a wireless signal. a signal separated from t). Here, t is an arbitrary time. Also, it is desirable that the frame synchronization position of the received signal has already been detected using other means (not shown). In order to simplify the description, the synchronization signal sequence S ₁ (t) is treated as a reference signal below. The receiving apparatus 10 includes an output switch (not shown) that branches the received signal sequence X (t) into the information signal sequence S ₀ (t) and the synchronization signal sequence S ₁ (t), and the synchronization signal sequence S _1. You may provide the reference signal detector (not shown) which detects a reference signal from (t).

The selector 12 outputs a selection signal W (t) to the input switch 11. The input switch 11 receives the selection signal W (t), the reference signal S ₁ (t), and the reference correction signal F (t) that is the output of the feedback controller 18. The input switch 11 adaptively selects either the reference signal S ₁ (t) or the reference correction signal F (t) according to the value of the selection signal W (t) output from the selector 12, The selected signal is output as a reference selection signal Y (t).

FIG. 2 is a timing chart showing an example of the relationship of signals input to the receiving device 10. As shown in FIG. 2, the information signal series S ₀ (t) and the reference signal S ₁ (t) are signals that are switched according to, for example, the selection signal W (t). In FIG. 2, a received signal X (t) is a signal that has been received and digitally converted using means for receiving a wired signal or a wireless signal. In FIG. 2, the received signal X (t) is configured by repetition of synchronization signal sequences P1, P2,... And information signal sequences D1, D2,. The selection signal W (t) becomes “1” when the synchronization signal sequence is received, and becomes “0” when the information signal sequence is received. When the selection signal W (t) is “1”, the reception signal X (t) is output as the reference signal S ₁ (t), and when the selection signal W (t) is “0”, the reception signal X (T) can be output as the information signal sequence S ₀ (t).

FIG. 3 is a timing chart showing an example of the operation of the input switch 11 shown in FIG. As shown in FIG. 3, the reference signal S ₁ (t) and the reference correction signal F (t) are input to the input switch 11. The selector 12 alternately outputs “1” or “0” as the selection signal W (t) to the input switch 11. The input switch 11 outputs the reference signal S ₁ (t) as the reference selection signal Y (t) when the selection signal W (t) is “1”, and the selection signal W (t) is “0”. Sometimes, the reference correction signal F (t) is output as the reference selection signal Y (t). As described above, the input switch 11 generates the reference selection signal Y (t) from the reference signal S ₁ (t) or the reference correction signal F (t).

As shown in FIG. 1, the phase shifter 13 converts a signal obtained by rotating the phase of the reference selection signal Y (t) into N replica signals R (t) (that is, R ₀ (t), R ₁ ( t),..., R _N-1 (t)).

FIG. 4 is a block diagram schematically showing a configuration example of the phase shifter 13. As shown in FIG. 4, the phase shifter 13 includes a plurality of phase rotation units (2π × (1 / N)), (2π × (2 / N)),..., (2π × ((N−1)). / N)). The phase shifter 13 receives the reference selection signal Y (t), and converts the signal obtained by rotating the phase of the reference selection signal Y (t) into N-system replica signals R ₀ (t), R ₁ (t),. Output as R _N-1 (t). .., R _N-1 (t) are all different in the amount of phase rotation given, and the phase rotation of adjacent replica signals is different from that of the N replica signals R ₀ (t), R ₁ (t),. The amount difference is preferably 2π / N [rad] = 360 / N [deg]. Furthermore, N is preferably the number of samples of signal points constituting one replica signal.

FIG. 5 is a waveform diagram showing an example of the operation of the phase shifter 13. FIG. 5 shows that the replica signal R ₀ (t) output from the phase shifter 13 when a sinusoidal signal is input as the reference selection signal Y (t) to the phase shifter 13 when N = 4. , R ₁ (t), R ₂ (t), R ₃ (t) are shown. When N = 4, the difference between the phase rotation amounts of the adjacent replica signals is π / 2, so that the replica signals R ₀ (t), R ₁ (t), R ₂ (t), R ₃ (t) are , The signals are different in phase by π / 2.

As shown in FIG. 1, the error calculator 14 compares the N system replica signals R (t) with the information signal series S ₀ (t), and the N system error signals E (t) (that is, E ₀ ). (T),..., E _N-1 (t)) are output.

FIG. 6 is a block diagram schematically showing a configuration example of the error calculator 14. As shown in FIG. 6, the error calculator 14 has N types of comparison calculators 141. The N comparison operation units 141 compare the N system replica signals R (t) (that is, R ₀ (t),..., R _N−1 (t)) with the information signal sequence S ₀ (t), The comparison result is output as an N-system error signal E (t) (that is, E ₀ (t),..., E _N-1 (t)). More specifically, each comparison computing unit 141 specified by an arbitrary integer k (0 ≦ k ≦ N−1) compares the replica signal R _k (t) with the information signal sequence S ₀ (t), The comparison result is output as an error signal E _k (t).

FIG. 7 is a block diagram schematically showing a configuration example of the comparison computing unit 141 shown in FIG. The N comparison calculators 141 shown in FIG. 7 need only have the same function. For this reason, the comparison calculator 141 to which the replica signal R _k (t) is input will be described.

As shown in FIG. 7, the comparison computing unit 141 delays the replica signal R _k (t) in time, and a plurality of delay units 1411 for delaying the information signal sequence S ₀ (t) in time. A plurality of delay units 1412, a plurality of subtracters 1413, and an absolute value adder 1414. For example, the plurality of delay devices 1411 are composed of N−1 stages, the plurality of delay devices 1412 are composed of N−1 stages, and the plurality of subtractors 1413 are composed of N−1 stages.

The subtractor 1413 performs a subtraction process on a combination of signals obtained by delaying the information signal series S ₀ (t) and the replica signal R _k (t) by the same time. When the subtractor 1413 is composed of N−1 stages, N subtraction results are obtained by performing such a subtraction process. The absolute value adder 1414 adds the absolute values of the N subtraction results and outputs the result as an error signal E _k (t).

FIG. 8 is a diagram illustrating the operation of the comparison operator 141 shown in FIG. FIG. 8 shows an example of the error signal output when N = 4 and the error calculator 14 receives the sine wave replica signal R _k (t) and the information signal sequence S ₀ (t). FIG. 8 shows that the sum a + b + c + d of the absolute values a, b, c, d (a, b, c, d ≧ 0) of the difference between the replica signal R _k (t) and the information signal sequence S ₀ (t) is an error. The signal E _k (t) is output. By taking such a method, the degree of difference in shape between the replica signal R _k (t) and the information signal sequence S ₀ (t) can be quantified.

The minimum value detector 15 shown in FIG. 1 detects the minimum value of N error signals E (t) (that is, E ₀ (t),..., E _N-1 (t)), and the error signal is detected. The minimum error number Z (t) corresponding to is output. Specifically, the minimum value detector 15 compares the magnitudes of the _N error signals E ₀ (t),..., E _N-1 (t), and detects the minimum error signal among them. . For example, when the detected minimum error signal is E _k (t), the minimum value detector 15 outputs the value k as the corresponding minimum error number Z (t). As already described, k is an arbitrary integer that satisfies 0 ≦ k ≦ N−1.

  FIG. 9 is a block diagram schematically showing a configuration example of the recombiner 16 shown in FIG. Recombiner 16 determines the amount of phase rotation of the information signal sequence according to the value of minimum error number Z (t), and outputs a signal obtained by phase-rotating the information signal sequence as preparation signal Q (t).

As shown in FIG. 9, the recombiner 16 includes an initial value selector 161 that determines an initial value J (t) of the preparation signal Q (t) according to the value of the minimum error number Z (t), and an information a plurality of delay devices 162 for delaying the signal sequence S _{0 (t)} in time, the information signal sequence S _{0 (t)} and which temporally delays based on the value of the initial value J (t) A time-division communicator 163 for selecting and outputting signals in a time-division manner. The plurality of delay units 162 are preferably configured by N-1 stages.

FIG. 10 is a diagram illustrating the operation of the recombiner 16 shown in FIG. FIG. 10 shows an output example of the preparation signal Q (t) when N = 4 and a sinusoidal signal is input to the recombiner 16 as the information signal series S ₀ (t). In the example shown in FIG. 10, it is assumed that the output J (t) of the initial value selector 161 is “1”, which is a control signal value associated with a phase rotation of π / 2. As shown in FIG. 10, the values p, q, r, and s of the information signal sequence S ₀ (t) corresponding to the period in which the output J (t) is “1” are transmitted from each delay unit 162 to the time-division communicator. 163 is input. The time division communication device 163 generates the preparation signal Q (t) by outputting the value p next to the values q, r, and s. By taking such a method, it is possible to output the preparation signal Q (t) obtained by rotating the phase of the information signal sequence S ₀ (t) according to the value of the minimum error number Z (t).

  FIG. 11 is a block diagram schematically showing a configuration example of the signal quality determiner 17 shown in FIG. The signal quality determiner 17 determines the reliability of the received signal by referring to the values of the error signal E (t) and the minimum error number Z (t), and outputs the feedback control signal G (t) according to the result. To do.

  As shown in FIG. 11, the signal quality determiner 17 includes a partial switch 171 that outputs a control signal P (t) corresponding to the value of the minimum error number Z (t), and a control that the partial switch 171 outputs. A switch 172 that switches the output of the signal to two signals according to the signal, an average calculator 173 that calculates an average value of one output of the switch 172, an output α and an average calculator of the other of the switch 172 A comparator 174 that compares the output β of 173 and a determiner 175 that determines the signal quality with reference to the output B (t) of the comparator 174 and outputs the feedback control signal G (t). .

  In the signal quality determiner 17, the partial switcher 171 outputs a control signal P (t) for selecting an error signal corresponding to the value of the minimum error number Z (t). The partial switcher 171 may output the minimum error number Z (t) as it is as the control signal P (t) for the purpose of realizing with a simple circuit or calculation.

  The switch 172 outputs one of the error signals E (t) corresponding to the control signal P (t) as the signal α, and outputs other N−1 types of error signals to the average calculator 173. The average calculator 173 calculates an average value of the inputted N−1 types of error signals and outputs this as a signal β.

FIG. 12 is a diagram showing the operation of the signal quality determiner 17 shown in FIG. FIG. 12 shows an operation example of the switch 172 when P (t) = k (where 0 ≦ k ≦ N−1). As shown in FIG. 12, the switch 172 outputs the k-th error signal E _k (t) as a signal α corresponding to the value k of the control signal P (t). Further, switching device _{172, E} k (t) other than the N-1 type of error signal _{E 0 (t), ...,} E k-1 (t), E k + 1 (t), ..., E N-1 ( t) is output to the average calculator 173. The average calculator 173, the error signal _{E 0 (t), ...,} E k-1 (t), E k + 1 (t), ..., and outputs the average value of _{E N-1} (t) as the signal beta.

  The comparator 174 compares the magnitudes of the signals α and β and outputs the comparison result B (t). As the simplest configuration, the comparator 174 can be configured to output a value obtained by subtracting the signal α from the signal β. The determiner 175 compares the comparison result B (t) with a predetermined value and outputs a feedback control signal G (t) based on the comparison result.

  FIG. 13 is a block diagram schematically showing a configuration example of the determiner 175 shown in FIG. As illustrated in FIG. 13, the determination unit 175 includes a normalization unit 1751, a plurality (M systems) of code determination units 1752, and a normalization adder 1753. The normalizing unit 1751 normalizes the output B (t) of the comparator 174. It is desirable that the normalization range in the normalization unit 1751 is a range from “0” to “1”.

  The output of the normalization unit 1751 is input to the M system code determination unit 1752. The sign determination unit 1752 compares the output of the normalization unit 1751 with a predetermined value, and outputs “1” if the comparison result is a non-negative value, and outputs “0” if the comparison result is a negative value. It is desirable that the M types of predetermined values input to the M system code determination unit 1752 are all different values. The M types of predetermined values input to the M system code determination unit 1752 are, for example, M types of values excluding “1” among M + 1 types of values obtained by equally dividing the values from “0” to “1” into M. A value is desirable. However, the M types of predetermined values are not limited to such values.

  The output of the M system code determination unit 1752 is input to the normalized adder 1753. The normalized adder 1753 calculates the sum of the outputs of the M system code determiners 1752 and outputs a value obtained by dividing the sum by the value M as the feedback control signal G (t). By adopting such a configuration, the value of the feedback control signal G (t) becomes a value between “0” and “1”, and the output B (t) of the comparator 174 is a large value. The closer the value is to “1”.

  FIG. 14 is a block diagram schematically showing a configuration example of the feedback controller 18 shown in FIG. As shown in FIG. 14, the feedback controller 18 includes a multiplication unit 182 that multiplies the preparation signal Q (t) by a predetermined ratio R of 0 or more and 1 and a ratio (1-R) of the reference selection signal Y (t). ) And an adder 184 for adding the output of the multiplier 182 and the output of the multiplier 183. The feedback controller 18 adds the reference selection signal Y (t) and the preparation signal Q (t) at a predetermined ratio R based on the value of the feedback control signal, and outputs the result as a reference correction signal F (t). At this time, as the ratio R, for example, the value of G (t) may be used as it is.

  As described above, by using the receiving apparatus 10 of the first embodiment, the reliability of the received signal is determined with reference to the values of the error signal E (t) and the minimum error number Z (t). The replica signal can be corrected while controlling the magnitude of the feedback control signal G (t) according to the result. For this reason, by using the receiving apparatus 10, the signal quality of the replica signal used when decoding the received signal can be efficiently improved, and the accuracy of decoding the received signal can be improved.

FIG. 15 is a diagram for explaining the effect of the receiving device 10 according to the first embodiment. FIG. 15 shows an example of the output of the error calculator 14 when the reception environment is good and when the reception environment is bad, in order to explain the effect of the first embodiment more specifically. In FIG. 15, it is assumed that N = 4, the replica signal is correctly generated, and the information signal sequence S ₀ (t) has a phase of π / 2 with respect to the replica signal R ₀ (t) that does not perform phase rotation. Assume that the signal is advanced.

As shown in FIG. 15, when the reception environment is good, errors obtained by comparing the four types of replica signals R ₀ (t),..., R ₃ (t) with the information signal sequence S ₀ (t). The signal E (t) (that is, E ₀ (t), E ₁ (t), E ₂ (t), E ₃ (t)) has a small value only for the error signal E ₁ (t), and other errors. The signals E ₀ (t), E ₂ (t), and E ₃ (t) are very large values compared to the error signal E ₁ (t).

On the other hand, in FIG. 15, when the reception environment is poor, the error signal E obtained by comparing the four types of replica signals R ₀ (t),..., R ₃ (t) with the information signal sequence S ₀ (t). (T) (that is, E ₀ (t), E ₁ (t), E ₂ (t), E ₃ (t)) are all large values. Therefore, the difference between the error signal E ₁ (t) and the other error signals E ₀ (t), E ₂ (t), E ₃ (t) becomes small.

At this time, since the minimum value detector 15 can detect the error signal E ₁ (t) as the minimum value in any reception environment, the recombiner 16 can detect the combination corresponding to the correct phase rotation amount. It is possible to output the prepared signal Q (t) that has been changed.

  However, if the preparation signal Q (t) is added at the same ratio as the reference selection signal Y (t) to generate the reference correction signal F (t), the quality deteriorates if the reception environment is poor. Since the information signal sequence is fed back, the quality of the replica signal may greatly deteriorate. Further, since signal processing such as error calculation is performed again using such a degraded replica signal, the reliability of the replica signal may be further degraded.

On the other hand, in the receiving apparatus 10 according to the first embodiment, the signal quality determiner 17 determines the quality of the received signal. That is, the signal quality determiner 17 compares the error signal E ₁ (t) with the average value of the other error signals, and the comparison result is large when the reception environment is good and the reception environment is poor. In such cases, it becomes smaller. Therefore, according to the comparison result, the feedback control signal G (t) is close to “1” when the reception environment is good, and close to “0” when the reception environment is poor.

  Further, the feedback controller 18 gives weights (that is, ratios R and (1-R)) to the reference selection signal Y (t) and the preparation signal Q (t) according to the value of the feedback control signal G (t). It has a function. Therefore, in receiving apparatus 10 of Embodiment 1, a large weight is given to preparation signal Q (t) when the reception environment is good, and a large weight is given to reference selection signal Y (t) when the reception environment is poor. As a result, the update amount of the replica signal can be adaptively changed according to the signal quality.

  As described above, according to the receiving apparatus 10 of the first embodiment, a coefficient based on the reliability of the demodulated signal is given to the received signal, and this is cumulatively added to the reference signal, so that only the highly reliable received signal is obtained. The replica signal can be updated by using it, and as a result, the signal quality of the replica signal can be improved efficiently.

  Moreover, according to the receiving apparatus 10 of Embodiment 1, the diversity effect is acquired by accumulating the received signal with respect to the reference signal. For this reason, irrespective of the signal level of the thermal noise component and impulsive noise included in the reference signal, these effects can be reduced, and the signal quality of the replica signal can be improved.

  Furthermore, according to the receiving apparatus 10 of the first embodiment, when the determination level number M in the determiner 175 is a power of 2, all signal processing for correcting the replica signal is performed by adding, subtracting, comparing, and combining signals. In other words, since it is limited to switching, the circuit scale and operation scale can be reduced. For this reason, the receiving apparatus 10 according to the first embodiment can be easily applied to a communication system in which the circuit scale and the operation scale are limited.

Embodiment 2. FIG.
FIG. 16 is a block diagram showing a configuration of receiving apparatus 20 according to the second embodiment of the present invention. In FIG. 16, the same reference numerals are given to the same or corresponding components as those of the receiving apparatus 10 (Embodiment 1) shown in FIG. In the receiving apparatus 20 of the second embodiment shown in FIG. 16, the input of the signal quality determiner 27 is an error signal E (t), a minimum error number Z (t), a reference selection signal Y (t), and a preparation signal. Q (t) is different from the receiving apparatus 10 of the first embodiment in which the signal quality determiner 17 (FIG. 1) inputs only the error signal E (t) and the minimum error number Z (t).

  FIG. 17 is a block diagram illustrating a configuration of the signal quality determiner 27 that configures the receiving device 20. In FIG. 17, the same reference numerals are given to the same or corresponding components as those of the signal quality determiner 17 (Embodiment 1) shown in FIG. The signal quality determiner 27 according to the second embodiment determines that the output B (t) of the comparator 174, the reference selection signal Y (t), and the preparation signal Q (t) are input to the determiner 275. This is different from the determination unit 175 (FIG. 11) of the first embodiment in which only the output B (t) of the comparator 174 is input to the unit 175.

FIG. 18 is a block diagram schematically showing the configuration of the determiner 275 shown in FIG. In FIG. 18, the same reference numerals are given to the same or corresponding components as those of the determiner 175 (Embodiment 1) shown in FIG. 13. The determiner 275 in the second embodiment is different from the determiner 175 (FIG. 13) in the first embodiment in that a protector 2754 is provided. The protector 2754 receives the output of the normalized adder 1753, the reference selection signal Y (t), and the preparation signal Q (t). Protector 2754 refers to the criteria selection signal Y (t) and the preparation signal Q (t), to determine whether the control signal output, and outputs the result as a feedback control signal G (t).

  Specifically, the protector 2754 monitors the difference in magnitude or phase rotation amount between the reference selection signal Y (t) and the preparation signal Q (t), and when the difference is larger than a predetermined value, feedback control is performed. When the signal G (t) is “0” and the difference is equal to or smaller than a predetermined value, the feedback control signal G (t) is output from the normalized adder 1753.

FIG. 19 is a diagram for explaining the effect of the receiving device 20 according to the second embodiment. FIG. 19 shows the output of error calculator 14 in a case where the reception environment is good and a reception environment affected by impulsive noise, in order to explain the effect of Embodiment 1 more specifically. In FIG. 19, it is assumed that N = 4, the replica signal is correctly generated, and the information signal sequence S ₀ (t) has a phase of π / 2 with respect to the replica signal R ₀ (t) that does not perform phase rotation. Assume that the signal is advanced.

As shown in FIG. 19, when the reception environment is good, an error obtained by comparing the four types of replica signals R ₀ (t),..., R ₃ (t) with the information signal sequence S ₀ (t). The signal E (t) (that is, E ₀ (t), E ₁ (t), E ₂ (t), E ₃ (t)) has a small value only for the error signal E ₁ (t), and other errors. The signals E ₀ (t), E ₂ (t), and E ₃ (t) are very large values compared to the error signal E ₁ (t).

On the other hand, in FIG. 19, when the reception environment is affected by impulsive noise, four types of replica signals R ₀ (t),..., R ₃ (t) are compared with the information signal sequence S ₀ (t). error signal E (t) _{(i.e., E 0 (t), E} 1 (t), E 2 (t), E 3 (t)) obtained by the error signal _E 2 (t) is relatively small May occur.

At this time, if the reception environment is affected by the impulsive noise, the minimum value detector 15 detects the error signal E ₂ (t) as the minimum value, and the recombiner 16 sets the erroneous phase rotation amount. A preparation signal Q (t) subjected to the corresponding recombination is output.

When signal quality determiner 17 of receiving apparatus 10 of Embodiment 1 is used, error signal E ₂ (t) is determined to be a relatively reliable signal, and feedback control signal G (t) is set to a large value. Therefore, the influence of impulsive noise may be fed back to the reference signal.

  On the other hand, if the configuration of the receiving device 20 of the second embodiment is adopted, a signal output propriety determination by the protector 2754 is performed before the feedback control signal G (t) is output. Specifically, the receiving device 20 of the second embodiment constantly monitors the difference between the reference selection signal Y (t) and the preparation signal Q (t), and when this difference becomes a value larger than a predetermined value. The feedback amount can be set to “0”.

  Assuming that decoding of the received signal is always accurate, the difference between the reference selection signal Y (t) and the preparation signal Q (t) is ideally always constant and has the same sign. On the other hand, if the received signal is erroneously decoded due to the influence of impulsive noise, the difference between the reference selection signal Y (t) and the preparation signal Q (t) may increase instantaneously. The receiving apparatus 20 according to the second embodiment can temporarily stop the update of the replica signal by detecting such an influence.

  Therefore, according to the receiving apparatus 20 of the second embodiment, by giving a coefficient based on the reliability of the demodulated signal to the received signal and referring to the phase change of the demodulated signal when cumulatively adding it to the reference signal, Impulsive noise can be detected and its influence can be reduced, and the signal quality of the replica signal can be improved.

Embodiment 3 FIG.
FIG. 20 is a block diagram schematically showing a configuration of receiving apparatus 30 according to the third embodiment of the present invention. 20, the same reference numerals are given to the same or corresponding components as those shown in FIG. 1 (Embodiment 1). The receiving apparatus 30 according to the third embodiment is different from the receiving apparatus 10 according to the first embodiment in the configuration of the signal quality determiner 37.

  FIG. 21 is a block diagram schematically showing a configuration example of the signal quality determiner 37 shown in FIG. In FIG. 21, the same reference numerals are given to the same or corresponding components as those shown in FIG. 11 (Embodiment 1). In the signal quality determiner 37 according to the third embodiment, the comparator 374 compares the signal α selected according to the output of the partial switch 171 with the other error signals of the N-1 system, and compares them. The point at which the result is output as B (t) is that the comparator 374 determines the average value β (average calculation) of the signal α selected in accordance with the output of the partial switch 171 and the other N−1 error signals. And the signal quality determiner 17 (FIG. 11) that outputs the comparison result.

FIG. 22 is a diagram for explaining the effect of the receiving device 30 according to the third embodiment. FIG. 22 shows an example of the output of the error calculator 14 in two types of reception environments in order to explain the effect of the third embodiment more specifically. In FIG. 22, it is assumed that N = 4, the replica signal is correctly generated, and the information signal sequence S ₀ (t) has a phase of only π / 2 with respect to the replica signal R ₀ (t) that does not perform phase rotation. Assume that the signal is advanced.

As shown in FIG. 22, in any reception environment, the minimum value of the error signal is E ₁ (t), but other error signals E ₀ (t), E ₂ (t), E ₃ ( The average value of t) is almost the same value in any reception environment. Therefore, when the signal quality determiner 17 (FIG. 11) as shown in the first embodiment is used, it is assumed that the reliability is the same in any reception environment, and the feedback control signal G having the same degree is used. (T) is output.

However, since it is clear that the reliability of the received signal with respect to the error signal E ₁ (t) is higher in the reception environment shown on the right side of FIG. 22, it is possible to obtain a higher accuracy by distinguishing these reliability levels. The feedback control signal G (t) can be selected. If the signal quality determiner 37 in the third embodiment is employed, the error signal is not averaged, and each error signal is compared with the signal α in the comparator 374. Therefore, the above highly accurate feedback control is performed. Selection of the signal G (t) can be realized.

  The signal quality determiner 37 in the third embodiment corresponds to the signal quality determiner 17 (FIG. 11) of the first embodiment except that the average calculator 173 is omitted, but the signal quality determiner in the third embodiment. The unit 37 may be configured by omitting the average calculator 173 from the signal quality determiner 27 (FIG. 17) of the second embodiment.

Embodiment 4 FIG.
FIG. 23 is a block diagram schematically showing a configuration of receiving apparatus 40 according to the fourth embodiment of the present invention. 23, the same reference numerals are given to the same or corresponding components as those shown in FIG. 16 (Embodiment 2). The receiving device 40 of the fourth embodiment is different from the receiving device 20 of the second embodiment in the configuration of the feedback controller 48.

  FIG. 24 is a block diagram schematically showing the configuration of the feedback controller 48 shown in FIG. The feedback controller 48 according to the fourth embodiment includes means 481 for giving a predetermined value W, means 482 for multiplying the preparation signal Q (t) by the value WR, and a value (1-WR) for the reference selection signal Y (t). Is provided with a means 483 for multiplying the output of the means 482 and an adder 484 for adding the output of the means 483, the means 182 for multiplying the preparation signal Q (t) by the ratio R, and the reference selection signal Y This is different from the feedback controller 18 shown in FIG. 14 which includes means 183 for multiplying (t) by the ratio (1-R), and an adder 184 for adding the output of means 182 and the output of means 183. .

  In the feedback controller 48 according to the fourth embodiment, the maximum value of the feedback amount of the preparation signal can be freely set by setting the predetermined value W to an appropriate value according to the communication system. However, it is desirable that the predetermined value W is a value included between “0” and “1”. The predetermined value W may be a fixed value that does not change over time, or may be a value that is variably controlled according to time.

  By employing the feedback controller 48 as in the fourth embodiment, the stability and followability of the communication system can be freely controlled. More specifically, it is possible to provide a communication system in which followability is emphasized as the predetermined value W is set larger, and a communication system in which stability is emphasized as the predetermined value W is set smaller.

  Therefore, when the receiving device 40 according to the fourth embodiment gives a coefficient based on the reliability of the demodulated signal to the received signal, the coefficient can be controlled automatically or manually, and the stability and followability can be improved accordingly. Since it can be controlled, a flexible design of the communication system can be performed.

  Further, the same effect can be obtained by replacing the feedback controller 18 in the configuration shown in the second embodiment with the feedback controller 48 shown in the fourth embodiment.

  The contents of Embodiments 1 to 4 exemplify aspects applicable to the receiving apparatus according to the present invention, and the present invention is not limited to these.

  10, 20, 30, 40 Receiver, 11 Input selector, 12 Selector, 13 Phase shifter, 14 Error calculator, 15 Minimum value detector, 16 Recombiner, 17, 27 Signal quality determiner, 18, 48 feedback controller, 141 comparison operation unit, 1411 delay unit, 1412 delay unit, 1413 subtractor, 1414 absolute value adder, 161 initial value selector, 162 delay unit, 163 time division communication unit, 171 partial switch unit, 172 Switcher, 173 average calculator, 174 comparator, 175 determiner, 1751 normalizer, 1752 sign determiner, 1753 normalized adder, 275 determiner, 2754 protector, 374 comparator, 481 predetermined value.

Claims (10)

An input switch that receives a reference signal and a reference correction signal detected from a synchronization signal sequence in the received signal sequence, and selectively outputs either the reference signal or the reference correction signal as a reference selection signal; ,
A selector that outputs a selection signal that causes the input selector to selectively output either the reference signal or the reference correction signal as the reference selection signal;
A phase shifter that rotates the phase of the reference selection signal and outputs a replica signal of N systems (N is an integer of 2 or more);
An error calculator that compares the information signal sequence in the received signal sequence with the N replica signals and outputs an N error signal based on a result of the comparison;
A minimum value detector for detecting a minimum value among the N error signals and outputting a minimum error number corresponding to the detected error signal of the minimum value;
A recombination unit for outputting a preparation signal generated by rotating the phase of the information signal sequence according to the value of the minimum error number;
Analyzing the error signal according to the value of the minimum error number, and generating a feedback control signal based on the result of the analysis;
A feedback controller that updates the reference correction signal by weighting the preparation signal and the reference selection signal based on the value of the feedback control signal and supplies the updated reference correction signal to the input switch And a receiving device. An input switch that receives a reference signal and a reference correction signal detected from a synchronization signal sequence in the received signal sequence, and selectively outputs either the reference signal or the reference correction signal as a reference selection signal; ,
A selector that outputs a selection signal that causes the input selector to selectively output either the reference signal or the reference correction signal as the reference selection signal;
A phase shifter that rotates the phase of the reference selection signal and outputs a replica signal of N systems (N is an integer of 2 or more);
An error calculator that compares the information signal sequence in the received signal sequence with the N replica signals and outputs an N error signal based on a result of the comparison;
A minimum value detector for detecting a minimum value among the N error signals and outputting a minimum error number corresponding to the detected error signal of the minimum value;
A recombination unit for outputting a preparation signal generated by rotating the phase of the information signal sequence according to the value of the minimum error number;
Analyzing the error signal according to the reference selection signal, the preparation signal, and the value of the minimum error number, and generating a feedback control signal based on a result of the analysis;
A feedback controller that updates the reference correction signal by weighting the preparation signal and the reference selection signal based on the value of the feedback control signal and supplies the updated reference correction signal to the input switch And a receiving device. The phase shifter generates N replica signals.
The N replica signals are
The reference selection signal;
The phase of the reference selection signal is 2π × (k / N) (k = 1, 2,..., N−1)
The receiving apparatus according to claim 1, further comprising: a rotated N-1 system signal. The recombiner determines a phase rotation amount according to the minimum error number, and rotates the phase of the information signal sequence based on the phase rotation amount to generate the preparation signal. The receiving device according to any one of 1 to 3. The signal quality determiner is
A switch that divides the N error signals into a first error signal corresponding to the minimum error number and an N-1 second error signal other than the first error number;
A comparator for comparing the second error signal of the N-1 system with the first error signal;
The receiving apparatus according to claim 1, further comprising: a determination unit that performs determination based on the comparison result and outputs a signal corresponding to the determination result as the feedback control signal. The signal quality determiner is
A switch that separates the N error signals from a first error signal corresponding to the minimum error number and N-1 second error signals other than the first error number;
A comparator for comparing the second error signal of the N-1 system with the first error signal;
A determination unit that makes a determination based on a result of the comparison with reference to values of the reference selection signal and the preparation signal, and outputs a signal corresponding to the determination result as the feedback control signal. The receiving device according to claim 2. The determiner is
The M code determination that compares the value according to the output value of the comparator with M (M is an integer of 2 or more) predetermined values and outputs a value 1 or 0 according to the result of the comparison And
The receiving apparatus according to claim 5, further comprising: a normalizing adder that normalizes and adds the outputs of the M systems of the code determination units and outputs a result of the addition as the feedback control signal. The feedback controller is
A predetermined ratio is determined according to the value of the feedback control signal,
The receiving apparatus according to any one of claims 1 to 7, wherein a signal obtained by adding the preparation signal and the reference selection signal at the predetermined ratio is output as the reference correction signal. The feedback controller is
Hold a certain value,
A predetermined ratio is determined according to the value of the feedback control signal and the predetermined value,
The receiving apparatus according to any one of claims 1 to 7, wherein a signal obtained by adding the preparation signal and the reference selection signal at the predetermined ratio is output as the reference correction signal. An output switch for branching the received signal sequence into the information signal sequence and the synchronization signal sequence;
The receiving apparatus according to claim 1, further comprising: a reference signal detector that detects the reference signal from the synchronization signal sequence.

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