JP5489880B2 - Central processing unit, control system, and port setting method - Google Patents

Description

  The present invention relates to a central processing unit, a control system, and a port setting method, and relates to a central processing unit that performs weight processing for temporarily stopping processing when a wait signal is input to a weight terminal, and the central processing unit The present invention relates to a control system including a device and a port setting method implemented by the central processing unit.

  In recent years, with the improvement in performance of a central processing unit (hereinafter referred to as CPU), a single CPU controls a plurality of external devices. For example, a control system shown in FIG. 3 has been proposed as a CPU for controlling a plurality of external devices.

  As shown in the figure, the control system 1 includes a CPU 2 that controls the entire system. The CPU 2 operates by receiving power from the power source 3. An input I / F 4 is connected to the port P1 of the CPU 2, and the measurement values of various sensors mounted on the vehicle and the operation states of the operation means are input.

  Further, a stepper control IC 5, an LED control IC 6, an LCD controller IC 7, and a CAN communication I / FIC 8 as external devices are connected to the plurality of ports P 2 to P 5 of the CPU 2. The stepper control IC 5 is an IC that controls the driving of stepper motors 51 and 52 that move the pointers of a speedometer and a tachometer mounted on the vehicle.

  The LED control IC 6 is an IC that controls the lighting of the LEDs 61 and 62. The LCD controller IC 7 is an IC that controls display on the LCD 71. The CAN communication I / FIC 8 is an IC for performing CAN communication in the vehicle. The CPU 2 controls the operations of the ICs 5 to 8 according to, for example, the measurement values of various sensors input from the input I / F 4 and the operation state of the operation means.

  By the way, an external device having a slower processing speed than the CPU 2 itself, such as the LCD controller IC 7, may be connected to the CPU 2 described above. As described above, when the processing speed of the CPU 2 is much higher than the processing speed of the LCD controller IC 7, processing of data transmitted from the CPU 2 by the LCD controller IC 7 may not be in time.

  Therefore, when the data processing is not in time, the LCD controller IC 7 outputs a high-level wait signal to the wait terminal T1 of the CPU 2. Further, it is considered that when a wait signal at H level is input to the wait terminal T1, the CPU 2 is caused to perform a wait operation to temporarily stop processing and stop data processing for the LCD controller IC7.

  While the wait signal is input to the wait terminal T1, the CPU 2 preferentially waits for the release of the wait operation, so that nothing can be processed, and processing for controlling the other ICs 5, 6, and 8 is also stopped. . Normally, there is no problem since the output of the wait signal is immediately stopped by the LCD controller IC7, but there is no problem, but the wait terminal T1 may be constant at Hi for some reason. In this case, there is a problem in that the wait operation of the CPU 2 is not released and not only the control of the LCD controller IC 7 but also the control of the other ICs 5, 6, 8 are stopped.

WO98 / 38571

  Therefore, the present invention provides an arithmetic processing device capable of controlling an external device other than a low-speed external device that outputs a wait signal even when a signal abnormality occurs and the wait operation continues, and the arithmetic processing device It is an object of the present invention to provide a port setting method implemented by a control system and a central processing unit including

  The invention according to claim 1 for solving the above-described problem is a central processing unit that performs control processing for controlling a plurality of external devices, and includes a plurality of ports respectively connected to the plurality of external devices; Among the plurality of external devices, a wait terminal to which a wait signal is input from a low-speed external device whose processing capability is slower than that of the central processing unit, and the control process is stopped when the wait signal is input to the wait terminal In a central processing unit comprising weight means for performing weight processing and port setting means for setting the plurality of ports and the weight terminal at the time of rising, a weight signal is input to the weight terminal at the time of rising. The port setting means sets the port connected to the low-speed external device and the weight terminal. It lies in a central processing unit, characterized in that to set except the port which is connected to the low-speed external device among the plurality of ports without.

  According to a second aspect of the present invention, the port setting means sets all of the plurality of ports and the weight terminal when no wait signal is input to the weight terminal at the time of rising. It exists in the central processing unit of item 1.

  The invention according to claim 3 periodically communicates with the central processing unit according to claim 1 or 2 with the central processing unit, and resets the central processing unit when communication cannot be performed for a certain time or more. A control system comprising a watchdog timer.

The invention according to claim 4 is a central processing unit that performs a control process for controlling a plurality of external devices, and a plurality of ports respectively connected to the plurality of external devices, and of the plurality of external devices, the A weight terminal for inputting a weight signal from a low-speed external device having a processing capacity slower than that of the central processing unit, and a weight means for performing a weight process for stopping the control processing when the weight signal is input to the weight terminal; In the port setting method of the central processing unit having the above, when a wait signal is input to the weight terminal at the time of start-up, the port connected to the low-speed external device and the weight terminal are not set. In the port setting method, the setting is performed except for a port connected to the low-speed external device among the plurality of ports. To do.

  As described above, according to the first and fourth aspects of the invention, when a wait signal is input to the weight terminal at the time of rising, it is determined that the signal is abnormal, and the port and the weight connected to the low-speed external device Do not set the terminal, but set the ports except those connected to low-speed external devices. As a result, even if some signal abnormality occurs and the wait operation continues, only the control of the low speed external device and the wait operation are stopped, and the control of the external device other than the low speed external device can be performed.

  According to the second aspect of the present invention, when no wait signal is input to the weight terminal at the time of rising, the port setting means sets all of the plurality of ports and the weight terminal. External device control and wait operation can be performed.

  According to the third aspect of the present invention, the watchdog timer periodically communicates with the central processing unit, and resets the central processing unit when the wait operation continues and communication cannot be performed for a predetermined time or longer. As a result, when some signal abnormality occurs and the wait operation continues, the watchdog timer resets the central processing unit and starts up, so control of external devices other than low-speed external devices is automatically restored. be able to.

It is a block diagram which shows one Embodiment of the control system incorporating CPU and information processing apparatus of this invention. It is a flowchart which shows the port setting process sequence at the time of initialization of CPU shown in FIG. It is a block diagram which shows an example of the control system incorporating the conventional CPU.

  Hereinafter, a central processing unit (CPU), a control system, and a port setting method according to the present invention will be described with reference to FIGS. As shown in the figure, the control system 1 incorporating the CPU 2 of the present invention is connected to a stepper control IC 5, LED control IC 6, LCD controller IC 7 and CAN communication I / FIC 8 as a plurality of external devices. And a watchdog timer (hereinafter referred to as W / D) 10 that resets the CPU 2 when it communicates with the CPU 2 periodically and cannot communicate for a certain period of time.

  The stepper control IC 5 is an IC that controls the driving of stepper motors 51 and 52 that move the pointers of a speedometer and a tachometer mounted on the vehicle. The LED control IC 6 is an IC that controls lighting of the LEDs 61 and 62 mounted on the vehicle. The LCD controller IC 7 is an IC that controls display on the LCD 71. The CAN communication I / FIC 8 is an IC for performing CAN communication in the vehicle.

  The LCD controller IC 7 described above is a low-speed external device whose processing capability is slower than that of the CPU 2 to be described later. If the processing of data transmitted from the CPU 2 is not in time, a wait signal is output to temporarily stop the operation of the CPU 2. Stop sending data.

  The CPU 2 operates by receiving power from the power source 3. The CPU 2 is provided with a plurality of ports P1 to P6, a wait terminal T1, a reset terminal T2, and a refresh terminal T3. An input I / F 4 is connected to the port P1, and measurement values of various sensors mounted on the vehicle and operation states of operation means are input to the CPU 2.

  The stepper control IC 5 is connected to the port P2. The CPU 2 controls the stepper control IC 5 by outputting a drive control signal from the port P2 to the stepper control IC 5. The LED control IC 6 is connected to the port P3. The CPU 2 controls the LED control IC 6 by outputting a lighting control signal from the port P3 to the LED control IC 6.

  The LCD controller IC 7 is connected to the port P4. The CPU 2 controls the LCD controller IC 7 by transmitting data to be displayed on the LCD 71 to the LCD controller IC 7 from the port P4. A CAN communication I / FIC 8 is connected to the ports P5 and P6. The CPU 2 outputs transmission data from the port P5 to the CAN communication I / FIC 8 and inputs reception data from the CAN communication I / FIC 8 from the port P6 to control the CAN communication I / FIC 8.

  Further, the LCD controller IC7 is connected to the weight terminal T1, and a high-level wait signal output from the LCD controller IC7 is input. When the wait terminal T1 becomes Hi level by the input of the wait signal, the CPU 2 performs a so-called wait operation that functions as a wait means and stops the operation for a predetermined clock. During this wait operation, the CPU 2 cannot perform any processing, so control of all the ICs 5 to 7 is stopped.

  Further, the W / D 10 is connected to the refresh terminal T2 and the reset terminal T3. The CPU 2 periodically outputs a refresh signal from the refresh terminal T2 while the process is normally performed. The refresh signal cannot be output when the CPU 2 cannot process anything, such as when the CPU 2 runs out of control or performs a wait operation.

  The W / D 10 is reset with respect to the reset terminal T3 when the runaway of the CPU 2 or the wait signal abnormality occurs and the wait operation continues and the state where the refresh signal is not output from the refresh terminal T2 continues for a certain time or more. Output a signal.

  When the reset signal is input from the reset terminal T3, the CPU 2 forcibly ends the process, starts up again, and returns to the initial state. A ROM (not shown) is connected to the CPU 2. The ROM stores an initialization program including port setting processing and the like, and control programs for the ICs 5 to 6. The CPU 2 reads an initialization program from a ROM (not shown) at the time of start-up such as reset or power-on and executes initialization, and then reads the control program and executes control of the IC.

  The operation of the control system 1 configured as described above will be described below with reference to the flowchart of FIG. First, when starting up such as reset or power-on, the CPU 2 executes an initialization program recorded in the ROM to perform initialization. The CPU 2 functions as a port setting means, and executes the port setting process shown in FIG. 2 in this initialization. First, the CPU 2 performs port settings of the ports P1 to P3, P5, and P6 except for the port P4 connected to the LCD controller IC 7 among the plurality of ports P1 to P6, and the reset terminal T2 and the refresh terminal T3 (step S1). ). At this time, the CPU 2 performs port setting as a simple input / output terminal for the weight terminal T1.

  Next, the CPU 2 turns on the power of the ICs 5 to 8 (step S2). Thereafter, the CPU 2 confirms the state of the weight terminal T1 (step S3). When no abnormality of the wait signal has occurred, a high-level wait signal is not output from the LCD controller IC 7 at the time of rising. If the wait terminal T1 is at the Lo level (Y in step S4), the CPU 2 determines that no abnormality of the wait signal has occurred, sets the port P4 connected to the LCD controller IC 7, and sets the wait terminal. After setting the wait function at T1 (step S5), the process is terminated.

  Therefore, when no abnormality of the wait signal has occurred, all the ports P1 to P6 are set, and in the control program executed following the initialization program, all the ICs 5 to 8 are controlled and the wait operation is performed. Can do.

  During the execution of the control program, the CPU 2 periodically outputs a refresh signal from the refresh terminal T3. Further, when the wait signal is output from the LCD controller IC 7 without processing the data transmitted from the CPU 2 in time during execution of the control program, the CPU 2 performs a wait operation for stopping the operation for a predetermined clock. During the wait operation, the CPU 2 is in a state where it cannot process anything, and not only the output of the refresh signal and the transmission of data to the LCD controller IC 7 but also the control of all the ICs 5, 6, 8 is stopped.

  Normally, since the output of the wait signal from the LCD controller IC 7 is stopped immediately, the CPU 2 cancels the wait operation and restarts the control process for each of the ICs 5 to 8. However, if some abnormality occurs and the wait terminal T1 remains in the Hi level state and the wait operation of the CPU 2 is not released and the refresh signal is not output for a predetermined time or longer, the W / D 10 detects this and resets it. A reset signal is output to the terminal T2 to reset the CPU2.

  When reset, the CPU 2 executes the initialization program recorded in the ROM again to perform initialization, and the port setting process shown in FIG. 2 is executed. In this port setting process, the CPU 2 performs steps S1 to S3 as in the normal state as described above. As described above, if the wait signal is abnormal and the wait terminal T1 is at the Hi level even at the rising edge (N in step S4), the CPU 2 sets the port P4 connected to the LCD controller IC 7 and the wait terminal. The process is immediately terminated without setting the wait function at T1.

  Therefore, even when a wait signal abnormality occurs, port settings other than the port P4 connected to the LCD controller IC 7 among the ports P1 to P6 are set, and the control program executed following the initialization program uses the LCD. Although the controller IC 7 cannot be controlled, the ICs 5, 6, and 8 other than the LCD controller IC 7 can be controlled.

  According to the above-described embodiment, when a wait signal is input to the wait terminal T1 at the time of rising, it is determined that the signal is abnormal, and the port P4 connected to the LCD controller IC 7 and the wait terminal T1 are not set. Setting is performed except for the port P4 connected to the LCD controller IC 7 among the plurality of ports P1 to P6. As a result, even if some signal abnormality occurs and the wait operation continues, only the control of the LCD controller IC 7 and the wait operation are stopped, and the control of the ICs 5, 6, 8 which are external devices other than the LCD controller IC 7 is controlled. It can be carried out.

  Further, according to the above-described embodiment, when no wait signal is input to the wait terminal T1 at the time of rising, the CPU 2 sets all of the plurality of ports P1 to P6 and the wait terminal T1. All ICs 5 to 8 can be controlled and the wait operation can be performed.

  Further, according to the above-described embodiment, the W / D 10 periodically communicates with the CPU 2 and resets the CPU 2 when the wait operation continues and communication cannot be performed for a predetermined time or longer. As a result, when some signal abnormality occurs and the wait operation is continued, the W / D 10 is reset and started up by the CPU 2, so that the control of the ICs 5, 6, 8 other than the LCD controller IC 7 is automatically restored. be able to.

  According to the above-described embodiment, after the ports P1 to P3 and P5 to P8 other than the port P4 are first set in the port setting process, the state of the wait terminal T1 is confirmed and the wait signal is output. For example, the port P4 and the weight terminal T1 are set. However, the present invention is not limited to this. For example, in the port setting process, after first confirming the wait terminal T1, if the wait signal is not output, the ports P1 to P6 are set. If the wait signal is output, the port P1 excluding the port P4 is set. -P3 and P5-P8 may be set.

  Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

1 control system 2 CPU (central processing unit, weight means, port setting means)
5 Stepper control IC (external device)
6 LED control IC (external device)
7 LCD controller IC (low speed external device)
8 CAN communication I / FIC (external equipment)
10 Watchdog timer T1 Wait terminal P1 to P6 port

Claims (4)

A central processing unit that performs control processing for controlling a plurality of external devices, and a plurality of ports respectively connected to the plurality of external devices, and a processing capability of the plurality of external devices than the central processing unit A wait terminal to which a wait signal from a slow low-speed external device is input; wait means for performing a wait process for stopping the control process when the wait signal is input to the wait terminal; In a central processing unit comprising a port setting means for setting the weight terminal,
When a wait signal is input to the weight terminal at the time of rising, the port setting means does not set the port connected to the low-speed external device and the weight terminal, and the low-speed among the plurality of ports. A central processing unit that performs settings except for ports connected to external devices. 2. The central processing unit according to claim 1, wherein, when a wait signal is not input to the weight terminal at the time of rising, the port setting unit sets all of the plurality of ports and the weight terminal. apparatus. The central processing unit according to claim 1 or 2,
A watchdog timer that periodically communicates with the central processing unit, and resets the central processing unit when communication is not possible for a certain period of time,
A control system characterized by comprising: A central processing unit that performs control processing for controlling a plurality of external devices, and a plurality of ports respectively connected to the plurality of external devices, and a processing capability of the plurality of external devices than the central processing unit A central processing unit comprising: a weight terminal for inputting a wait signal from a slow low-speed external device; and weight means for performing a weight process for stopping the control process when the weight signal is input to the weight terminal In the port setting method of
When a wait signal is input to the weight terminal at the time of rising, the port connected to the low-speed external device and the low-speed external device among the plurality of ports are connected without setting the weight terminal. A port setting method, characterized in that settings are made excluding ports.

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