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JP5491602B2 - Semiconductor device - Google Patents
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JP5491602B2 - Semiconductor device - Google Patents

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JP5491602B2
JP5491602B2 JP2012236473A JP2012236473A JP5491602B2 JP 5491602 B2 JP5491602 B2 JP 5491602B2 JP 2012236473 A JP2012236473 A JP 2012236473A JP 2012236473 A JP2012236473 A JP 2012236473A JP 5491602 B2 JP5491602 B2 JP 5491602B2
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富士雄 舛岡
広記 中村
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Unisantis Electronics Singapore Pte Ltd
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Description

この発明は半導体装置に関するものである。 The present invention relates to a semiconductor device.

半導体装置、なかでもＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。デジタル回路の基本回路は、インバータ回路であるが、このインバータ回路を構成するＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難であり、ホットキャリア効果による信頼性の低下が生じ、また必要な電流量確保の要請から回路の占有面積をなかなかちいさくできない、といった問題があった。この様な問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲートがシリコン柱を取り囲む構造のＳｕｒｒｏｕｎｄｉｎｇ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ（ＳＧＴ）が提案され、ｐＭＯＳ ＳＧＴとｎＭＯＳ ＳＧＴを用いたＣＭＯＳインバータ回路が提案された（例えば、非特許文献１）。 Semiconductor devices, especially integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. The basic circuit of the digital circuit is an inverter circuit. However, as the MOS transistors constituting the inverter circuit are miniaturized, it is difficult to suppress the leakage current, and the reliability is lowered due to the hot carrier effect. There has been a problem that it is difficult to occupy the area occupied by the circuit due to a demand for securing a large amount of current. In order to solve such a problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds a silicon pillar is proposed, and pMOS SGT and nMOS SGT are formed. A CMOS inverter circuit used has been proposed (for example, Non-Patent Document 1).

インバータ二つと選択トランジスタ二つでＳＲＡＭが構成される。従来のＳＧＴを用いたＣＭＯＳインバータ回路を用いて構成すると、２本のｐＭＯＳ ＳＧＴと、４本のｎＭＯＳ ＳＧＴで構成される。すなわち、従来のＳＧＴを用いたＣＭＯＳインバータ回路を用いたＳＲＡＭは、計６本の柱で構成される。 An SRAM is composed of two inverters and two selection transistors. When a conventional CMOS inverter circuit using SGT is used, it is composed of two pMOS SGTs and four nMOS SGTs. That is, an SRAM using a CMOS inverter circuit using a conventional SGT is composed of a total of six pillars.

Ｓ．Ｗａｔａｎａｂｅ、Ｋ．Ｔｓｕｃｈｉｄａ、Ｄ．Ｔａｋａｓｈｉｍａ、Ｙ．Ｏｏｗａｋｉ、Ａ．Ｎｉｔａｙａｍａ、Ｋ．Ｈｉｅｄａ、Ｈ．Ｔａｋａｔｏ、Ｋ．Ｓｕｎｏｕｃｈｉ、Ｆ．Ｈｏｒｉｇｕｃｈｉ、Ｋ．Ｏｈｕｃｈｉ、Ｆ．Ｍａｓｕｏｋａ、Ｈ．Ｈａｒａ、“Ａ Ｎｏｂｅｌ Ｃｉｒｃｕｉｔ Ｔｅｃｈｎｏｌｏｇｙ ｗｉｔｈ Ｓｕｒｒｏｕｎｄｉｎｇ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒｓ （ＳＧＴ’ｓ） ｆｏｒ Ｕｌｔｒａ Ｈｉｇｈ Ｄｅｎｓｉｔｙ ＤＲＡＭ’ｓ”、ＩＥＥＥ ＪＳＳＣ、Ｖｏｌ．３０、Ｎｏ．９、１９９５．S. Watanabe, K.M. Tsuchida, D.H. Takashima, Y. et al. Oowaki, A .; Nitayama, K .; Hieda, H .; Takato, K.K. Sunouchi, F.A. Horiguchi, K. et al. Ohuchi, F.A. Masuka, H .; Hara, “A Nobel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, IEEE JSSC, Vol. 30, no. 9, 1995.

そこで、１本の柱を用いてインバータを構成することにより、
２本の柱で２個のインバータを構成し、
２本の柱で２個の選択トランジスタを構成することにより、
計４本の柱でＳＲＡＭを構成することにより、高集積なＣＭＯＳ ＳＲＡＭを提供することを課題とする。 Therefore, by constructing an inverter using one pillar,
Two inverters consist of two pillars,
By configuring two select transistors with two pillars,
It is an object of the present invention to provide a highly integrated CMOS SRAM by configuring the SRAM with a total of four pillars.

本発明の１態様では、
基板上に行列状に配列された２つのインバータ及び２つの選択トランジスタを備えた半導体装置であって、
第１の第１導電型半導体と、該第１の第１導電型半導体とは極性が異なる第１の第２導電型半導体と、前記第１の第１導電型半導体と前記第１の第２導電型半導体との間に配置される第１の絶縁物が一体となり基板に対して垂直に延びる１本の第１の柱と、
前記第１の第１導電型半導体の上に配置され、前記第１の第１導電型半導体とは極性が異なる第１の第２導電型高濃度半導体と、
前記第１の第１導電型半導体の下に配置され、前記第１の第１導電型半導体とは極性が異なる第２の第２導電型高濃度半導体と、
前記第１の第２導電型半導体の上に配置され、前記第１の第２導電型半導体とは極性が異なる第１の第１導電型高濃度半導体と、
前記第１の第２導電型半導体の下に配置され、前記第１の第２導電型半導体とは極性が異なる第２の第１導電型高濃度半導体と、
前記第１の柱を取り囲む第１のゲート絶縁物と、
前記第１のゲート絶縁物を取り囲む第１のゲート導電体と、
を有する一行二列目の第１のインバータと、
第２の第１導電型半導体と、該第２の第１導電型半導体とは極性が異なる第２の第２導電型半導体と、前記第２の第１導電型半導体と前記第２の第２導電型半導体との間に配置される第２の絶縁物が一体となり基板に対して垂直に延びる１本の第２の柱と、
前記第２の第１導電型半導体の上に配置され、前記第２の第１導電型半導体とは極性が異なる第３の第２導電型高濃度半導体と、
前記第２の第１導電型半導体の下に配置され、前記第２の第１導電型半導体とは極性が異なる第４の第２導電型高濃度半導体と、
前記第２の第２導電型半導体の上に配置され、前記第２の第２導電型半導体とは極性が異なる第３の第１導電型高濃度半導体と、
前記第２の第２導電型半導体の下に配置され、前記第２の第２導電型半導体とは極性が異なる第４の第１導電型高濃度半導体と、
前記第２の柱を取り囲む第２のゲート絶縁物と、
前記第２のゲート絶縁物を取り囲む第２のゲート導電体と、
を有する二行一列目の第２のインバータと、
第３の第１導電型半導体からなる第３の柱と、
前記第３の第１導電型半導体の上に配置され、前記第３の第１導電型半導体とは極性が異なる第５の第２導電型高濃度半導体と、
前記第３の第１導電型半導体の下に配置され、前記第３の第１導電型半導体とは極性が異なる第６の第２導電型高濃度半導体と、
前記第３の柱を取り囲む第３のゲート絶縁物と、
前記第３のゲート絶縁物を取り囲む第３のゲート導電体と、
を有する一行一列目の選択トランジスタと、
第４の第１導電型半導体からなる第４の柱と、
前記第４の第１導電型半導体の上に配置され、前記第４の第１導電型半導体とは極性が異なる第７の第２導電型高濃度半導体と、
前記第４の第１導電型半導体の下に配置され、前記第４の第１導電型半導体とは極性が異なる第８の第２導電型高濃度半導体と、
前記第４の柱を取り囲む第４のゲート絶縁物と、
前記第４のゲート絶縁物を取り囲む第４のゲート導電体と、
を有する二行二列目の選択トランジスタと、
を有することを特徴とする半導体装置である。 In one aspect of the invention,
A semiconductor device comprising two inverters and two selection transistors arranged in a matrix on a substrate,
A first first conductivity type semiconductor; a first second conductivity type semiconductor having a polarity different from that of the first first conductivity type semiconductor; the first first conductivity type semiconductor; and the first second conductivity type. A first pillar integrated with a first insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A first second conductivity type high concentration semiconductor disposed on the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A second second conductivity type high-concentration semiconductor disposed under the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A first first-conductivity-type high-concentration semiconductor disposed on the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A second first-conductivity-type high-concentration semiconductor disposed under the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A first gate insulator surrounding the first pillar;
A first gate conductor surrounding the first gate insulator;
A first inverter in the first row and the second column having
A second first conductive semiconductor, a second second conductive semiconductor having a polarity different from that of the second first conductive semiconductor, the second first conductive semiconductor, and the second second. A second pillar integrally formed with the second insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A third second-conductivity-type high-concentration semiconductor disposed on the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A fourth second-conductivity-type high-concentration semiconductor disposed under the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A third first-conductivity type high-concentration semiconductor disposed on the second second-conductivity type semiconductor and having a polarity different from that of the second second-conductivity type semiconductor;
A fourth first-conductivity-type high-concentration semiconductor disposed under the second second-conductivity-type semiconductor and having a polarity different from that of the second second-conductivity-type semiconductor;
A second gate insulator surrounding the second pillar;
A second gate conductor surrounding the second gate insulator;
A second inverter in the second row and first column having
A third pillar made of a third first conductivity type semiconductor;
A fifth second-conductivity-type high-concentration semiconductor disposed on the third first-conductivity-type semiconductor and having a polarity different from that of the third first-conductivity-type semiconductor;
A sixth second-conductivity type high-concentration semiconductor disposed under the third first-conductivity type semiconductor and having a polarity different from that of the third first-conductivity type semiconductor;
A third gate insulator surrounding the third pillar;
A third gate conductor surrounding the third gate insulator;
A selection transistor in the first row and the first column having:
A fourth column made of a fourth first conductivity type semiconductor;
A seventh second-conductivity type high-concentration semiconductor disposed on the fourth first-conductivity type semiconductor and having a polarity different from that of the fourth first-conductivity type semiconductor;
An eighth second conductivity type high-concentration semiconductor disposed below the fourth first conductivity type semiconductor and having a polarity different from that of the fourth first conductivity type semiconductor;
A fourth gate insulator surrounding the fourth pillar;
A fourth gate conductor surrounding the fourth gate insulator;
A second row and second column selection transistor having:
It is a semiconductor device characterized by having.

また、本発明の好ましい態様では、
第２の第１導電型高濃度半導体と第２の第２導電型高濃度半導体と第８の第２導電型高濃度半導体が接続され、
第８の第２導電型高濃度半導体と第２のゲート導電体とが接続され、
第４の第１導電型高濃度半導体と第４の第２導電型高濃度半導体と第６の第２導電型高濃度半導体が接続され、
第６の第２導電型高濃度半導体と第１のゲート導電体とが接続されることを特徴とする前記記載の半導体装置である。 In a preferred embodiment of the present invention,
The second first conductivity type high concentration semiconductor, the second second conductivity type high concentration semiconductor, and the eighth second conductivity type high concentration semiconductor are connected,
An eighth second conductivity type high concentration semiconductor and a second gate conductor are connected;
A fourth first conductivity type high concentration semiconductor, a fourth second conductivity type high concentration semiconductor, and a sixth second conductivity type high concentration semiconductor are connected;
The semiconductor device as described above, wherein the sixth second-conductivity type high-concentration semiconductor and the first gate conductor are connected.

また、本発明の好ましい態様では、
半導体はシリコンであることを特徴とする前記記載の半導体装置である。 In a preferred embodiment of the present invention,
The semiconductor device as described above, wherein the semiconductor is silicon.

また、本発明の好ましい態様では、
第１導電型はｐ型であり、第２導電型はｎ型であることを特徴とする前記記載の半導体装置である。 In a preferred embodiment of the present invention,
The semiconductor device as described above, wherein the first conductivity type is p-type and the second conductivity type is n-type.

本発明では、
本発明の１態様では、
基板上に行列状に配列された２つのインバータ及び２つの選択トランジスタを備えた半導体装置であって、
第１の第１導電型半導体と、該第１の第１導電型半導体とは極性が異なる第１の第２導電型半導体と、前記第１の第１導電型半導体と前記第１の第２導電型半導体との間に配置される第１の絶縁物が一体となり基板に対して垂直に延びる１本の第１の柱と、
前記第１の第１導電型半導体の上に配置され、前記第１の第１導電型半導体とは極性が異なる第１の第２導電型高濃度半導体と、
前記第１の第１導電型半導体の下に配置され、前記第１の第１導電型半導体とは極性が異なる第２の第２導電型高濃度半導体と、
前記第１の第２導電型半導体の上に配置され、前記第１の第２導電型半導体とは極性が異なる第１の第１導電型高濃度半導体と、
前記第１の第２導電型半導体の下に配置され、前記第１の第２導電型半導体とは極性が異なる第２の第１導電型高濃度半導体と、
前記第１の柱を取り囲む第１のゲート絶縁物と、
前記第１のゲート絶縁物を取り囲む第１のゲート導電体と、
を有する一行二列目の第１のインバータと、
第２の第１導電型半導体と、該第２の第１導電型半導体とは極性が異なる第２の第２導電型半導体と、前記第２の第１導電型半導体と前記第２の第２導電型半導体との間に配置される第２の絶縁物が一体となり基板に対して垂直に延びる１本の第２の柱と、
前記第２の第１導電型半導体の上に配置され、前記第２の第１導電型半導体とは極性が異なる第３の第２導電型高濃度半導体と、
前記第２の第１導電型半導体の下に配置され、前記第２の第１導電型半導体とは極性が異なる第４の第２導電型高濃度半導体と、
前記第２の第２導電型半導体の上に配置され、前記第２の第２導電型半導体とは極性が異なる第３の第１導電型高濃度半導体と、
前記第２の第２導電型半導体の下に配置され、前記第２の第２導電型半導体とは極性が異なる第４の第１導電型高濃度半導体と、
前記第２の柱を取り囲む第２のゲート絶縁物と、
前記第２のゲート絶縁物を取り囲む第２のゲート導電体と、
を有する二行一列目の第２のインバータと、
第３の第１導電型半導体からなる第３の柱と、
前記第３の第１導電型半導体の上に配置され、前記第３の第１導電型半導体とは極性が異なる第５の第２導電型高濃度半導体と、
前記第３の第１導電型半導体の下に配置され、前記第３の第１導電型半導体とは極性が異なる第６の第２導電型高濃度半導体と、
前記第３の柱を取り囲む第３のゲート絶縁物と、
前記第３のゲート絶縁物を取り囲む第３のゲート導電体と、
を有する一行一列目の選択トランジスタと、
第４の第１導電型半導体からなる第４の柱と、
前記第４の第１導電型半導体の上に配置され、前記第４の第１導電型半導体とは極性が異なる第７の第２導電型高濃度半導体と、
前記第４の第１導電型半導体の下に配置され、前記第４の第１導電型半導体とは極性が異なる第８の第２導電型高濃度半導体と、
前記第４の柱を取り囲む第４のゲート絶縁物と、
前記第４のゲート絶縁物を取り囲む第４のゲート導電体と、
を有する二行二列目の選択トランジスタと、
を有することを特徴とする半導体装置により、
１本の柱を用いてインバータを構成することにより、
２本の柱で２個のインバータを構成し、
２本の柱で２個の選択トランジスタを構成することにより、
計４本の柱でＳＲＡＭを構成することにより、高集積なＣＭＯＳ ＳＲＡＭを提供することができる。 In the present invention,
In one aspect of the invention,
A semiconductor device comprising two inverters and two selection transistors arranged in a matrix on a substrate,
A first first conductivity type semiconductor; a first second conductivity type semiconductor having a polarity different from that of the first first conductivity type semiconductor; the first first conductivity type semiconductor; and the first second conductivity type. A first pillar integrated with a first insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A first second conductivity type high concentration semiconductor disposed on the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A second second conductivity type high-concentration semiconductor disposed under the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A first first-conductivity-type high-concentration semiconductor disposed on the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A second first-conductivity-type high-concentration semiconductor disposed under the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A first gate insulator surrounding the first pillar;
A first gate conductor surrounding the first gate insulator;
A first inverter in the first row and the second column having
A second first conductive semiconductor, a second second conductive semiconductor having a polarity different from that of the second first conductive semiconductor, the second first conductive semiconductor, and the second second. A second pillar integrally formed with the second insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A third second-conductivity-type high-concentration semiconductor disposed on the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A fourth second-conductivity-type high-concentration semiconductor disposed under the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A third first-conductivity type high-concentration semiconductor disposed on the second second-conductivity type semiconductor and having a polarity different from that of the second second-conductivity type semiconductor;
A fourth first-conductivity-type high-concentration semiconductor disposed under the second second-conductivity-type semiconductor and having a polarity different from that of the second second-conductivity-type semiconductor;
A second gate insulator surrounding the second pillar;
A second gate conductor surrounding the second gate insulator;
A second inverter in the second row and first column having
A third pillar made of a third first conductivity type semiconductor;
A fifth second-conductivity-type high-concentration semiconductor disposed on the third first-conductivity-type semiconductor and having a polarity different from that of the third first-conductivity-type semiconductor;
A sixth second-conductivity type high-concentration semiconductor disposed under the third first-conductivity type semiconductor and having a polarity different from that of the third first-conductivity type semiconductor;
A third gate insulator surrounding the third pillar;
A third gate conductor surrounding the third gate insulator;
A selection transistor in the first row and the first column having:
A fourth column made of a fourth first conductivity type semiconductor;
A seventh second-conductivity type high-concentration semiconductor disposed on the fourth first-conductivity type semiconductor and having a polarity different from that of the fourth first-conductivity type semiconductor;
An eighth second conductivity type high-concentration semiconductor disposed below the fourth first conductivity type semiconductor and having a polarity different from that of the fourth first conductivity type semiconductor;
A fourth gate insulator surrounding the fourth pillar;
A fourth gate conductor surrounding the fourth gate insulator;
A second row and second column selection transistor having:
By a semiconductor device characterized by having
By constructing an inverter using one pillar,
Two inverters consist of two pillars,
By configuring two select transistors with two pillars,
By configuring the SRAM with a total of four pillars, a highly integrated CMOS SRAM can be provided.

また、本発明では、
第２の第１導電型高濃度半導体と第２の第２導電型高濃度半導体と第８の第２導電型高濃度半導体が接続され、
第８の第２導電型高濃度半導体と第２のゲート導電体とが接続され、
第４の第１導電型高濃度半導体と第４の第２導電型高濃度半導体と第６の第２導電型高濃度半導体が接続され、
第６の第２導電型高濃度半導体と第１のゲート導電体とが接続されることを特徴とする前記記載の半導体装置により、ＳＲＡＭを構成することができ、高集積なＣＭＯＳ ＳＲＡＭを提供することができる。 In the present invention,
The second first conductivity type high concentration semiconductor, the second second conductivity type high concentration semiconductor, and the eighth second conductivity type high concentration semiconductor are connected,
An eighth second conductivity type high concentration semiconductor and a second gate conductor are connected;
A fourth first conductivity type high concentration semiconductor, a fourth second conductivity type high concentration semiconductor, and a sixth second conductivity type high concentration semiconductor are connected;
An SRAM can be constituted by the semiconductor device described above, wherein the sixth second-conductivity type high-concentration semiconductor and the first gate conductor are connected, and a highly integrated CMOS SRAM is provided. be able to.

また、本発明では、
半導体はシリコンであることを特徴とする前記記載の半導体装置により、シリコンを用いた高集積なＣＭＯＳ ＳＲＡＭを提供することができる。 In the present invention,
According to the semiconductor device described above, wherein the semiconductor is silicon, a highly integrated CMOS SRAM using silicon can be provided.

また、本発明では、
第１導電型はｐ型であり、第２導電型はｎ型であることを特徴とする前記記載の半導体装置により、
選択トランジスタをｎ型トランジスタとすることができる。 In the present invention,
According to the semiconductor device described above, wherein the first conductivity type is p-type and the second conductivity type is n-type.
The selection transistor can be an n-type transistor.

（ａ）はこの発明に係る半導体装置の平面図、（ｂ）はこの発明に係る半導体装置のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置のＹ−Ｙ’断面図である。(A) is a plan view of the semiconductor device according to the present invention, (b) is an XX ′ sectional view of the semiconductor device according to the present invention, and (c) is a YY ′ sectional view of the semiconductor device according to the present invention. is there. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. （ａ）はこの発明に係る半導体装置の製造方法の平面図、（ｂ）はこの発明に係る半導体装置の製造方法のＸ−Ｘ’断面図、（ｃ）はこの発明に係る半導体装置の製造方法のＹ−Ｙ’断面図である。(A) is a plan view of a method for manufacturing a semiconductor device according to the present invention, (b) is a cross-sectional view taken along the line XX ′ of the method for manufacturing a semiconductor device according to the present invention, and (c) is a method for manufacturing the semiconductor device according to the present invention. It is YY 'sectional drawing of a method. この発明に係る半導体装置を２行２列に配置した図である。It is the figure which has arrange | positioned the semiconductor device based on this invention in 2 rows 2 columns. この発明に係る半導体装置を２行２列に配置した装置のトランジスタ層の図である。It is a figure of the transistor layer of the apparatus which has arrange | positioned the semiconductor device based on this invention in 2 rows 2 columns. この発明に係る半導体装置を２行２列に配置した装置のコンタクト層、第１メタル層の図である。It is a figure of the contact layer of a device which has arranged the semiconductor device concerning this invention in 2 rows and 2 columns, and the 1st metal layer. この発明に係る半導体装置を２行２列に配置した装置の第１ビア（第１メタル−第２メタル間コンタクト）、第２メタル層の図である。It is a figure of the 1st via | veer (1st metal-second metal contact) of a device which has arranged the semiconductor device concerning this invention in 2 rows and 2 columns, and the 2nd metal layer. この発明に係る半導体装置を２行２列に配置した装置の第２ビア（第２メタル−第３メタル間コンタクト）、第３メタル層の図である。It is a figure of the 2nd via | veer (2nd metal-third metal contact) of the apparatus which has arrange | positioned the semiconductor device based on this invention in 2 rows 2 columns, and a 3rd metal layer. この発明に係る半導体装置を２行２列に配置した装置の第３ビア（第３メタル−第４メタル間コンタクト）、第４メタル層の図である。It is a figure of the 3rd via (contact between 3rd metal-4th metal) of a device which has arranged the semiconductor device concerning this invention in 2 rows and 2 columns, and the 4th metal layer. この発明に係る半導体装置の図面と、図面と相対する等価回路の図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a semiconductor device according to the present invention, and a diagram of an equivalent circuit opposite to the drawing. この発明に係る半導体装置の図面と、等価回路を１対１で表せる図面である。BRIEF DESCRIPTION OF THE DRAWINGS It is drawing which can represent the drawing of the semiconductor device based on this invention, and an equivalent circuit by one to one.

この発明に係る半導体装置の平面図と断面構造をそれぞれ図１（ａ）、（ｂ）、（ｃ）に示す。図１（ａ）は平面図であり、図１（ｂ）はＸ−Ｘ’断面図、図１（ｃ）はＹ−Ｙ’断面図である。
また、図７２はこの発明に係る半導体装置の図面と、図面と相対する等価回路の図であり、図７３はこの発明に係る半導体装置の図面と、等価回路を１対１で表せる図面である。 A plan view and a cross-sectional structure of the semiconductor device according to the present invention are shown in FIGS. 1 (a), (b), and (c), respectively. 1A is a plan view, FIG. 1B is an XX ′ sectional view, and FIG. 1C is a YY ′ sectional view.
72 is a diagram of a semiconductor device according to the present invention and an equivalent circuit diagram relative to the drawing. FIG. 73 is a diagram of the semiconductor device according to the present invention and an equivalent circuit that can be represented on a one-to-one basis. .

この実施例では、
第１のｐ型シリコン１３７と、該第１のｐ型シリコン１３７とは極性が異なる第１のｎ型シリコン１０４と、前記第１のｐ型シリコン１３７と前記第１のｎ型シリコン１０４との間に配置される第１の絶縁物１１２が一体となり基板に対して垂直に延びる１本の第１の柱と、
前記第１のｐ型シリコン１３７の上に配置され、前記第１のｐ型シリコン１３７とは極性が異なる第１のｎ型高濃度シリコン１８２と、
前記第１のｐ型シリコン１３７の下に配置され、前記第１のｐ型シリコン１３７とは極性が異なる第２のｎ型高濃度シリコン１４１と、
前記第１のｎ型シリコン１０４の上に配置され、前記第１のｎ型シリコン１０４とは極性が異なる第１のｐ型高濃度シリコン１８６と、
前記第１のｎ型シリコン１０４の下に配置され、前記第１のｎ型シリコン１０４とは極性が異なる第２のｐ型高濃度シリコン１４３と、
前記第１の柱を取り囲む第１のゲート絶縁物１７６と、
前記第１のゲート絶縁物１７６を取り囲む第１のゲート導電体１６７と、
を有する一行二列目の第１のインバータ５０１と、
第２のｐ型シリコンと、該第２のｐ型シリコンとは極性が異なる第２のｎ型シリコンと、前記第２のｐ型シリコンと前記第２のｎ型シリコンとの間に配置される第２の絶縁物１１３が一体となり基板に対して垂直に延びる１本の第２の柱と、
前記第２のｐ型シリコンの上に配置され、前記第２のｐ型シリコンとは極性が異なる第３のｎ型高濃度シリコンと、
前記第２のｐ型シリコンの下に配置され、前記第２のｐ型シリコンとは極性が異なる第４のｎ型高濃度シリコンと、
前記第２のｎ型シリコンの上に配置され、前記第２のｎ型シリコンとは極性が
異なる第３のｐ型高濃度シリコンと、
前記第２のｎ型シリコンの下に配置され、前記第２のｎ型シリコンとは極性が異なる第４のｐ型高濃度シリコンと、
前記第２の柱を取り囲む第２のゲート絶縁物１７７と、
前記第２のゲート絶縁物１７７を取り囲む第２のゲート導電体１６８と、
を有する二行一列目の第２のインバータ５０２と、
第３のｐ型シリコン１３６からなる第３の柱と、
前記第３のｐ型シリコン１３６の上に配置され、前記第３のｐ型シリコン１３６とは極性が異なる第５のｎ型高濃度シリコン１８１と、
前記第３のｐ型シリコン１３６の下に配置され、前記第３のｐ型シリコン１３６とは極性が異なる第６のｎ型高濃度シリコン１４０と、
前記第３の柱を取り囲む第３のゲート絶縁物１７５と、
前記第３のゲート絶縁物１７５を取り囲む第３のゲート導電体１６６と、
を有する一行一列目の選択トランジスタ５０３と、
第４のｐ型シリコンからなる第４の柱と、
前記第４のｐ型シリコンの上に配置され、前記第４のｐ型シリコンとは極性が異なる第７のｎ型高濃度シリコンと、
前記第４のｐ型シリコンの下に配置され、前記第４のｐ型シリコンとは極性が異なる第８のｎ型高濃度シリコンと、
前記第４の柱を取り囲む第４のゲート絶縁物と、
前記第４のゲート絶縁物を取り囲む第４のゲート導電体１６９と、
を有する二行二列目の選択トランジスタ５０４と、
を有することを特徴とする半導体装置である。
なお、二行二列目の選択トランジスタについては、断面図を用いて説明していないが、図１（ｂ）及び（ｃ）から、二行二列目の選択トランジスタと第１及び第２のインバータとの接続関係を示す断面は容易に理解される。すなわち、二行二列目の選択トランジスタと第２のインバータとの接続関係を示す断面は、図１（ｂ）の第１のインバータと一行一列目の選択トランジスタとを左右の位置を入れ替えて配置して互いに接続したものと等しい。また、二行二列目の選択トランジスタと第１のインバータとの接続関係を示す断面は、図１（ｃ）の第２のインバータと一行一列目の選択トランジスタとを上下の位置を入れ替えて配置して互いに接続したものと等しい。
第１のインバータ５０１の第２のｎ型高濃度シリコン１４１と第２のｐ型高濃度シリコン１４３はシリコンと金属の化合物１９３にて接続され、
シリコンと金属の化合物１９３は第８のｎ型高濃度シリコンと接続し、
第８のｎ型高濃度シリコンはシリコンと金属の化合物１９６と接続する。
第２のインバータ５０２の第４のｎ型高濃度シリコンと第４のｐ型高濃度シリコンはシリコンと金属の化合物１９２にて接続され、
シリコンと金属の化合物１９２は第６のｎ型高濃度シリコン１４０と接続し、
第６のｎ型高濃度シリコン１４０はシリコンと金属の化合物１８９と接続する。
第１のインバータ５０１のゲート導電体１６７は、コンタクト２０２を介してシリコンと金属の化合物１８９と接続する。
第２のインバータ５０２のゲート導電体１６８は、コンタクト２０３を介してシリコンと金属の化合物１９６と接続する。 In this example,
A first p-type silicon 137; a first n-type silicon 104 having a polarity different from that of the first p-type silicon 137; and the first p-type silicon 137 and the first n-type silicon 104 A first pillar that is integrated with a first insulator 112 disposed therebetween and extends perpendicularly to the substrate;
A first n-type high-concentration silicon 182 disposed on the first p-type silicon 137 and having a polarity different from that of the first p-type silicon 137;
A second n-type high-concentration silicon 141 disposed under the first p-type silicon 137 and having a polarity different from that of the first p-type silicon 137;
A first p-type high-concentration silicon 186 disposed on the first n-type silicon 104 and having a polarity different from that of the first n-type silicon 104;
A second p-type high-concentration silicon 143 disposed under the first n-type silicon 104 and having a polarity different from that of the first n-type silicon 104;
A first gate insulator 176 surrounding the first pillar;
A first gate conductor 167 surrounding the first gate insulator 176;
A first inverter 501 in the first row and the second column having
Arranged between the second p-type silicon, the second n-type silicon having a different polarity from the second p-type silicon, and the second p-type silicon and the second n-type silicon One second pillar integrally formed with the second insulator 113 and extending perpendicularly to the substrate;
A third n-type high-concentration silicon disposed on the second p-type silicon and having a polarity different from that of the second p-type silicon;
A fourth n-type high-concentration silicon disposed under the second p-type silicon and having a polarity different from that of the second p-type silicon;
A third p-type high-concentration silicon disposed on the second n-type silicon and having a polarity different from that of the second n-type silicon;
A fourth p-type high-concentration silicon disposed under the second n-type silicon and having a polarity different from that of the second n-type silicon;
A second gate insulator 177 surrounding the second pillar;
A second gate conductor 168 surrounding the second gate insulator 177;
A second inverter 502 in the second row and first column having
A third column of third p-type silicon 136;
A fifth n-type high-concentration silicon 181 disposed on the third p-type silicon 136 and having a polarity different from that of the third p-type silicon 136;
A sixth n-type high-concentration silicon 140 disposed under the third p-type silicon 136 and having a polarity different from that of the third p-type silicon 136;
A third gate insulator 175 surrounding the third pillar;
A third gate conductor 166 surrounding the third gate insulator 175;
A selection transistor 503 in the first row and the first column having
A fourth pillar made of fourth p-type silicon;
A seventh n-type high-concentration silicon disposed on the fourth p-type silicon and having a polarity different from that of the fourth p-type silicon;
An eighth n-type high-concentration silicon disposed under the fourth p-type silicon and having a polarity different from that of the fourth p-type silicon;
A fourth gate insulator surrounding the fourth pillar;
A fourth gate conductor 169 surrounding the fourth gate insulator;
A second row and second column selection transistor 504 having:
It is a semiconductor device characterized by having.
Note that the selection transistor in the second row and the second column is not described with reference to cross-sectional views, but from FIG. 1B and FIG. 1C, the selection transistor in the second row and the second column and the first and second transistors The cross section showing the connection relationship with the inverter is easily understood. That is, the cross section showing the connection relationship between the second row and second column selection transistor and the second inverter is arranged by switching the left and right positions of the first inverter and the first row and first column selection transistor of FIG. And are equal to those connected to each other. The cross section showing the connection relationship between the selection transistor in the second row and the second column and the first inverter is arranged with the second inverter and the selection transistor in the first row and the first column in FIG. And are equal to those connected to each other.
The second n-type high-concentration silicon 141 and the second p-type high-concentration silicon 143 of the first inverter 501 are connected by a compound 193 of silicon and metal,
The compound 193 of silicon and metal is connected to the eighth n-type high concentration silicon,
The eighth n-type high-concentration silicon is connected to a compound 196 of silicon and metal.
The fourth n-type high-concentration silicon and the fourth p-type high-concentration silicon of the second inverter 502 are connected by a compound 192 of silicon and metal,
The compound 192 of silicon and metal is connected to the sixth n-type high concentration silicon 140,
The sixth n-type high-concentration silicon 140 is connected to a silicon-metal compound 189.
The gate conductor 167 of the first inverter 501 is connected to the silicon and metal compound 189 through the contact 202.
The gate conductor 168 of the second inverter 502 is connected to the silicon and metal compound 196 through the contact 203.

また、第２のｐ型高濃度シリコン１４３と第２のｎ型高濃度シリコン１４１と第８のｎ型高濃度シリコンが接続され、
第８のｎ型高濃度シリコンと第２のゲート導電体１６８とが接続され、
第４のｐ型高濃度シリコンと第４のｎ型高濃度シリコンと第６のｎ型高濃度シリコン１４０が接続され、
第６のｎ型高濃度シリコン１４０と第１のゲート導電体１６７とが接続される。 In addition, the second p-type high-concentration silicon 143, the second n-type high-concentration silicon 141, and the eighth n-type high-concentration silicon are connected,
The eighth n-type high-concentration silicon and the second gate conductor 168 are connected,
The fourth p-type high-concentration silicon, the fourth n-type high-concentration silicon, and the sixth n-type high-concentration silicon 140 are connected,
The sixth n-type high-concentration silicon 140 and the first gate conductor 167 are connected.

以下に、この発明に係る半導体装置の構造を形成するための製造工程の一例を図２〜図６５を参照して説明する。なお、これらの図面では、同一の構成要素に対しては同一の符号が付されている。図２〜図６５は、この発明に係る半導体装置の製造例を示している。（ａ）は平面図、（ｂ）はＸ−Ｘ’断面図、（ｃ）はＹ−Ｙ’断面図を示している。 An example of a manufacturing process for forming the structure of the semiconductor device according to the present invention will be described below with reference to FIGS. In these drawings, the same components are denoted by the same reference numerals. 2 to 65 show an example of manufacturing a semiconductor device according to the present invention. (A) is a plan view, (b) is an X-X ′ cross-sectional view, and (c) is a Y-Y ′ cross-sectional view.

図２を参照して、酸化膜１０１上に形成されたｐ型シリコン１０２に、ｎ型シリコンを形成するためのレジスト１０３を形成する。 Referring to FIG. 2, a resist 103 for forming n-type silicon is formed on p-type silicon 102 formed on oxide film 101.

図３を参照して、不純物を導入し、ｎ型シリコン１０４、１０５を形成する。 Referring to FIG. 3, impurities are introduced to form n-type silicon 104 and 105.

図４を参照して、レジスト１０３を剥離する。 Referring to FIG. 4, the resist 103 is peeled off.

図５を参照して、酸化膜１０６、窒化膜１０７を堆積する。 Referring to FIG. 5, an oxide film 106 and a nitride film 107 are deposited.

図６を参照して、窒化膜エッチングのためのレジスト１０８を形成する。 Referring to FIG. 6, a resist 108 for nitride film etching is formed.

図７を参照して、窒化膜をエッチングし、酸化膜をエッチングする。 Referring to FIG. 7, the nitride film is etched and the oxide film is etched.

図８を参照して、レジスト１０８を剥離する。 Referring to FIG. 8, the resist 108 is removed.

図９を参照して、窒化膜１０９を堆積する。 Referring to FIG. 9, a nitride film 109 is deposited.

図１０を参照して、窒化膜をエッチバックし、窒化膜サイドウォール１１０、１１１を形成する。 Referring to FIG. 10, the nitride film is etched back to form nitride film sidewalls 110 and 111.

図１１を参照して、シリコンをエッチングする。 Referring to FIG. 11, silicon is etched.

図１２を参照して、絶縁膜を堆積し、平坦化し、第１の絶縁膜１１２、１１３とする。 Referring to FIG. 12, an insulating film is deposited and planarized to form first insulating films 112 and 113.

図１３を参照して、窒化膜１１４を堆積する。 Referring to FIG. 13, a nitride film 114 is deposited.

図１４を参照して、柱形成のためのレジスト１１５、１１６、１１７、１１８を形成する。 Referring to FIG. 14, resists 115, 116, 117, and 118 for forming columns are formed.

図１５を参照して、窒化膜をエッチングし、窒化膜ハードマスク１１９、１２０、１２１、１２２を形成する。 Referring to FIG. 15, the nitride film is etched to form nitride film hard masks 119, 120, 121, and 122.

図１６を参照して、酸化膜をエッチングし、酸化膜１２３、１２４を形成する。 Referring to FIG. 16, the oxide film is etched to form oxide films 123 and 124.

図１７を参照して、レジスト１１５、１１６、１１７、１１８を剥離する。 Referring to FIG. 17, resists 115, 116, 117, and 118 are removed.

図１８を参照して、シリコンをエッチングし、柱を形成する。 Referring to FIG. 18, silicon is etched to form pillars.

図１９を参照して、酸化膜１２５を堆積する。 Referring to FIG. 19, an oxide film 125 is deposited.

図２０を参照して、酸化膜をエッチングし、サイドウォール状に残存させ、酸化膜サイドウォール１２６、１２７、１２８、１２９を形成する。 Referring to FIG. 20, the oxide film is etched and left in a sidewall shape, and oxide film side walls 126, 127, 128, and 129 are formed.

図２１を参照して、素子分離するためのレジスト１３０、１３１を形成する。 Referring to FIG. 21, resists 130 and 131 for element isolation are formed.

図２２を参照して、シリコンをエッチングし、素子分離を行う。ｐ型シリコン１３２、１３３が形成される。 Referring to FIG. 22, silicon is etched and element isolation is performed. P-type silicon 132 and 133 are formed.

図２３を参照して、レジスト１３０、１３１を剥離する。 Referring to FIG. 23, resists 130 and 131 are removed.

図２４を参照して、不純物導入のためのレジスト１３４、１３５を形成する。 Referring to FIG. 24, resists 134 and 135 for introducing impurities are formed.

図２５を参照して、不純物を導入し、ｎ型高濃度シリコン１４０、１４１を形成する。ｐ型シリコン１３６、１３７、１３８、１３９が形成される。 Referring to FIG. 25, impurities are introduced to form n-type high-concentration silicon 140 and 141. P-type silicon 136, 137, 138, 139 is formed.

図２６を参照して、レジスト１３４、１３５を剥離する。 Referring to FIG. 26, resists 134 and 135 are removed.

図２７を参照して、不純物導入のためのレジスト１４２を形成する。 Referring to FIG. 27, a resist 142 for introducing impurities is formed.

図２８を参照して、不純物を導入し、ｐ型高濃度シリコン１４３、１４４を形成する。 Referring to FIG. 28, impurities are introduced to form p-type high concentration silicon 143 and 144.

図２９を参照して、レジスト１４２を剥離する。 Referring to FIG. 29, resist 142 is removed.

図３０を参照して、酸化膜サイドウォール１２６、１２７、１２８、１２９をエッチングする。 Referring to FIG. 30, oxide film side walls 126, 127, 128, and 129 are etched.

図３１を参照して、酸化膜１４５を堆積する。 Referring to FIG. 31, an oxide film 145 is deposited.

図３２を参照して、酸化膜をエッチバックする。このとき、窒化膜上にも酸化膜１４６、１４７、１４８、１４９が残存する。 Referring to FIG. 32, the oxide film is etched back. At this time, oxide films 146, 147, 148, and 149 also remain on the nitride film.

図３３を参照して、ゲート絶縁膜である高誘電体膜１５０、ゲート導電体である金属１５１を堆積し、平坦化する。平坦化の際、酸化膜１４６、１４７、１４８、１４９はエッチングされる。 Referring to FIG. 33, a high dielectric film 150 as a gate insulating film and a metal 151 as a gate conductor are deposited and planarized. During planarization, the oxide films 146, 147, 148, and 149 are etched.

図３４を参照して、金属１５１をエッチバックする。 Referring to FIG. 34, metal 151 is etched back.

図３５を参照して、酸化膜１５２を堆積し、平坦化する。 Referring to FIG. 35, an oxide film 152 is deposited and planarized.

図３６を参照して、酸化膜１５２をエッチバックする。 Referring to FIG. 36, the oxide film 152 is etched back.

図３７を参照して、窒化膜１５３を堆積する。 Referring to FIG. 37, a nitride film 153 is deposited.

図３８を参照して、窒化膜１５３をエッチングし、サイドウォール状に残存させ、窒化膜サイドウォール１５４、１５５、１５６、１５７を形成する。 Referring to FIG. 38, nitride film 153 is etched and left in a sidewall shape to form nitride film sidewalls 154, 155, 156, and 157.

図３９を参照して、ゲート導電体形成のためのレジスト１５８、１５９、１６０、１６１を形成する。 Referring to FIG. 39, resists 158, 159, 160, 161 for forming a gate conductor are formed.

図４０を参照して、酸化膜１５２をエッチングし、酸化膜１６２、１６３、１６４、１６５を形成する。 Referring to FIG. 40, oxide film 152 is etched to form oxide films 162, 163, 164, 165.

図４１を参照して、金属１５１をエッチングし、ゲート導電体１６６、１６７、１６８、１６９を形成する。 Referring to FIG. 41, metal 151 is etched to form gate conductors 166, 167, 168, 169.

図４２を参照して、レジスト１５８、１５９、１６０、１６１を剥離する。 Referring to FIG. 42, resists 158, 159, 160, 161 are removed.

図４３を参照して、酸化膜１７０を堆積する。 Referring to FIG. 43, an oxide film 170 is deposited.

図４４を参照して、酸化膜１７０をエッチングし、サイドウォール状に残存させ、酸化膜サイドウォール１７１、１７２、１７３、１７４を形成する。 Referring to FIG. 44, oxide film 170 is etched and left in a sidewall shape to form oxide film side walls 171, 172, 173 and 174.

図４５を参照して、高誘電体膜１５０をエッチングし、ゲート絶縁膜１７５、１７６、１７７、１７８を形成する。 Referring to FIG. 45, high dielectric film 150 is etched to form gate insulating films 175, 176, 177 and 178.

図４６を参照して、窒化膜をエッチングする。 Referring to FIG. 46, the nitride film is etched.

図４７を参照して、高誘電体膜であるゲート絶縁膜１７５、１７６、１７７、１７８をエッチングする。 Referring to FIG. 47, gate insulating films 175, 176, 177 and 178 which are high dielectric films are etched.

図４８を参照して、酸化膜をエッチングし、ｎ型高濃度シリコン１４０、１４１、ｐ型高濃度シリコン１４４、１４３を露出する。 Referring to FIG. 48, the oxide film is etched to expose n-type high concentration silicon 140 and 141 and p-type high concentration silicon 144 and 143.

図４９を参照して、不純物導入のためのレジスト１７９、１８０を形成する。 Referring to FIG. 49, resists 179 and 180 for introducing impurities are formed.

図５０を参照して、不純物を導入し、ｎ型高濃度シリコン１８１、１８２、１８３、１８４を形成する。 Referring to FIG. 50, impurities are introduced to form n-type high concentration silicon 181, 182, 183, and 184.

図５１を参照して、レジスト１７９、１８０を剥離する。 Referring to FIG. 51, resists 179 and 180 are removed.

図５２を参照して、不純物形成のためのレジスト１８５を形成する。 Referring to FIG. 52, a resist 185 for impurity formation is formed.

図５３を参照して、不純物を導入し、ｐ型高濃度シリコン１８６、１８７を形成する。 Referring to FIG. 53, impurities are introduced to form p-type high-concentration silicon 186 and 187.

図５４を参照して、レジスト１８５を剥離する。 Referring to FIG. 54, resist 185 is removed.

図５５を参照して、シリコンと金属の化合物１８８、１８９、１９０、１９１、１９２、１９３、１９４、１９５、１９６、１９７を形成する。 Referring to FIG. 55, silicon and metal compounds 188, 189, 190, 191, 192, 193, 194, 195, 196, and 197 are formed.

図５６を参照して、窒化膜１９８を堆積し、酸化膜１９９を堆積し、平坦化を行う。 Referring to FIG. 56, a nitride film 198 is deposited, an oxide film 199 is deposited, and planarization is performed.

図５７を参照して、コンタクト孔２００、２０１を形成する。 Referring to FIG. 57, contact holes 200 and 201 are formed.

図５８を参照して、コンタクト２０２、２０３を形成する。 Referring to FIG. 58, contacts 202 and 203 are formed.

図５９を参照して、酸化膜２０４を堆積し、平坦化する。 Referring to FIG. 59, an oxide film 204 is deposited and planarized.

図６０を参照して、コンタクト孔２０５、２０６を形成する。 Referring to FIG. 60, contact holes 205 and 206 are formed.

図６１を参照して、コンタクト孔２０７、２０８、２０９、２１０を形成する。 Referring to FIG. 61, contact holes 207, 208, 209 and 210 are formed.

図６２を参照して、コンタクト孔２１１、２１２を形成する。 Referring to FIG. 62, contact holes 211 and 212 are formed.

図６３を参照して、窒化膜１９８をエッチングし、酸化膜をエッチングする。 Referring to FIG. 63, nitride film 198 is etched, and the oxide film is etched.

図６４を参照して、コンタクト２１３、２１４、２１５、２１６、２１７、２１８、２１９、２２０を形成する。 Referring to FIG. 64, contacts 213, 214, 215, 216, 217, 218, 219, 220 are formed.

図６５を参照して、第１メタル２２１、２２２、２２３、２２４、２２５、２２６、２２７、２２８を形成する。
以上により、ＳＲＡＭメモリセルが形成される。 Referring to FIG. 65, first metals 221, 222, 223, 224, 225, 226, 227, and 228 are formed.
As a result, an SRAM memory cell is formed.

以下に、この発明に係る半導体装置を２行２列に配置したものの一例を図６６〜図７１を参照して説明する。なお、これらの図面では、同一の構成要素に対しては同一の符号が付されている。図６６はこの発明に係る半導体装置を２行２列に配置したものを示している。図６７はトランジスタ層を示している。図６８はコンタクト層、第１メタル層を示している。図６９は第１ビア（第１メタル−第２メタル間コンタクト）、第２メタル層を示している。図７０は第２ビア（第２メタル−第３メタル間コンタクト）、第３メタル層を示している。図７１は第３ビア（第３メタル−第４メタル間コンタクト）、第４メタル層を示している。 Hereinafter, an example in which the semiconductor devices according to the present invention are arranged in two rows and two columns will be described with reference to FIGS. In these drawings, the same components are denoted by the same reference numerals. FIG. 66 shows a semiconductor device according to the present invention arranged in 2 rows and 2 columns. FIG. 67 shows the transistor layer. FIG. 68 shows the contact layer and the first metal layer. FIG. 69 shows a first via (first metal-second metal contact) and a second metal layer. FIG. 70 shows the second via (second metal-third metal contact) and the third metal layer. FIG. 71 shows a third via (third metal-fourth metal contact) and a fourth metal layer.

１行１列目には選択トランジスタ３０１が配置される。
１行２列目にはインバータ３０２が配置される。
２行１列目にはインバータ３０５が配置される。
２行２列目には選択トランジスタ３０６が配置される。
インバータ３０５と選択トランジスタ３０１は出力端子３３１で接続される。
インバータ３０２と選択トランジスタ３０６は出力端子３３３で接続される。
インバータ３０５の入力端子３２１は、コンタクト３４１を介して出力端子３３３と接続される。
インバータ３０２の入力端子３１８は、コンタクト３３９を介して出力端子３３１と接続される。
１行４列目には選択トランジスタ３０４が配置される。
１行３列目にはインバータ３０３が配置される。
２行４列目にはインバータ３０８が配置される。
２行３列目には選択トランジスタ３０７が配置される。
インバータ３０３と選択トランジスタ３０７は出力端子３３４で接続される。
インバータ３０８と選択トランジスタ３０４は出力端子３３２で接続される。
インバータ３０３の入力端子３１９は、コンタクト３４０を介して出力端子３３２と接続される。
インバータ３０８の入力端子３２３は、コンタクト３４２を介して出力端子３３４と接続される。
選択トランジスタ３０１はゲート導電体３１７を有する。
選択トランジスタ３０６と選択トランジスタ３０７はゲート導電体３２２を有する。
選択トランジスタ３０４はゲート導電体３２０を有する。
３行２列目には選択トランジスタ３１０が配置される。
３行１列目にはインバータ３０９が配置される。
４行２列目にはインバータ３１４が配置される。
４行１列目には選択トランジスタ３１３が配置される。
インバータ３０９と選択トランジスタ３１３は出力端子３３７で接続される。
インバータ３１４と選択トランジスタ３１０は出力端子３３５で接続される。
インバータ３０９の入力端子３２４は、コンタクト３４３を介して出力端子３３５と接続される。
インバータ３１４の入力端子３２８は、コンタクト３４５を介して出力端子３３７と接続される。
３行３列目には選択トランジスタ３１１が配置される。
３行４列目にはインバータ３１２が配置される。
４行３列目にはインバータ３１５が配置される。
４行４列目には選択トランジスタ３１６が配置される。
インバータ３１５と選択トランジスタ３１１は出力端子３３６で接続される。
インバータ３１２と選択トランジスタ３１６は出力端子３３８で接続される。
インバータ３１５の入力端子３２９は、コンタクト３４６を介して出力端子３３８と接続される。
インバータ３１２の入力端子３２６は、コンタクト３４４を介して出力端子３３６と接続される。
選択トランジスタ３１３はゲート導電体３２７を有する。
選択トランジスタ３１０と選択トランジスタ３１１はゲート導電体３２５を有する。
選択トランジスタ３１６はゲート導電体３３０を有する。 A selection transistor 301 is arranged in the first row and the first column.
An inverter 302 is arranged in the first row and the second column.
An inverter 305 is arranged in the second row and the first column.
A selection transistor 306 is arranged in the second row and the second column.
The inverter 305 and the selection transistor 301 are connected by an output terminal 331.
The inverter 302 and the selection transistor 306 are connected by an output terminal 333.
The input terminal 321 of the inverter 305 is connected to the output terminal 333 through the contact 341.
The input terminal 318 of the inverter 302 is connected to the output terminal 331 through the contact 339.
A selection transistor 304 is arranged in the first row and the fourth column.
An inverter 303 is arranged in the first row and the third column.
An inverter 308 is arranged in the second row and the fourth column.
A selection transistor 307 is arranged in the second row and the third column.
The inverter 303 and the selection transistor 307 are connected at the output terminal 334.
The inverter 308 and the selection transistor 304 are connected by an output terminal 332.
The input terminal 319 of the inverter 303 is connected to the output terminal 332 through the contact 340.
The input terminal 323 of the inverter 308 is connected to the output terminal 334 through the contact 342.
The selection transistor 301 has a gate conductor 317.
The selection transistor 306 and the selection transistor 307 have a gate conductor 322.
The selection transistor 304 has a gate conductor 320.
A selection transistor 310 is arranged in the third row and the second column.
An inverter 309 is arranged in the third row and the first column.
An inverter 314 is arranged in the fourth row and the second column.
A selection transistor 313 is arranged in the fourth row and the first column.
The inverter 309 and the selection transistor 313 are connected by an output terminal 337.
The inverter 314 and the selection transistor 310 are connected at the output terminal 335.
The input terminal 324 of the inverter 309 is connected to the output terminal 335 through the contact 343.
The input terminal 328 of the inverter 314 is connected to the output terminal 337 via the contact 345.
A selection transistor 311 is arranged in the third row and the third column.
An inverter 312 is arranged in the third row and the fourth column.
An inverter 315 is arranged in the fourth row and the third column.
A selection transistor 316 is arranged in the fourth row and the fourth column.
The inverter 315 and the selection transistor 311 are connected by an output terminal 336.
The inverter 312 and the selection transistor 316 are connected at the output terminal 338.
The input terminal 329 of the inverter 315 is connected to the output terminal 338 through the contact 346.
The input terminal 326 of the inverter 312 is connected to the output terminal 336 through the contact 344.
The selection transistor 313 has a gate conductor 327.
The selection transistor 310 and the selection transistor 311 have a gate conductor 325.
The select transistor 316 has a gate conductor 330.

インバータ３０２のｎＭＯＳトランジスタ上にコンタクト３４９が配置され、
インバータ３０２のｐＭＯＳトランジスタ上にコンタクト３５０が配置され、
選択トランジスタ３０６上にコンタクト３５７が配置され、
インバータ３０５のｎＭＯＳトランジスタ上にコンタクト３５６が配置され、
インバータ３０５のｐＭＯＳトランジスタ上にコンタクト３５５が配置され、
選択トランジスタ３０１上にコンタクト３４８が配置され、
インバータ３０３のｎＭＯＳトランジスタ上にコンタクト３５２が配置され、
インバータ３０３のｐＭＯＳトランジスタ上にコンタクト３５１が配置され、
選択トランジスタ３０７上にコンタクト３５９が配置され、
インバータ３０８のｎＭＯＳトランジスタ上にコンタクト３６０が配置され、
インバータ３０８のｐＭＯＳトランジスタ上にコンタクト３６１が配置され、
選択トランジスタ３０４上にコンタクト３５３が配置され、
ゲート導電体３１７上にコンタクト３４７が配置され、
ゲート導電体３２２上にコンタクト３５８が配置され、
ゲート導電体３２０上にコンタクト３５４が配置され、
インバータ３０９のｎＭＯＳトランジスタ上にコンタクト３６３が配置され、
インバータ３０９のｐＭＯＳトランジスタ上にコンタクト３６２が配置され、
選択トランジスタ３１３上にコンタクト３７０が配置され、
インバータ３１４のｎＭＯＳトランジスタ上にコンタクト３７１が配置され、
インバータ３１４のｐＭＯＳトランジスタ上にコンタクト３７２が配置され、
選択トランジスタ３１０上にコンタクト３６４が配置され、
インバータ３１５のｎＭＯＳトランジスタ上にコンタクト３７４が配置され、
インバータ３１５のｐＭＯＳトランジスタ上にコンタクト３７３が配置され、
選択トランジスタ３１１上にコンタクト３６６が配置され、
インバータ３１２のｎＭＯＳトランジスタ上にコンタクト３６７が配置され、
インバータ３１２のｐＭＯＳトランジスタ上にコンタクト３６８が配置され、
選択トランジスタ３１６上にコンタクト３７５が配置され、
ゲート導電体３２７上にコンタクト３６９が配置され、
ゲート導電体３２５上にコンタクト３６５が配置され、
ゲート導電体３３０上にコンタクト３７６が配置され、
コンタクト３４７に第１メタル３７７が接続され、
コンタクト３４８に第１メタル３７８が接続され、
コンタクト３４９に第１メタル３７９が接続され、
コンタクト３５０とコンタクト３５１に第１メタル３８０が接続され、
コンタクト３５２に第１メタル３８１が接続され、
コンタクト３５３に第１メタル３８２が接続され、
コンタクト３５４に第１メタル３８３が接続され、
コンタクト３５５とコンタクト３６２に第１メタル３８４が接続され、
コンタクト３５６とコンタクト３６３に第１メタル３８５が接続され、
コンタクト３５７とコンタクト３６４に第１メタル３８６が接続され、
コンタクト３５８に第１メタル３８７が接続され、
コンタクト３６５に第１メタル３８８が接続され、
コンタクト３５９とコンタクト３６６に第１メタル３８９が接続され、
コンタクト３６０とコンタクト３６７に第１メタル３９０が接続され、
コンタクト３６１とコンタクト３６８に第１メタル３９１が接続され、
コンタクト３６９に第１メタル３９２が接続され、
コンタクト３７０に第１メタル３９３が接続され、
コンタクト３７１に第１メタル３９４が接続され、
コンタクト３７２とコンタクト３７３に第１メタル３９５が接続され、
コンタクト３７４に第１メタル３９６が接続され、
コンタクト３７５に第１メタル３９７が接続され、
コンタクト３７６に第１メタル３９８が接続される。 A contact 349 is disposed on the nMOS transistor of the inverter 302,
A contact 350 is disposed on the pMOS transistor of the inverter 302,
A contact 357 is disposed on the selection transistor 306,
A contact 356 is disposed on the nMOS transistor of the inverter 305, and
A contact 355 is disposed on the pMOS transistor of the inverter 305,
A contact 348 is disposed on the select transistor 301,
A contact 352 is arranged on the nMOS transistor of the inverter 303,
A contact 351 is disposed on the pMOS transistor of the inverter 303,
A contact 359 is disposed on the selection transistor 307,
A contact 360 is disposed on the nMOS transistor of the inverter 308,
A contact 361 is arranged on the pMOS transistor of the inverter 308,
A contact 353 is disposed on the selection transistor 304,
A contact 347 is disposed on the gate conductor 317,
A contact 358 is disposed on the gate conductor 322;
A contact 354 is disposed on the gate conductor 320;
A contact 363 is disposed on the nMOS transistor of the inverter 309,
A contact 362 is disposed on the pMOS transistor of the inverter 309,
A contact 370 is disposed on the selection transistor 313,
A contact 371 is arranged on the nMOS transistor of the inverter 314,
A contact 372 is disposed on the pMOS transistor of the inverter 314,
A contact 364 is disposed on the select transistor 310,
A contact 374 is arranged on the nMOS transistor of the inverter 315,
A contact 373 is disposed on the pMOS transistor of the inverter 315,
A contact 366 is disposed on the selection transistor 311,
A contact 367 is disposed on the nMOS transistor of the inverter 312,
A contact 368 is disposed on the pMOS transistor of the inverter 312,
A contact 375 is disposed on the select transistor 316,
A contact 369 is disposed on the gate conductor 327;
A contact 365 is disposed on the gate conductor 325,
A contact 376 is disposed on the gate conductor 330;
A first metal 377 is connected to the contact 347,
A first metal 378 is connected to the contact 348,
A first metal 379 is connected to the contact 349,
The first metal 380 is connected to the contact 350 and the contact 351,
The first metal 381 is connected to the contact 352,
The first metal 382 is connected to the contact 353,
The first metal 383 is connected to the contact 354,
The first metal 384 is connected to the contact 355 and the contact 362,
The first metal 385 is connected to the contact 356 and the contact 363,
The first metal 386 is connected to the contact 357 and the contact 364,
A first metal 387 is connected to the contact 358,
A first metal 388 is connected to the contact 365,
The first metal 389 is connected to the contact 359 and the contact 366,
A first metal 390 is connected to the contact 360 and the contact 367,
The first metal 391 is connected to the contact 361 and the contact 368,
A first metal 392 is connected to the contact 369,
The first metal 393 is connected to the contact 370,
A first metal 394 is connected to the contact 371,
A first metal 395 is connected to the contact 372 and the contact 373,
A first metal 396 is connected to the contact 374,
A first metal 397 is connected to the contact 375,
A first metal 398 is connected to the contact 376.

第１メタル３７８上に第１ビア３９９が配置され、
第１メタル３７９上に第１ビア４００が配置され、
第１メタル３８０上に第１ビア４０１が配置され、
第１メタル３８１上に第１ビア４０２が配置され、
第１メタル３８２上に第１ビア４０３が配置され、
第１メタル３７７上に第１ビア４０４が配置され、
第１メタル３８３上に第１ビア４０５が配置され、
第１メタル３８７上に第１ビア４０６が配置され、
第１メタル３８４上に第１ビア４０７が配置され、
第１メタル３８５上に第１ビア４０８が配置され、
第１メタル３８６上に第１ビア４０９が配置され、
第１メタル３８９上に第１ビア４１０が配置され、
第１メタル３９０上に第１ビア４１１が配置され、
第１メタル３９１上に第１ビア４１２が配置され、
第１メタル３８８上に第１ビア４１３が配置され、
第１メタル３９２上に第１ビア４１４が配置され、
第１メタル３９８上に第１ビア４１５が配置され、
第１メタル３９３上に第１ビア４１６が配置され、
第１メタル３９４上に第１ビア４１７が配置され、
第１メタル３９５上に第１ビア４１８が配置され、
第１メタル３９６上に第１ビア４１９が配置され、
第１メタル３９７上に第１ビア４２０が配置され、
第１ビア３９９に第２メタル４２１が接続され、
第１ビア４００に第２メタル４２２が接続され、
第１ビア４０１に第２メタル４２３が接続され、
第１ビア４０２に第２メタル４２４が接続され、
第１ビア４０３に第２メタル４２５が接続され、
第１ビア４０４、４０５、４０６に第２メタル４２６が接続され、
第１ビア４０７に第２メタル４２７が接続され、
第１ビア４０８に第２メタル４２８が接続され、
第１ビア４０９に第２メタル４２９が接続され、
第１ビア４１０に第２メタル４３０が接続され、
第１ビア４１１に第２メタル４３１が接続され、
第１ビア４１２に第２メタル４３２が接続され、
第１ビア４１３、４１４、４１５に第２メタル４３３が接続され、
第１ビア４１６に第２メタル４３４が接続され、
第１ビア４１７に第２メタル４３５が接続され、
第１ビア４１８に第２メタル４３６が接続され、
第１ビア４１９に第２メタル４３７が接続され、
第１ビア４２０に第２メタル４３８が接続される。 A first via 399 is disposed on the first metal 378,
The first via 400 is disposed on the first metal 379,
A first via 401 is disposed on the first metal 380,
A first via 402 is disposed on the first metal 381,
A first via 403 is disposed on the first metal 382,
A first via 404 is disposed on the first metal 377,
A first via 405 is disposed on the first metal 383,
A first via 406 is disposed on the first metal 387,
A first via 407 is disposed on the first metal 384,
A first via 408 is disposed on the first metal 385,
A first via 409 is disposed on the first metal 386,
A first via 410 is disposed on the first metal 389,
A first via 411 is disposed on the first metal 390,
A first via 412 is disposed on the first metal 391,
A first via 413 is disposed on the first metal 388,
A first via 414 is disposed on the first metal 392,
A first via 415 is disposed on the first metal 398,
A first via 416 is disposed on the first metal 393,
A first via 417 is disposed on the first metal 394,
A first via 418 is disposed on the first metal 395,
A first via 419 is disposed on the first metal 396,
A first via 420 is disposed on the first metal 397,
The second metal 421 is connected to the first via 399,
A second metal 422 is connected to the first via 400,
A second metal 423 is connected to the first via 401,
A second metal 424 is connected to the first via 402,
A second metal 425 is connected to the first via 403,
A second metal 426 is connected to the first vias 404, 405, 406,
A second metal 427 is connected to the first via 407,
A second metal 428 is connected to the first via 408,
The second metal 429 is connected to the first via 409,
The second metal 430 is connected to the first via 410,
A second metal 431 is connected to the first via 411,
A second metal 432 is connected to the first via 412,
The second metal 433 is connected to the first vias 413, 414, 415,
A second metal 434 is connected to the first via 416,
A second metal 435 is connected to the first via 417,
A second metal 436 is connected to the first via 418,
A second metal 437 is connected to the first via 419,
A second metal 438 is connected to the first via 420.

第２メタル４２１上に第２ビア４３９が配置され、
第２メタル４２２上に第２ビア４４０が配置され、
第２メタル４２３上に第２ビア４４１が配置され、
第２メタル４２４上に第２ビア４４２が配置され、
第２メタル４２５上に第２ビア４４３が配置され、
第２メタル４２７上に第２ビア４４４が配置され、
第２メタル４２８上に第２ビア４４５が配置され、
第２メタル４２９上に第２ビア４４６が配置され、
第２メタル４３０上に第２ビア４４７が配置され、
第２メタル４３１上に第２ビア４４８が配置され、
第２メタル４３２上に第２ビア４４９が配置され、
第２メタル４３４上に第２ビア４５０が配置され、
第２メタル４３５上に第２ビア４５１が配置され、
第２メタル４３６上に第２ビア４５２が配置され、
第２メタル４３７上に第２ビア４５３が配置され、
第２メタル４３８上に第２ビア４５４が配置され、
第２ビア４３９に第３メタル４５５が接続され、
第２ビア４４０、４４２、４４５、４４８に第３メタル４５８が接続され、
第２ビア４４１に第３メタル４５６が接続され、
第２ビア４４３に第３メタル４５７が接続され、
第２ビア４４４、４４９、４５２に第３メタル４６１が接続され、
第２ビア４４６に第３メタル４５９が接続され、
第２ビア４４７に第３メタル４６０が接続され、
第２ビア４５０に第３メタル４６２が接続され、
第２ビア４５１に第３メタル４６３が接続され、
第２ビア４５３に第３メタル４６４が接続され、
第２ビア４５４に第３メタル４６５が接続される。 A second via 439 is disposed on the second metal 421,
A second via 440 is disposed on the second metal 422,
A second via 441 is disposed on the second metal 423,
A second via 442 is disposed on the second metal 424,
A second via 443 is disposed on the second metal 425,
A second via 444 is disposed on the second metal 427,
A second via 445 is disposed on the second metal 428,
A second via 446 is disposed on the second metal 429,
A second via 447 is disposed on the second metal 430,
A second via 448 is disposed on the second metal 431,
A second via 449 is disposed on the second metal 432,
A second via 450 is disposed on the second metal 434,
A second via 451 is disposed on the second metal 435,
A second via 452 is disposed on the second metal 436,
A second via 453 is disposed on the second metal 437,
A second via 454 is disposed on the second metal 438,
A third metal 455 is connected to the second via 439,
A third metal 458 is connected to the second vias 440, 442, 445, 448,
A third metal 456 is connected to the second via 441,
A third metal 457 is connected to the second via 443,
A third metal 461 is connected to the second vias 444, 449, 452,
A third metal 459 is connected to the second via 446,
A third metal 460 is connected to the second via 447,
A third metal 462 is connected to the second via 450,
A third metal 463 is connected to the second via 451,
A third metal 464 is connected to the second via 453,
A third metal 465 is connected to the second via 454.

第３メタル４５５上に第３ビア４６６が配置され、
第３メタル４５９上に第３ビア４６８が配置され、
第３メタル４６０上に第３ビア４６９が配置され、
第３メタル４５７上に第３ビア４６７が配置され、
第３メタル４６２上に第３ビア４７０が配置され、
第３メタル４６５上に第３ビア４７１が配置され、
第３ビア４６６、４７０に第４メタル４７２が接続され、
第３ビア４６８に第４メタル４７３が接続され、
第３ビア４６９に第４メタル４７４が接続され、
第３ビア４６７、４７１に第４メタル４７５が接続される。 A third via 466 is disposed on the third metal 455,
A third via 468 is disposed on the third metal 459,
A third via 469 is disposed on the third metal 460,
A third via 467 is disposed on the third metal 457,
A third via 470 is disposed on the third metal 462,
A third via 471 is disposed on the third metal 465,
A fourth metal 472 is connected to the third vias 466 and 470,
A fourth metal 473 is connected to the third via 468,
A fourth metal 474 is connected to the third via 469,
A fourth metal 475 is connected to the third vias 467 and 471.

本発明の半導体装置により、
１本の柱を用いてインバータを構成することにより、
２本の柱で２個のインバータを構成し、
２本の柱で２個の選択トランジスタを構成することにより、
計４本の柱でＳＲＡＭを構成することにより、高集積なＣＭＯＳ ＳＲＡＭを提供することができる。４本の柱でＳＲＡＭを構成するため、集積度が高くなり、高集積なＣＭＯＳ ＳＲＡＭを提供できるので、産業上の利用可能性は極めて大きい。 By the semiconductor device of the present invention,
By constructing an inverter using one pillar,
Two inverters consist of two pillars,
By configuring two select transistors with two pillars,
By configuring the SRAM with a total of four pillars, a highly integrated CMOS SRAM can be provided. Since the SRAM is composed of four pillars, the degree of integration is high, and a highly integrated CMOS SRAM can be provided. Therefore, the industrial applicability is extremely large.

１０１．酸化膜
１０２．ｐ型シリコン
１０３．レジスト
１０４．ｎ型シリコン
１０５．ｎ型シリコン
１０６．酸化膜
１０７．窒化膜
１０８．レジスト
１０９．窒化膜
１１０．窒化膜サイドウォール
１１１．窒化膜サイドウォール
１１２．絶縁物
１１３．絶縁物
１１４．窒化膜
１１５．レジスト
１１６．レジスト
１１７．レジスト
１１８．レジスト
１１９．窒化膜ハードマスク
１２０．窒化膜ハードマスク
１２１．窒化膜ハードマスク
１２２．窒化膜ハードマスク
１２３．酸化膜
１２４．酸化膜
１２５．酸化膜
１２６．酸化膜サイドウォール
１２７．酸化膜サイドウォール
１２８．酸化膜サイドウォール
１２９．酸化膜サイドウォール
１３０．レジスト
１３１．レジスト
１３２．ｐ型シリコン
１３３．ｐ型シリコン
１３４．レジスト
１３５．レジスト
１３６．ｐ型シリコン
１３７．ｐ型シリコン
１３８．ｐ型シリコン
１３９．ｐ型シリコン
１４０．ｎ型高濃度シリコン
１４１．ｎ型高濃度シリコン
１４２．レジスト
１４３．ｐ型高濃度シリコン
１４４．ｐ型高濃度シリコン
１４５．酸化膜
１４６．酸化膜
１４７．酸化膜
１４８．酸化膜
１４９．酸化膜
１５０．高誘電体膜
１５１．金属
１５２．酸化膜
１５３．窒化膜
１５４．窒化膜サイドウォール
１５５．窒化膜サイドウォール
１５６．窒化膜サイドウォール
１５７．窒化膜サイドウォール
１５８．レジスト
１５９．レジスト
１６０．レジスト
１６１．レジスト
１６２．酸化膜
１６３．酸化膜
１６４．酸化膜
１６５．酸化膜
１６６．ゲート導電体
１６７．ゲート導電体
１６８．ゲート導電体
１６９．ゲート導電体
１７０．酸化膜
１７１．酸化膜サイドウォール
１７２．酸化膜サイドウォール
１７３．酸化膜サイドウォール
１７４．酸化膜サイドウォール
１７５．ゲート絶縁物
１７６．ゲート絶縁物
１７７．ゲート絶縁物
１７８．ゲート絶縁物
１７９．レジスト
１８０．レジスト
１８１．ｎ型高濃度シリコン
１８２．ｎ型高濃度シリコン
１８３．ｎ型高濃度シリコン
１８４．ｎ型高濃度シリコン
１８５．レジスト
１８６．ｐ型高濃度シリコン
１８７．ｐ型高濃度シリコン
１８８．シリコンと金属の化合物
１８９．シリコンと金属の化合物
１９０．シリコンと金属の化合物
１９１．シリコンと金属の化合物
１９２．シリコンと金属の化合物
１９３．シリコンと金属の化合物
１９４．シリコンと金属の化合物
１９５．シリコンと金属の化合物
１９６．シリコンと金属の化合物
１９７．シリコンと金属の化合物
１９８．窒化膜
１９９．酸化膜
２００．コンタクト孔
２０１．コンタクト孔
２０２．コンタクト
２０３．コンタクト
２０４．酸化膜
２０５．コンタクト孔
２０６．コンタクト孔
２０７．コンタクト孔
２０８．コンタクト孔
２０９．コンタクト孔
２１０．コンタクト孔
２１１．コンタクト孔
２１２．コンタクト孔
２１３．コンタクト
２１４．コンタクト
２１５．コンタクト
２１６．コンタクト
２１７．コンタクト
２１８．コンタクト
２１９．コンタクト
２２０．コンタクト
２２１．第１メタル
２２２．第１メタル
２２３．第１メタル
２２４．第１メタル
２２５．第１メタル
２２６．第１メタル
２２７．第１メタル
２２８．第１メタル
３０１．選択トランジスタ
３０２．インバータ
３０３．インバータ
３０４．選択トランジスタ
３０５．インバータ
３０６．選択トランジスタ
３０７．選択トランジスタ
３０８．インバータ
３０９．インバータ
３１０．選択トランジスタ
３１１．選択トランジスタ
３１２．インバータ
３１３．選択トランジスタ
３１４．インバータ
３１５．インバータ
３１６．選択トランジスタ
３１７．ゲート導電体
３１８．入力端子
３１９．入力端子
３２０．ゲート導電体
３２１．入力端子
３２２．ゲート導電体
３２３．入力端子
３２４．入力端子
３２５．ゲート導電体
３２６．入力端子
３２７．ゲート導電体
３２８．入力端子
３２９．入力端子
３３０．ゲート導電体
３３１．出力端子
３３２．出力端子
３３３．出力端子
３３４．出力端子
３３５．出力端子
３３６．出力端子
３３７．出力端子
３３８．出力端子
３３９．コンタクト
３４０．コンタクト
３４１．コンタクト
３４２．コンタクト
３４３．コンタクト
３４４．コンタクト
３４５．コンタクト
３４６．コンタクト
３４７．コンタクト
３４８．コンタクト
３４９．コンタクト
３５０．コンタクト
３５１．コンタクト
３５２．コンタクト
３５３．コンタクト
３５４．コンタクト
３５５．コンタクト
３５６．コンタクト
３５７．コンタクト
３５８．コンタクト
３５９．コンタクト
３６０．コンタクト
３６１．コンタクト
３６２．コンタクト
３６３．コンタクト
３６４．コンタクト
３６５．コンタクト
３６６．コンタクト
３６７．コンタクト
３６８．コンタクト
３６９．コンタクト
３７０．コンタクト
３７１．コンタクト
３７２．コンタクト
３７３．コンタクト
３７４．コンタクト
３７５．コンタクト
３７６．コンタクト
３７７．第１メタル
３７８．第１メタル
３７９．第１メタル
３８０．第１メタル
３８１．第１メタル
３８２．第１メタル
３８３．第１メタル
３８４．第１メタル
３８５．第１メタル
３８６．第１メタル
３８７．第１メタル
３８８．第１メタル
３８９．第１メタル
３９０．第１メタル
３９１．第１メタル
３９２．第１メタル
３９３．第１メタル
３９４．第１メタル
３９５．第１メタル
３９６．第１メタル
３９７．第１メタル
３９８．第１メタル
３９９．第１ビア
４００．第１ビア
４０１．第１ビア
４０２．第１ビア
４０３．第１ビア
４０４．第１ビア
４０５．第１ビア
４０６．第１ビア
４０７．第１ビア
４０８．第１ビア
４０９．第１ビア
４１０．第１ビア
４１１．第１ビア
４１２．第１ビア
４１３．第１ビア
４１４．第１ビア
４１５．第１ビア
４１６．第１ビア
４１７．第１ビア
４１８．第１ビア
４１９．第１ビア
４２０．第１ビア
４２１．第２メタル
４２２．第２メタル
４２３．第２メタル
４２４．第２メタル
４２５．第２メタル
４２６．第２メタル
４２７．第２メタル
４２８．第２メタル
４２９．第２メタル
４３０．第２メタル
４３１．第２メタル
４３２．第２メタル
４３３．第２メタル
４３４．第２メタル
４３５．第２メタル
４３６．第２メタル
４３７．第２メタル
４３８．第２メタル
４３９．第２ビア
４４０．第２ビア
４４１．第２ビア
４４２．第２ビア
４４３．第２ビア
４４４．第２ビア
４４５．第２ビア
４４６．第２ビア
４４７．第２ビア
４４８．第２ビア
４４９．第２ビア
４５０．第２ビア
４５１．第２ビア
４５２．第２ビア
４５３．第２ビア
４５４．第２ビア
４５５．第３メタル
４５６．第３メタル
４５７．第３メタル
４５８．第３メタル
４５９．第３メタル
４６０．第３メタル
４６１．第３メタル
４６２．第３メタル
４６３．第３メタル
４６４．第３メタル
４６５．第３メタル
４６６．第３ビア
４６７．第３ビア
４６８．第３ビア
４６９．第３ビア
４７０．第３ビア
４７１．第３ビア
４７２．第４メタル
４７３．第４メタル
４７４．第４メタル
４７５．第４メタル
５０１．インバータ
５０２．インバータ
５０３．選択トランジスタ
５０４．選択トランジスタ 101. Oxide film 102. p-type silicon 103. Resist 104. n-type silicon 105. n-type silicon 106. Oxide film 107. Nitride film 108. Resist 109. Nitride film 110. Nitride film sidewall 111. Nitride film sidewall 112. Insulator 113. Insulator 114. Nitride film 115. Resist 116. Resist 117. Resist 118. Resist 119. Nitride hard mask 120. Nitride hard mask 121. Nitride hard mask 122. Nitride hard mask 123. Oxide film 124. Oxide film 125. Oxide film 126. Oxide film side wall 127. Oxide film sidewall 128. Oxide film side wall 129. Oxide film sidewall 130. Resist 131. Resist 132. p-type silicon 133. p-type silicon 134. Resist 135. Resist 136. p-type silicon 137. p-type silicon 138. p-type silicon 139. p-type silicon 140. n-type high-concentration silicon 141. n-type high-concentration silicon 142. Resist 143. p-type high-concentration silicon 144. p-type high-concentration silicon 145. Oxide film 146. Oxide film 147. Oxide film 148. Oxide film 149. Oxide film 150. High dielectric film 151. Metal 152. Oxide film 153. Nitride film 154. Nitride film sidewall 155. Nitride film sidewall 156. Nitride film side wall 157. Nitride film side wall 158. Resist 159. Resist 160. Resist 161. Resist 162. Oxide film 163. Oxide film 164. Oxide film 165. Oxide film 166. Gate conductor 167. Gate conductor 168. Gate conductor 169. Gate conductor 170. Oxide film 171. Oxide film side wall 172. Oxide film side wall 173. Oxide film side wall 174. Oxide film sidewall 175. Gate insulator 176. Gate insulator 177. Gate insulator 178. Gate insulator 179. Resist 180. Resist 181. n-type high-concentration silicon 182. n-type high-concentration silicon 183. n-type high-concentration silicon 184. n-type high-concentration silicon 185. Resist 186. p-type high-concentration silicon 187. p-type high-concentration silicon 188. Compound of silicon and metal 189. Compound of silicon and metal Compound of silicon and metal 191. Compound of silicon and metal 192. Compound of silicon and metal 193. Compound of silicon and metal 194. Compound of silicon and metal 195. Compound of silicon and metal 196. Compound of silicon and metal 197. Compound of silicon and metal198. Nitride film 199. Oxide film 200. Contact hole 201. Contact hole 202. Contact 203. Contact 204. Oxide film 205. Contact hole 206. Contact hole 207. Contact hole 208. Contact hole 209. Contact hole 210. Contact hole 211. Contact hole 212. Contact hole 213. Contact 214. Contact 215. Contact 216. Contact 217. Contact 218. Contact 219. Contact 220. Contact 221. First metal 222. First metal 223. First metal 224. First metal 225. First metal 226. First metal 227. First metal 228. First metal 301. Select transistor 302. Inverter 303. Inverter 304. Select transistor 305. Inverter 306. Select transistor 307. Select transistor 308. Inverter 309. Inverter 310. Select transistor 311. Select transistor 312. Inverter 313. Select transistor 314. Inverter 315. Inverter 316. Select transistor 317. Gate conductor 318. Input terminal 319. Input terminal 320. Gate conductor 321. Input terminal 322. Gate conductor 323. Input terminal 324. Input terminal 325. Gate conductor 326. Input terminal 327. Gate conductor 328. Input terminal 329. Input terminal 330. Gate conductor 331. Output terminal 332. Output terminal 333. Output terminal 334. Output terminal 335. Output terminal 336. Output terminal 337. Output terminal 338. Output terminal 339. Contact 340. Contact 341. Contact 342. Contact 343. Contact 344. Contact 345. Contact 346. Contact 347. Contact 348. Contact 349. Contact 350. Contact 351. Contact 352. Contact 353. Contact 354. Contact 355. Contact 356. Contact 357. Contact 358. Contact 359. Contact 360. Contact 361. Contact 362. Contact 363. Contact 364. Contact 365. Contact 366. Contact 367. Contact 368. Contact 369. Contact 370. Contact 371. Contact 372. Contact 373. Contact 374. Contact 375. Contact 376. Contact 377. First metal 378. First metal 379. First metal 380. First metal 381. First metal 382. First metal 383. First metal 384. First metal 385. First metal 386. First metal 387. First metal 388. First metal 389. First metal 390. First metal 391. First metal 392. First metal 393. First metal 394. First metal 395. First metal 396. First metal 397. First metal 398. First metal 399. First via 400. First via 401. First via 402. First via 403. First via 404. First via 405. First via 406. First via 407. First via 408. First via 409. First via 410. First via 411. First via 412. First via 413. First via 414. First via 415. First via 416. First via 417. First via 418. First via 419. First via 420. First via 421. Second metal 422. Second metal 423. Second metal 424. Second metal 425. Second metal 426. Second metal 427. Second metal 428. Second metal 429. Second metal 430. Second metal 431. Second metal 432. Second metal 433. Second metal 434. Second metal 435. Second metal 436. Second metal 437. Second metal 438. Second metal 439. Second via 440. Second via 441. Second via 442. Second via 443. Second via 444. Second via 445. Second via 446. Second via 447. Second via 448. Second via 449. Second via 450. Second via 451. Second via 452. Second via 453. Second via 454. Second via 455. Third metal 456. Third metal 457. Third metal 458. Third metal 459. Third metal 460. Third metal 461. Third metal 462. Third metal 463. Third metal 464. Third metal 465. Third metal 466. Third via 467. Third via 468. Third via 469. Third via 470. Third via 471. Third via 472. Fourth metal 473. Fourth metal 474. Fourth metal 475. Fourth metal 501. Inverter 502. Inverter 503. Select transistor 504. Select transistor

Claims (3)

基板上に行列状に配列された２つのインバータ及び２つの選択トランジスタを備えた半導体装置であって、
第１の第１導電型半導体と、該第１の第１導電型半導体とは極性が異なる第１の第２導電型半導体と、前記第１の第１導電型半導体と前記第１の第２導電型半導体との間に配置される第１の絶縁物が一体となり基板に対して垂直に延びる１本の第１の柱と、
前記第１の第１導電型半導体の上に配置され、前記第１の第１導電型半導体とは極性が異なる第１の第２導電型高濃度半導体と、
前記第１の第１導電型半導体の下に配置され、前記第１の第１導電型半導体とは極性が異なる第２の第２導電型高濃度半導体と、
前記第１の第２導電型半導体の上に配置され、前記第１の第２導電型半導体とは極性が異なる第１の第１導電型高濃度半導体と、
前記第１の第２導電型半導体の下に配置され、前記第１の第２導電型半導体とは極性が異なる第２の第１導電型高濃度半導体と、
前記第１の柱を取り囲む第１のゲート絶縁物と、
前記第１のゲート絶縁物を取り囲む第１のゲート導電体と、
を有する一行二列目の第１のインバータとを有し、
前記第１の第１導電型半導体の全ての下面は、前記第２の第２導電型高濃度半導体に接し、
前記第１の第２導電型半導体の全ての下面は、前記第２の第１導電型高濃度半導体に接し、
前記第１の絶縁物は、前記第２の第２導電型高濃度半導体と前記第２の第１導電型高濃度半導体とに挟まれることを特徴とし、
前記半導体装置は、更に、
第２の第１導電型半導体と、該第２の第１導電型半導体とは極性が異なる第２の第２導電型半導体と、前記第２の第１導電型半導体と前記第２の第２導電型半導体との間に配置される第２の絶縁物が一体となり基板に対して垂直に延びる１本の第２の柱と、
前記第２の第１導電型半導体の上に配置され、前記第２の第１導電型半導体とは極性が異なる第３の第２導電型高濃度半導体と、
前記第２の第１導電型半導体の下に配置され、前記第２の第１導電型半導体とは極性が異なる第４の第２導電型高濃度半導体と、
前記第２の第２導電型半導体の上に配置され、前記第２の第２導電型半導体とは極性が異なる第３の第１導電型高濃度半導体と、
前記第２の第２導電型半導体の下に配置され、前記第２の第２導電型半導体とは極性が異なる第４の第１導電型高濃度半導体と、
前記第２の柱を取り囲む第２のゲート絶縁物と、
前記第２のゲート絶縁物を取り囲む第２のゲート導電体と、
を有する二行一列目の第２のインバータとを有し、
前記第２の第１導電型半導体の全ての下面は、前記第４の第２導電型高濃度半導体に接し、
前記第２の第２導電型半導体の全ての下面は、前記第４の第１導電型高濃度半導体に接し、
前記第２の絶縁物は、前記第４の第２導電型高濃度半導体と前記第４の第１導電型高濃度半導体とに挟まれることを特徴とし、
前記半導体装置は、更に、
第３の第１導電型半導体からなる第３の柱と、
前記第３の第１導電型半導体の上に配置され、前記第３の第１導電型半導体とは極性が異なる第５の第２導電型高濃度半導体と、
前記第３の第１導電型半導体の下に配置され、前記第３の第１導電型半導体とは極性が異なる第６の第２導電型高濃度半導体と、
前記第３の柱を取り囲む第３のゲート絶縁物と、
前記第３のゲート絶縁物を取り囲む第３のゲート導電体と、
を有する一行一列目の選択トランジスタと、
第４の第１導電型半導体からなる第４の柱と、
前記第４の第１導電型半導体の上に配置され、前記第４の第１導電型半導体とは極性が異なる第７の第２導電型高濃度半導体と、
前記第４の第１導電型半導体の下に配置され、前記第４の第１導電型半導体とは極性が異なる第８の第２導電型高濃度半導体と、
前記第４の柱を取り囲む第４のゲート絶縁物と、
前記第４のゲート絶縁物を取り囲む第４のゲート導電体と、
を有する二行二列目の選択トランジスタと、
を有し、
第２の第１導電型高濃度半導体と第２の第２導電型高濃度半導体と第８の第２導電型高濃度半導体が接続され、
第８の第２導電型高濃度半導体と第２のゲート導電体とが前記二行二列目の選択トランジスタと前記二行一列目の第２のインバータの間のコンタクトにより接続され、
前記二行二列目の選択トランジスタと前記二行一列目の第２のインバータの間の前記コンタクトの上面は、前記第３の第２導電型高濃度半導体の上面より低いことを特徴とし、
前記第３の第２導電型高濃度半導体上に形成されるコンタクトを有し、
前記第３の第２導電型高濃度半導体上に形成される前記コンタクトの中心は、前記第３の第２導電型高濃度半導体の中心より前記二行二列目の選択トランジスタ側にあって、
前記第３の第１導電型高濃度半導体上に形成されるコンタクトを有し、
前記第３の第１導電型高濃度半導体上に形成される前記コンタクトの中心は、前記第３の第１導電型高濃度半導体の中心より前記二行二列目の選択トランジスタと反対側にあって、
第４の第１導電型高濃度半導体と第４の第２導電型高濃度半導体と第６の第２導電型高濃度半導体が接続され、
第６の第２導電型高濃度半導体と第１のゲート導電体とが前記一行一列目の選択トランジスタと前記一行二列目の第１のインバータの間のコンタクトにより接続され、
前記一行一列目の選択トランジスタと前記一行二列目の第１のインバータの間の前記コンタクトの上面は、前記第１の第２導電型高濃度半導体の上面より低いことを特徴とし、
前記第１の第２導電型高濃度半導体上に形成されるコンタクトを有し、
前記第１の第２導電型高濃度半導体上に形成される前記コンタクトの中心は、前記第１の第２導電型高濃度半導体の中心より前記一行一列目の選択トランジスタ側にあって、
前記第１の第１導電型高濃度半導体上に形成されるコンタクトを有し、
前記第１の第１導電型高濃度半導体上に形成される前記コンタクトの中心は、前記第１の第１導電型高濃度半導体の中心より前記一行一列目の選択トランジスタと反対側にあることを特徴とする半導体装置。 A semiconductor device comprising two inverters and two selection transistors arranged in a matrix on a substrate,
A first first conductivity type semiconductor; a first second conductivity type semiconductor having a polarity different from that of the first first conductivity type semiconductor; the first first conductivity type semiconductor; and the first second conductivity type. A first pillar integrated with a first insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A first second conductivity type high concentration semiconductor disposed on the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A second second conductivity type high-concentration semiconductor disposed under the first first conductivity type semiconductor and having a polarity different from that of the first first conductivity type semiconductor;
A first first-conductivity-type high-concentration semiconductor disposed on the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A second first-conductivity-type high-concentration semiconductor disposed under the first second-conductivity-type semiconductor and having a polarity different from that of the first second-conductivity-type semiconductor;
A first gate insulator surrounding the first pillar;
A first gate conductor surrounding the first gate insulator;
The first inverter in the first row and the second column having
All lower surfaces of the first first conductivity type semiconductor are in contact with the second second conductivity type high concentration semiconductor,
All lower surfaces of the first second conductivity type semiconductor are in contact with the second first conductivity type high concentration semiconductor,
The first insulator is sandwiched between the second second-conductivity type high-concentration semiconductor and the second first-conductivity type high-concentration semiconductor,
The semiconductor device further includes:
A second first conductive semiconductor, a second second conductive semiconductor having a polarity different from that of the second first conductive semiconductor, the second first conductive semiconductor, and the second second. A second pillar integrally formed with the second insulator disposed between the conductive semiconductor and extending perpendicularly to the substrate;
A third second-conductivity-type high-concentration semiconductor disposed on the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A fourth second-conductivity-type high-concentration semiconductor disposed under the second first-conductivity-type semiconductor and having a polarity different from that of the second first-conductivity-type semiconductor;
A third first-conductivity type high-concentration semiconductor disposed on the second second-conductivity type semiconductor and having a polarity different from that of the second second-conductivity type semiconductor;
A fourth first-conductivity-type high-concentration semiconductor disposed under the second second-conductivity-type semiconductor and having a polarity different from that of the second second-conductivity-type semiconductor;
A second gate insulator surrounding the second pillar;
A second gate conductor surrounding the second gate insulator;
And a second inverter in the second row and first column having
All lower surfaces of the second first conductivity type semiconductor are in contact with the fourth second conductivity type high-concentration semiconductor,
All lower surfaces of the second second conductivity type semiconductor are in contact with the fourth first conductivity type high concentration semiconductor,
The second insulator is sandwiched between the fourth second-conductivity-type high-concentration semiconductor and the fourth first-conductivity-type high-concentration semiconductor,
The semiconductor device further includes:
A third pillar made of a third first conductivity type semiconductor;
A fifth second-conductivity-type high-concentration semiconductor disposed on the third first-conductivity-type semiconductor and having a polarity different from that of the third first-conductivity-type semiconductor;
A sixth second-conductivity type high-concentration semiconductor disposed under the third first-conductivity type semiconductor and having a polarity different from that of the third first-conductivity type semiconductor;
A third gate insulator surrounding the third pillar;
A third gate conductor surrounding the third gate insulator;
A selection transistor in the first row and the first column having:
A fourth column made of a fourth first conductivity type semiconductor;
A seventh second-conductivity type high-concentration semiconductor disposed on the fourth first-conductivity type semiconductor and having a polarity different from that of the fourth first-conductivity type semiconductor;
An eighth second conductivity type high-concentration semiconductor disposed below the fourth first conductivity type semiconductor and having a polarity different from that of the fourth first conductivity type semiconductor;
A fourth gate insulator surrounding the fourth pillar;
A fourth gate conductor surrounding the fourth gate insulator;
A second row and second column selection transistor having:
Have
The second first conductivity type high concentration semiconductor, the second second conductivity type high concentration semiconductor, and the eighth second conductivity type high concentration semiconductor are connected,
Connected second conductivity type eighth high-concentration semiconductor and the second gate conductor is the contact between the second inverter of the second line first row and the second row second column selection transistors,
The top surface of the contact between the selection transistor in the second row and second column and the second inverter in the second row and first column is lower than the top surface of the third second-conductivity-type high-concentration semiconductor,
A contact formed on the third second conductivity type high concentration semiconductor;
The center of the contact formed on the third second-conductivity type high-concentration semiconductor is closer to the select transistor in the second row and second column than the center of the third second-conductivity type high-concentration semiconductor,
A contact formed on the third first-conductivity-type high-concentration semiconductor;
The center of the contact formed on the third first-conductivity type high-concentration semiconductor is on the opposite side of the second row and second column selection transistor from the center of the third first-conductivity type high-concentration semiconductor. And
A fourth first conductivity type high concentration semiconductor, a fourth second conductivity type high concentration semiconductor, and a sixth second conductivity type high concentration semiconductor are connected;
A sixth second-conductivity type high-concentration semiconductor and a first gate conductor are connected by a contact between the selection transistor in the first row and first column and the first inverter in the first row and second column;
The upper surface of the contact between the selection transistor in the first row and first column and the first inverter in the first row and second column is lower than the upper surface of the first second conductivity type high-concentration semiconductor,
A contact formed on the first second conductivity type high concentration semiconductor;
The center of the contact formed on the first second-conductivity type high-concentration semiconductor is closer to the select transistor in the first row and first column than the center of the first second-conductivity type high-concentration semiconductor,
A contact formed on the first first conductivity type high concentration semiconductor;
The center of the contact formed on the first first-conductivity-type high-concentration semiconductor is on the opposite side of the first row and first-column select transistor from the center of the first first-conductivity-type high-concentration semiconductor. A featured semiconductor device. 前記半導体の全ては、シリコンであることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein all of the semiconductors are silicon. 第１導電型はｐ型であり、第２導電型はｎ型であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.
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