JP5493257B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a plating layer on an external connection lead, and more particularly to a semiconductor device having a Pb-free plating layer on an external connection lead.

  The resin-encapsulated semiconductor package includes external connection leads for connection to a printed circuit board. Since the external connection lead is generally formed of Cu or Fe—Ni alloy, the wettability with respect to the molten solder containing Sn is poor. Therefore, a plating layer is applied to the external connection lead. By applying a plating layer containing Sn to the external connection lead, the solderability can be improved, and a dense solder layer for connecting the external connection lead and the printed board can be formed.

  Conventionally, Sn—Pb alloy has been used for this plating layer, but Pb-free alloy has been used in recent years for reasons such as environmental pollution. However, when the plating layer is formed of a Pb-free alloy, metal whiskers are likely to be generated and grow from the surface of the plating layer as compared with the case of the Sn—Pb alloy. This metal whisker is generated and grows mainly by the internal stress of the plating layer. When a metal whisker grows and an electrical connection between adjacent external connection leads is electrically short-circuited, the semiconductor package does not operate normally. Therefore, there has conventionally been a method for manufacturing a semiconductor device that can relieve internal stress of a Pb-free plated layer. It has been proposed (see, for example, Patent Document 1).

In the conventional method for manufacturing a semiconductor device, the lead for external connection is formed of an Fe—Ni alloy, and a plating layer made of an Sn—Cu alloy is formed on the surface thereof. Next, using a heat treatment furnace, heat treatment is performed at a temperature equal to or higher than the melting point of the plating layer to melt the plating layer. At this time, a temperature equal to or higher than the melting point of the plating layer is maintained for 20 seconds or more. By this heat treatment, the grain boundary of the plating layer can be eliminated. Moreover, the oxide film formed on the surface of the plating layer can be destroyed by this heat treatment. Thereby, the internal stress of a plating layer can be relieved and generation | occurrence | production of a whisker can be suppressed.
JP 2007-81235 A

  However, the semiconductor device manufactured by the above-described conventional manufacturing method can relieve the internal stress of the plating layer generated during manufacturing, but cannot relieve the internal stress of the plating layer generated after manufacturing.

  FIG. 3 is a cross-sectional view of a plating layer schematically showing the problems of a semiconductor device manufactured by a conventional manufacturing method. In FIG. 3, the plating layer 6 is laminated on the external connection lead 14b. In this case, internal stress is generated in the plating layer 6 after manufacture due to first to third causes described later.

The first cause is the difference between the thermal expansion of the plating layer 6 (arrow B) and the thermal expansion of the external connection lead 14b (arrow A). Plating layer 6 (Sn23 × 10 ⁻⁶ / ° C.) having different thermal expansion coefficient and lead 14 b for external connection (Fe-42Ni alloy (weight%, the same applies hereinafter)) 5 × 10 ⁻⁶ / ° C., Cu 17 × 10 ⁻⁶ / When the temperature rises, compressive stress is generated in the plating layer 6, and tensile stress is generated in the external connection lead 14b.

The second cause is a diffusion reaction between the plating layer 6 and the external connection lead 14b. Since the plating layer 6 and the external connection lead 14b are adjacent to each other, they undergo a diffusion reaction. When an Fe—Ni alloy is used for the external connection lead 14 b, the Ni component diffuses into the plating layer 6, and the Ni—Sn intermetallic compound such as Ni ₃ Sn, Ni ₃ Sn ₂ , Ni ₃ Sn _4, etc. 2 precipitates out. When Cu is used for the external connection lead 14 b, the Cu component diffuses into the plating layer 6, and the Cu—Sn intermetallic compound 2 such as Cu ₃ Sn and Cu ₆ Sn ₅ is deposited on the plating layer 6. Since these intermetallic compounds 2 precipitate while volume expansion in the direction of arrow C, compressive stress is generated in the plating layer 6. Further, when the temperature rises, the intermetallic compound 2 generates an internal stress in the plating layer 6 due to a difference in thermal expansion from the plating layer 6.

  The third cause is corrosion of the plating layer 6. The surface of the plating layer 6 is provided with an organic coating (not shown) for protecting it from moisture in the air, but is corroded when the organic coating is deteriorated. When the surface of the plating layer 6 is corroded, fine particles 4 containing Sn oxide as a main component are deposited on the surface of the plating layer 6. Since the fine particles 4 containing Sn oxide as a main component are deposited while volume-expanding in the direction of arrow D, compressive stress is generated in the plating layer 6. Further, the fine particles 4 containing Sn oxide as a main component generate internal stress in the plating layer 6 due to a difference in thermal expansion from the plating layer 6 when the temperature rises.

  The present invention has been made in view of the above points, and provides a semiconductor device that can alleviate internal stress of a plating layer generated after manufacturing and can suppress generation and growth of whiskers from the surface of the plating layer. Objective.

According to one aspect of the invention ,
In a method for manufacturing a semiconductor device having a plating layer on a lead for external connection,
The plating layer has a first layer and a second layer formed on the first layer,
Wherein the second layer, the maximum operating temperature higher than the solidus temperature or melting point during vehicle, formed by Pb-free alloy or Sn containing Sn,
Said first layer, said vehicle when the maximum operating temperature lower than the solidus temperature or the melting point of, formed by Pb-free alloy containing Sn, the method of manufacturing a semiconductor device is provided.

According to the present invention, when the temperature of the plating layer rises to a predetermined value or more, at least a part of the first layer is melted, and the external connection lead that is the first cause is due to the viscous flow of the first layer. And thermal stress due to a difference in thermal expansion between the plating layer and the plating layer can be reduced. Therefore, the internal stress of the plating layer generated after production can be relaxed, and the generation and growth of whiskers from the plating layer can be suppressed.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  1A and 1B are diagrams showing an embodiment of a semiconductor device according to the present invention, in which FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line AA in FIG.

  In the semiconductor device of this embodiment, a semiconductor element 12 is mounted on a die pad 11 as shown in FIG. The semiconductor element 12 is electrically connected to the internal connection lead 14 a by a bonding wire 13. The die pad 11, the semiconductor element 12, the bonding wire 13, and the internal connection lead 14a are sealed with an epoxy resin 15 containing carbon and protected from light, moisture in the air, and the like. The external connection lead 14b extends from the internal connection lead 14a and protrudes from the sealing resin 15 to the outside. A plating layer 16 for improving solderability is formed on the surface of the external connection lead 14b, and the external connection lead 14b is soldered to a printed board (not shown). For this reason, a signal from the printed circuit board can be transmitted to the semiconductor element 12 and a result processed by the semiconductor element 12 can be taken out as a signal.

  As the semiconductor element 12, for example, an IC or LSI in which a large number of transistors are incorporated in a Si chip can be used. The semiconductor element 12 processes an input signal from the printed circuit board and outputs the processed result to the printed circuit board as an output signal.

  For the die pad 11 and the lead 14, Cu having excellent conductivity and heat dissipation and Fe-42Ni alloy having excellent thermal expansion difference from the semiconductor element 12 are used, and these metal plates are punched with a precision die. Or by etching these metal plates.

  A Pb-free plating layer 16 is formed on the external connection lead 14b by using an electrolytic plating method in order to improve solderability.

  As shown in FIG. 1B, the plating layer 16 of the present embodiment includes a low melting point plating layer 16a and a high melting point plating layer 16b formed on the low melting point plating layer 16a. Have. These low melting point plating layer 16a and high melting point plating layer 16b are each laminated by 0.5 μm or more by electrolytic plating. When the thickness is less than 0.5 μm, the low melting point plating layer 16a and the high melting point plating layer 16b are not sufficiently thick, so that the effects of the low melting point plating layer 16a and the high melting point plating layer 16b described later are not sufficiently exhibited.

  The high melting point plating layer 16b is formed of a Pb-free alloy having a solidus temperature or a melting point higher than the maximum use temperature. In the present embodiment, the maximum operating temperature means the maximum temperature of the plating layer 16 when the semiconductor device is actually used. In the case of an in-vehicle semiconductor device, the maximum use temperature may reach 70 ° C. or more due to the irradiation heat of sunlight under the sun, heat generation of other in-vehicle components, etc., depending on the installation location in the vehicle.

  For example, when the maximum use temperature is 120 ° C., the high melting point plating layer 16b includes Sn (melting point 232 ° C.), Sn-3.5Ag alloy (melting point 221 ° C.), Sn-0.7Cu alloy (melting point 227 ° C.), An Sn-4Bi alloy (solidus temperature 217 ° C.) can be used.

  Since the high melting point plating layer 16b does not melt even at the highest use temperature, it does not easily react with the organic coating applied to the surface of the high melting point plating layer 16b. For this reason, deterioration of the organic coating can be suppressed, and the refractory plating layer 16b can be protected from moisture in the air.

  Further, since the high melting point plating layer 16b does not melt even at the maximum use temperature, the molten low melting point plating layer 16a is formed by the inner wall of the solid high melting point plating layer 16b and the outer wall of the solid external connection lead 14b. Can be prevented.

  The low melting point plating layer 16a is formed of a Pb-free alloy having a solidus temperature or a melting point lower than the maximum use temperature.

  For example, when the maximum use temperature is 120 ° C., the low melting point plating layer 16 a includes an Sn-52In alloy (melting point 117 ° C.) that is completely melted at 120 ° C., and an Sn-48In alloy (solid phase wire that is partially melted at 120 ° C. Temperature 117 ° C., liquidus temperature 131 ° C.).

  Alternatively, when the maximum use temperature is 150 ° C., in addition to the above Sn-52In alloy and Sn-48In alloy, Sn-58Bi alloy (melting point 139 ° C.) that melts all at 150 ° C., Sn that partially melts at 150 ° C. A −20 Bi alloy (solidus temperature 144 ° C., liquidus temperature 208 ° C.) can be used.

  Thus, the low melting point plating layer 16a is partially melted at least at the maximum use temperature. For this reason, the internal stress of the plating layer 16 generated after manufacture can be relaxed due to the first to third causes described above. Hereinafter, the details of the relaxation of the internal stress of the plating layer 16 will be described with reference to FIG.

  First, the difference in thermal expansion between the plating layer 16 and the external connection lead 14b, which is the first cause, will be described. As described above, when the temperature rises, compressive stress is generated in the plating layer 16 due to the difference in thermal expansion between the plating layer 16 and the external connection lead 14b.

  Here, when at least a part of the low melting point plating layer 16a is melted, the plating layer 16 can be freely thermally expanded without being constrained by the external connection leads 14b due to the viscous flow of the low melting point plating layer 16a. Thereby, the compressive stress which generate | occur | produces in the plating layer 16 due to a thermal expansion difference can be relieved.

  As a result, the internal stress of the plating layer 16 generated after manufacture can be relaxed, and the generation and growth of whiskers from the plating layer 16 can be suppressed.

  Next, the diffusion reaction between the external connection lead 14b and the plating layer 16, which is the second cause, will be described. As described above, when the intermetallic compound 2 precipitates while expanding in volume due to the diffusion reaction between the external connection lead 14 b and the plating layer 16, a compressive stress is generated in the plating layer 16. Further, as described above, the deposited intermetallic compound 2 generates an internal stress in the plating layer 16 due to a difference in thermal expansion with the plating layer 16 when the temperature rises.

  Here, when at least a part of the low-melting point plating layer 16a is melted, as shown in FIG. 2, the intermetallic compound 2 deposited on the low-melting point plating layer 16a is decomposed by the convection of the low-melting point plating layer 16a. Can be dispersed. Even after the low melting point plating layer 16a is solidified, the intermetallic compound 2 is dispersed in a wide range, so that the internal stress generated due to the difference in thermal expansion between the plating layer 16 and the intermetallic compound 2 can be dispersed. it can. Thereby, the compressive stress which generate | occur | produces in the plating layer 16 resulting from precipitation of an intermetallic compound can be relieved.

  When at least a part of the low melting point plating layer 16a is melted, the compressive stress generated in the plating layer 16 due to the precipitation of the intermetallic compound 2 can be released by the viscous flow of the low melting point plating layer 16a. Thereby, the compressive stress which generate | occur | produces in the plating layer 16 resulting from precipitation of an intermetallic compound can be relieved.

  As a result, the internal stress of the plating layer 16 generated after manufacture can be relaxed, and the generation and growth of whiskers from the plating layer 16 can be suppressed.

  Finally, the corrosion of the plating layer 16 that is the third cause will be described. As described above, when the fine particles 4 containing Sn oxide as a main component are deposited while being expanded due to corrosion of the high melting point plating layer 16b, compressive stress is generated in the plating layer 16. Further, as described above, the fine particles 4 mainly composed of precipitated Sn oxide generate internal stress in the plating layer 16 due to a difference in thermal expansion from the plating layer 16 when the temperature rises.

  Here, when at least a part of the low melting point plating layer 16a is melted, as shown in FIG. 2, fine particles 4 mainly composed of Sn oxide deposited on the high melting point plating layer 16b by convection of the low melting point plating layer 16a. Can be decomposed and dispersed in a wide range. Even after the low melting point plating layer 16a is solidified, the fine particles 4 mainly composed of Sn oxide are dispersed in a wide range, so that the internal stress generated due to the difference in thermal expansion between the plating layer 16 and the fine particles 4 is reduced. Can be dispersed. Thereby, the compressive stress which generate | occur | produces in the plating layer 16 due to corrosion of the plating layer 16 can be relieved.

  Further, when at least a part of the low melting point plating layer 16a is melted, the compressive stress generated in the plating layer 16 due to the precipitation of the fine particles 4 mainly composed of Sn oxide is released by the viscous flow of the low melting point plating layer 16a. Can do. Thereby, the compressive stress which generate | occur | produces in the plating layer 16 due to corrosion of the plating layer 16 can be relieved.

  As a result, the internal stress of the plating layer 16 generated after manufacture can be relaxed, and the generation and growth of whiskers from the plating layer 16 can be suppressed.

  Thus, in the semiconductor device of this example, the plating layer 16 has the low melting point plating layer 16a and the high melting point plating layer 16b formed on the low melting point plating layer 16a. , Formed of a metal having a solidus temperature or a melting point lower than the maximum use temperature. As a result, when the temperature of the plating layer 16 rises to a predetermined value or more, at least a part of the low melting point plating layer 16a is melted, and the plating layer 16 generated after the production due to the viscous flow and convection of the low melting point plating layer 16a. The internal stress can be relaxed, and the generation and growth of whiskers from the plating layer 16 can be suppressed.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, although the plating layer 16 of the present embodiment includes the low melting point plating layer 16a and the high melting point plating layer 16b formed on the low melting point plating layer 16a, the plating which is at least the first cause described above. As long as the internal stress caused by the difference in thermal expansion between the layer 16 and the external connection lead 14b can be alleviated, the laminated structure is not limited. For example, between the low melting point plating layer 16a and the high melting point plating layer 16b In addition, a third plating layer may be formed, or a third plating layer may be formed between the external connection lead 14b and the low melting point plating layer 16a.

  In this example, Sn-52In alloy, Sn-48In alloy, Sn-58Bi alloy, and Sn-20Bi alloy were used for the low melting point plating layer 16a. As long as it is a low Pb-free alloy, its chemical composition is not limited.

It is the figure which showed one Example of the structure of the semiconductor device of this invention. It is sectional drawing of the plating layer 16 which showed an example of the state which at least one part of the low melting-point plating layer 16a fuse | melted. It is sectional drawing of the plating layer 6 which showed typically the problem of the semiconductor device manufactured with the conventional manufacturing method.

Explanation of symbols

12 Semiconductor element 14a Internal connection lead 14b External connection lead 16 Plating layer 16a Low melting point plating layer 16b High melting point plating layer

Claims (1)

In a method for manufacturing a semiconductor device having a plating layer on a lead for external connection,
The plating layer has a first layer and a second layer formed on the first layer;
Wherein the second layer, the maximum operating temperature higher than the solidus temperature or melting point during vehicle, formed by Pb-free alloy or Sn containing Sn,
Said first layer, said vehicle when the maximum operating temperature lower than the solidus temperature or the melting point of, formed by Pb-free alloy containing Sn, a method of manufacturing a semiconductor device.

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