JP5500554B2 - Multilayer printed wiring board - Google Patents

Description

  The present invention relates to a multilayer printed wiring board.

  In the production of a multilayer printed wiring board, an inner layer pattern shift (hereinafter also referred to as an inner layer pattern shift) may occur with respect to an interlayer connection via. This is because, when forming an interlayer connection via for interlayer connection to the land of the inner layer pattern (hereinafter referred to as the inner layer land), the interlayer connection via depends on factors such as the accuracy of the processing apparatus and the expansion and contraction of the printed wiring board. This is a so-called “inner land drop” defect that deviates from the inner land.

  Such a defect, for example, in a build-up multilayer printed wiring board, causes an electrical defect if the interlayer connection via deviates from the inner layer land. Therefore, in order to ensure the quality of the build-up multilayer printed wiring board, in the manufacturing process, it is required to accurately inspect whether the inner layer pattern deviation is within an allowable range.

  Further, even in a multilayer printed wiring board using through holes for interlayer connection, if the through holes are displaced with respect to the inner land, the connection area between the through hole and the inner land surface may be reduced, resulting in an electrical failure. . Accordingly, in the same manner as described above, it is required to accurately inspect whether or not the inner layer pattern deviation is within an allowable range in the manufacturing process in order to ensure the quality of the multilayer printed wiring board.

Patent Document 1 discloses a build-up multilayer printed wiring board that can electrically detect an inner layer pattern shift. This build-up multilayer printed wiring board is provided with an inspection pattern having a predetermined amount of clearance larger than that of the inspection micro via on the inner layer, thereby enabling electrical inspection.
That is, if the inner layer pattern deviation is smaller than the allowable value, the inspection micro via and the inspection pattern are disconnected. On the contrary, if the inner layer pattern deviation is larger than the allowable value, the inspection micro via and the inspection pattern are brought into conduction. As described above, by checking the conduction state between the inspection micro via and the inspection pattern, it is possible to perform an electrical inspection as to whether or not the inner layer pattern deviation is within an allowable range.

  Further, in Patent Document 2, when the inner layer pattern deviation is within an allowable range, it is electrically connected to the inspection micro via, and when it is out of the allowable range, the inspection is out of the inspection micro via. A printed wiring board having a pattern is described.

JP2002-1000084 JP2008-166424

The method disclosed in Patent Document 1 has a drawback of being affected by variations in processing of the inner layer pattern.
In other words, the inner layer pattern is formed by removing unnecessary portions from the uniform copper surface by etching, but this etching varies depending on the variation in the thickness of the copper surface and the width of the pattern formed due to the state of the device used. Occurs. That is, when the finish by etching of the inner layer pattern is larger than the target (wide), the inner layer land in the product is finished larger than the target, but the clearance of the inner layer inspection pattern is finished smaller than the target. In this case, according to the method of Patent Document 1, although the inner layer land drop does not occur, the inspection micro via and the inner layer inspection pattern may be electrically short-circuited, and the non-defective product is excessively detected as a defective product. It is a disadvantage that it will.

  On the other hand, when the finish by etching the inner layer pattern is smaller than the target (the width is narrow), the inner layer land in the product is finished smaller than the target, but the clearance of the inner layer inspection pattern is finished larger than the target. In this case, although the inner layer land drop has occurred, the inspection micro via and the inner layer inspection pattern may not be electrically short-circuited, and a defect may be missed. Therefore, in order to avoid this oversight, it is conceivable to reduce the design value of the clearance of the inner layer inspection pattern. However, if it is set to a small value, there is a disadvantage that the rate of occurrence of excessive detection increases.

  In Patent Document 2, the above-mentioned problem does not occur, but for example, four patterns (0 °, 90 degree, 180 degree, 270 degree direction) is a necessary technology, and in order to detect an oblique 45 degree direction, four more (45 degrees, 135 degrees, 225 degrees, 315 degrees) Direction) detectors are required, and at least eight detectors must be formed.

  Under such circumstances, the present invention can detect whether or not the inner layer pattern deviation with respect to the interlayer connection via is within an allowable range without being affected by the finished state of the inner layer pattern by etching with a small number of detection units. An object of the present invention is to provide a multilayer printed wiring board that can be inspected automatically.

According to the first aspect of the present invention, there is a circular land on the surface of the multilayer printed wiring board, a circular micro via extending from the land to the inner surface of the multilayer printed wiring board, and the deviation of the inner layer pattern of the multilayer printed wiring board. If within the allowable range, a pair of conductors that are provided on the inner layer surface of the multilayer printed wiring board and are opposed to each other through a space of the interval a shown by the relationship of the following formula (1) that is electrically connected to the micro via. It is a multilayer printed wiring board which has a pattern for a test | inspection provided with a part.

  According to a second aspect of the present invention, there is provided a multilayer printed wiring board comprising at least two or more sets of test patterns having different angles formed by the pair of conductor portions in the first invention and the X-axis direction of the multilayer printed wiring board. It is.

  In the third invention of the present invention, when the test pattern in the first or second invention has no displacement of the inner layer pattern, the center line of the space formed by the pair of conductor portions facing each other through the space, This is a multilayer printed wiring board in which a pair of opposing conductor portions are formed through a space so as to pass through the center of the micro via.

  In the present invention, in producing a multilayer printed wiring board, it is possible to electrically inspect whether the inner layer deviation is within an allowable range without being affected by the finished state of the inner layer pattern by etching. It is possible to prevent shipment of non-defective products due to excessive detection and shipment of defective products due to oversight.

FIG. 5 is a view showing an inspection pattern in an ideal state without any deviation of the inner layer pattern and an interlayer connection via portion as an example of a product portion, where (a) is a plan view of the surface layer surface, and (b) is a plane of the inner layer surface. (C) is a cross-sectional view, (d) is the angle formed by the X-axis direction (solid arrow) of the multilayer printed wiring board and the relative direction (broken line arrow) of a pair of conductors. It is a figure which shows that it is parallel at angle = 0 degree. It is a figure which shows the state when the gap | deviation of a micro via and an inner layer is more than predetermined amount, (a) is a top view of a surface layer surface, (b) is a top view of an inner layer surface, (c) is sectional drawing. The figure which shows the state which changed the test pattern used for Example 1 90 degree at a time, and connected two, (a) is "a shift | offset | difference" in a product part, (b) is "45 degree allowable amount in a product part. (C) is a diagram showing a case where “0 ° allowable deviation” is present in the product portion, and (d) is a case where “90 ° allowable deviation” is present in the product portion. The figure which shows the state which changed the pattern for an inspection used for Example 2 60 degrees at a time, and connected three, (a) has no "deviation" in a product part, (b) shows "30 degree allowable amount in a product part. (C) is a diagram showing a case where “0 ° allowable deviation” is present in the product portion, and (d) is a case where “60 ° allowable deviation” is present in the product portion. is there. 4A and 4B are diagrams showing a state in which four inspection patterns used in Example 3 are changed by 45 °, and four patterns are connected to each other. FIG. (C) is a diagram showing a case where “0 ° allowable deviation” is present in the product portion, and (d) is a case where “45 ° allowable deviation” is present in the product portion. is there.

The inspection pattern for detecting the deviation between the interlayer connection via and the inner layer pattern in the multilayer printed wiring board will be described.
FIG. 1 shows an inspection pattern in an ideal state with no inner layer pattern shift, and (a) a surface layer, (b) an inner layer surface, and (c) a cross section of an interlayer connection via portion as an example of a product portion. Show. In the micro via portion of the product portion in FIG. 1, 11 is a surface layer land of the product, 12 is an interlayer connection via of the product, and 15 is an inner layer land of the product.
FIG. 2 shows (a) a surface layer, (b) an inner layer surface, and (c) an inspection pattern in a state where the deviation of the inner layer pattern exceeds an allowable amount, and an interlayer connection via portion as an example of a product portion. A cross section is shown. In the inspection pattern in FIG. 2, a portion indicated by 6 indicates a disconnected state due to “deviation”, and in the micro via portion of the product, 16 indicates a drop in the inner layer land of the product.

The inspection pattern shown in FIGS. 1 and 2 is an inspection pattern when the angle = 0 ° for inspecting the inner layer pattern deviation in the X-axis direction of the multilayer printed wiring board, and has a pair of spaces having a predetermined interval a . It consists of a conductor portion 3, a microvia 2 for inspection, and a surface layer land 1. A wire 4 connected to a check land (not shown) on the surface layer is connected from the pair of conductor portions 3. This angle is the angle formed by the X-axis direction (solid arrow) of the multilayer printed wiring board as shown in FIG. 1D and the relative direction of the pair of conductor parts (broken arrow). Are parallel at an angle = 0 °.
Then, at least two sets of inspection patterns are formed in order to inspect the inner layer pattern deviation in the X-axis direction and the Y-axis direction. The Y-axis direction is an inspection pattern with an angle = 90 °.

Here, in the prior art, when the pattern of the inspection is formed by setting the space interval of the conductor portion 3 as a , the diameter of the micro via 2 as b, and the deviation allowance between the interlayer connection via of the product and the inner layer land as c, The space interval a of the conductor portion 3 is set so as to satisfy the relationship represented by the following formula (2) .

However, if an inner layer pattern shift occurs in an oblique 45 ° direction (or 135 ° direction), it will not be disconnected (cannot be detected as defective) unless the inner layer pattern shift exceeds c × 2 ^1/2. .
Therefore, in the present invention, in order to prevent undetection in the 45 ° direction which is the center between 0 ° and 90 °, the following equation (3) is used to set θ / 2 = 90 ° / 2 = 45 ° and Set the space interval a. Note that the angle θ represents an angle difference in a combination of inspection patterns having different angles formed by the pair of conductor portions 3 and 3 and the X axis of the multilayer printed wiring board.

In the present invention, since the conductor portion 3 is formed in a pair of forms through a space, it is possible to inspect the inner layer pattern deviation on the + side and the − side in one set, and at least two sets of angles. Since different conductor portions are formed, the space interval a is set so as to detect the inner layer pattern deviation in the central angular direction of the two sets of angles, thereby preventing the inner layer pattern deviation from being undetected.

In the present invention, at least two sets of test patterns having conductor portions with different angles of 0 ° or more and less than 180 ° are formed. In order to inspect the inner layer pattern deviation in all directions, “0” described above is used. In the case of “0 °”, “60 °”, “120 °” as well as “°” and “90 °”, non-detection in the 30 ° direction, which is the center of “0 °” and “60 °”, is prevented. The space to be set will also be set.
Thus, by setting the space in consideration of the central angular direction of the two sets of patterns, it is possible to inspect with a small number of inspection patterns.

The inspection pattern thus formed has a variation in the etching finish of the inner layer surface, and even if the allowable deviation c of the product changes, the inspection pattern “(b−a) / Since the value indicated by “2” also changes by the same distance, it is not affected by variations in the etching finish of the inner layer surface.
That is, by connecting the wiring 4 to the check land on the surface layer surface and electrically inspecting the conduction state, it is possible to determine whether or not the deviation between the interlayer connection via 12 as the product and the inner layer land portion 15 is good. Furthermore, it is possible to inspect the deviation in all directions by combining two or more sets of the above-described inspection patterns by changing the angle of the space to be formed.

As the number of inspection pattern pairs is increased and the angle of the inspection pattern is reduced, the space interval a can be narrowed to reduce over-detection, so the number of sets is set according to the distance of the allowable deviation c. It will be.
When the allowable deviation c is large, it is unlikely that the positional deviation reaches the full land, so it is possible to inspect two sets of the multilayer printed wiring board in the X-axis direction and the Y-axis direction. Is small, the probability that the misalignment reaches the full land is high. Therefore, the number of sets is set to three or more, and the space a between the conductor portions of the test pattern is narrowed to reduce the excessive detection.
For example, when the allowable displacement c is 100 μm or more, there are two sets in the X-axis direction and the Y-axis direction, and when the allowable displacement c is less than 100 μm, there are three or more sets as shown in FIGS. An inspection pattern is formed.

    Hereinafter, the present invention will be described in detail using examples.

As Example 1, an example in which two inspection patterns shown in FIG.
At this time, the state in which the deviation between the micro via and the inner layer surface pattern is maximized under the condition that the check lands are conducted on both sides is an example in the case of FIG. In this example, the micro via is shifted in a 45 ° direction obliquely with respect to the inner layer surface pattern.
That is, when it is desired to set the allowable amount of deviation of the micro via and the inner layer surface pattern in all directions within c, the space interval a of the inspection pattern and the diameter b of the micro via are selected so as to satisfy the following formula (4). To do.
Then, the conduction state of the check lands on both sides is electrically inspected, and if there is conduction, it can be said that the deviation amount of the micro via and the inner layer surface pattern in all directions is within c and within the allowable range.

Next, as Example 2, an example in which three inspection patterns shown in FIG.
At this time, the state in which the deviation between the micro via and the inner layer surface pattern is maximized under the condition that the check lands on both sides are conducted is an example in the case of FIG. In this example, the micro via is shifted in the direction of 30 ° obliquely with respect to the inner layer surface pattern.
That is, when it is desired to set the allowable amount of deviation in all directions between the micro via and the inner layer surface pattern to be within c, the space interval a of the inspection pattern and the diameter b of the micro via are expressed by the following equation (5). select. Then, the conduction state of the check lands on both sides is electrically inspected, and if there is conduction, the deviation amount of the micro via and the inner layer surface pattern in all directions is within c, which can be said to be within the allowable range.

Next, as Example 3, an example in which the inspection patterns shown in FIG.
At this time, the state where the deviation between the micro via and the inner layer surface pattern is maximized under the condition that the check lands on both sides are conducted is an example in the case of FIG. In this example, the micro via is displaced in the direction of 22.5 ° obliquely with respect to the inner layer surface pattern.
That is, when it is desired to set the allowable amount of misalignment in all directions between the micro via and the inner layer surface pattern within c, the space interval a of the inspection pattern and the diameter b of the micro via are expressed by the following equation (6). select. Then, the conduction state of the check lands on both sides is electrically inspected, and if there is conduction, the deviation amount of the micro via and the inner layer surface pattern in all directions is within c, which can be said to be within the allowable range.

  As shown in the first to third embodiments, depending on the direction of deviation between the micro via and the inner layer surface pattern, even if the deviation between the micro via and the inner layer is within the allowable amount c, it may be judged as a failure due to disconnection. However, excessive detection is reduced by increasing the number of inspection patterns to be combined and reducing the angle difference.

Table 1 summarizes the relationship between the inspection pattern combination angle difference θ of the embodiments shown in FIGS. 3, 4, and 5 and the value “(b−a) / 2”. Table 2 shows a numerical example of a typical inspection pattern including the inspection pattern used in the example.
The following values were set as the micro via and the allowable amount c of deviation in the example.
・ Micro via: b = φ250μm
・ Allowable displacement: c = 75 μm
In these examples, the value of “(b−a) / 2” when the diameter b of the micro via is 250 μm and the allowable displacement c between the micro via and the inner land is 75 μm is shown. The closer the value of “(b−a) / 2” is to the value of c = 75 μm, the smaller the excess detection.

  The application to the multilayer printed wiring board has been described above, but it is obvious that the present invention can also be applied to an interlayer connection via that connects the inner layer surface of the build-up multilayer printed wiring board with another inner layer surface. In addition, the present invention can also be applied to the inspection of misalignment between the through hole and each inner layer of the multilayer printed wiring board using the through hole.

  As a method of using the inspection pattern of the present invention, a plurality of layers are arranged at the periphery of a laminated board (so-called workpiece) at the manufacturing stage in a multilayer printed wiring board, and a tester or the like is provided in the middle process after pattern formation on the surface layer surface. It can be used for electrical inspection or placed on a discarded board portion in a sheet state that is a product form as a printed wiring board, and the quality of the sheet can be determined in the electrical inspection process.

DESCRIPTION OF SYMBOLS 1 Inspection pattern: Surface layer land 2 Inspection pattern: Micro via 3 Inspection pattern: A pair of conductor part 4 which has the space | interval space a of an inner layer surface Inspection pattern: Wiring 6 connected to the check land of surface layer 11) Product surface layer land 12 Product interlayer connection via 15 Product inner layer land 16 Product inner layer land drop a Space spacing of conductor part of inspection pattern b Diameter of micro via of inspection pattern c Tolerance of product deviation

Claims (3)

A circular land on the surface of the multilayer printed wiring board,
A circular micro via leading from the land to the inner layer surface of the multilayer printed wiring board;
When the deviation of the inner layer pattern of the multilayer printed wiring board is within an allowable range, the gap is provided on the inner layer surface of the multilayer printed wiring board and is electrically connected to the micro via and represented by the relationship of the following formula (1) A test pattern comprising a pair of conductor portions opposed via a space of a ,
A multilayer printed wiring board comprising:

  2. The inspection pattern according to claim 1, wherein an angle formed by a pair of conductor portions and the X-axis direction of the multilayer printed wiring board facing each other through the space includes at least two sets of inspection patterns different from each other. The multilayer printed wiring board as described.   When the test pattern has no inner layer pattern shift, the center line of the space formed by the pair of conductors facing each other through the space is relatively passed through the space so that it passes through the center of the micro via. The multilayer printed wiring board according to claim 1, wherein the printed circuit board is a test pattern in which a pair of conductor portions are formed.

Images