JP5516619B2 - Manufacturing method of electronic parts - Google Patents

Description

The present invention relates to a resin insulating layer and preparation how electronic components at least two chip mounted on the wiring layer and a conductor pattern.

As a substrate on which a semiconductor element is mounted, a build-up multilayer wiring board in which a build-up layer of a core substrate is stacked is used. Furthermore, in order to make the wiring board thinner, a build-up multilayer wiring board not using a core substrate has been put into practical use. The coreless build-up multilayer wiring board is peeled off after the chip is mounted in a state where it is supported by the supporting board, and then the strength is increased by molding. Patent Document 1 discloses a multichip package on which a plurality of chips are mounted.

JP 2008-288250 A

However, the coreless build-up multilayer wiring board cannot apply the test probe to the pad on the lower surface side of the build-up multilayer wiring board before the support plate is peeled off. Therefore, when mounting a plurality of chips, for example, when mounting a logic chip and a memory chip, the logic chip and the memory chip are mounted, molded with a resin material, the support plate is peeled off, and then both chips are mounted. It was necessary to conduct a functional test.
Accordingly, the memory chip is attached even when the attached logic chip does not operate normally.

The present invention has been made to solve the above-described problems, and its object is to perform a function test of the first chip after mounting the first chip and before mounting the second chip. can be to provide a manufacturing how electronic components makes it possible to improve the yield.

An electronic component comprising: a wiring layer having an interlayer resin insulation layer and a conductor pattern formed on the interlayer resin insulation layer; and a first chip and a second chip mounted on the wiring layer. Manufacturing method:
Forming an interlayer resin insulation layer on the support plate;
A first conductive pattern for testing, a first mounting pad for mounting the first chip, a second mounting pad for mounting the second chip, and the first mounting pad on the interlayer resin insulating layer Forming a second conductor pattern connecting at least a part of the first conductor pattern for testing with the second conductor pattern;
Mounting the first chip on the first mounting pad and performing a functional test of the first chip via the first conductive pattern for testing;
Mounting the second chip on the second mounting pad after the function test of the first chip;
Peeling off the support plate.

In the electronic component manufacturing method according to claim 1, the first conductive pattern for testing, the first mounting pad for mounting the first chip, and the second chip are mounted on the outermost interlayer resin insulation layer. The second mounting pad for forming the first conductive pad and the second conductive pattern for connecting at least a part of the first mounting pad and the first conductive pattern for testing are formed. Then, after mounting the first chip on the first mounting pad and performing a functional test of the first chip via the test pad, the second chip is mounted on the second mounting pad. For this reason, before the second chip is attached, the function test of the first chip can be easily performed. If the first chip does not function, the attachment of the second chip can be stopped, so that it is possible to avoid wasting the second chip. .

It is a manufacturing process figure of the electronic component which concerns on 1st Embodiment of this invention. It is a manufacturing process figure of the electronic component which concerns on 1st Embodiment. It is a manufacturing process figure of the electronic component which concerns on 1st Embodiment. It is a manufacturing process figure of the electronic component which concerns on 1st Embodiment. It is a manufacturing process figure of the electronic component which concerns on 1st Embodiment. It is sectional drawing of the electronic component which concerns on 1st Embodiment. It is sectional drawing which mounted the electronic component which concerns on 1st Embodiment on the board | substrate. It is sectional drawing of the board | substrate which concerns on 1st Embodiment. 9A is a plan view of the substrate of FIG. 3C, FIG. 9B is a plan view of the substrate of FIG. 3E, and FIG. 9C is a plan view of FIG. It is a top view of a board | substrate. FIG. 10A and FIG. 10B are plan views of the substrate according to the second embodiment. It is an example of arrangement | positioning of the pad for a test. It is an example of arrangement | positioning of the pad for a test.

[First embodiment]
The electronic component according to the first embodiment of the present invention will be described. FIG. 6 is a cross-sectional view of the electronic component of the first embodiment. The electronic component 10 includes a wiring layer 20, a logic chip 90A and a memory chip 90B mounted on the wiring layer 20. The wiring layer 20 does not have a core substrate. The electronic component 10 is mounted on a substrate 200 as shown in FIG. 8, for example (see FIG. 7).

A cross section of the substrate 200 is shown in FIG.
The substrate 200 is provided with a core substrate 230 and a through hole 233 that penetrates the core substrate 230 laminated on both surfaces of the core substrate, and a through hole conductor 236 is formed in the through hole 233. A through-hole land 236L is formed at the end of the through-hole conductor. Conductor circuits 234 on both sides of the core substrate are connected by through-hole conductors 236. On the core substrate 230, an interlayer resin insulation layer 250 including via conductors 260 and signal lines 258 is built up. On the interlayer resin insulation layer 250, an interlayer resin insulation layer 350 including a via conductor 360, a via land 360L, and a pad 358P is built up. A solder resist layer 270 having an opening 271 is formed on the interlayer resin insulating layer 350, and a via land 360 </ b> L for connecting a substrate and a pad 358 </ b> P are exposed in the opening 271. Solder bumps 272 for connecting to an external substrate are provided in the opening 271 on the lower surface side.

A cross section of the electronic component 10 is shown in FIG.
The wiring layer 20 is formed on the first surface F of the first interlayer resin insulation layer 50 and the first interlayer resin insulation layer 50 having the first surface F and the second surface S opposite to the first surface. Formed on the first interlayer resin insulation layer 50, the second interlayer resin insulation layer 150 formed on the first surface of the first interlayer resin insulation layer 50 and on the conductor pattern 58, and the second interlayer resin insulation layer 150. Via land 160L, a first mounting pad 158A for mounting the logic chip 90A, a second mounting pad 158B for mounting the memory chip 90B, and a test pad (first conductor pattern) 158T for the logic chip 90A, And a connection conductor pattern 158S for connecting the logic chip 90A and the memory chip 90B. A through hole 151 is provided in the second interlayer resin insulation layer 150, and a via conductor 160 is provided in the through hole 151.

A ZZ cross section in FIG. 6 is shown in FIG.
On the second interlayer resin insulation layer 150, as described above, the first mounting pads 158A and the via lands 160L are disposed in the logic chip mounting area 89A, and the second mounting pads 158B and 158B are disposed in the memory chip mounting area 89B. Via land (160L) is disposed, connecting conductor pattern (158S) is disposed between logic chip mounting area (89A) and memory chip mounting area (89B), test pad (158T) is disposed outside logic chip mounting area (89A), and the first A second conductor pattern 158 that connects a part of the mounting pad 158A and the test pad 158T is disposed.

The first interlayer resin insulation layer 50 is a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added to a part of the thermosetting resin, a thermoplastic resin, or a resin composite containing these resins. It is the layer which consists of. A through hole 51 is provided in the first interlayer resin insulation layer 50. An electrode 60 made of plating is formed inside the through hole 51. A solder bump 77 is disposed at the tip of the electrode 60.

A solder resist layer 70 is provided on the second interlayer resin insulation layer 150. The solder resist layer 70 is provided with an opening 71 that exposes at least a part of the pad 158P. Inside the opening 71, logic chip mounting solder bumps 76A and memory chip mounting solder bumps 76B are provided. A logic chip 90A is mounted on the wiring layer 20 via solder bumps 76A, and a memory chip 90B is mounted via solder bumps 76B. An underfill 94 is filled between the wiring layer 20 and the logic chip 90A and the memory chip 90B. The side surfaces of the logic chip 90A and the memory chip 90B are sealed with a sealing resin 96.

In the first embodiment, in the electronic component 10, the logic chip 90 </ b> A and the memory chip 90 </ b> B are provided on the wiring layer 20 with a fine pitch and high cost, and the wiring density of the substrate 200 that is far from the logic chip 90 </ b> A and the memory chip 90 </ b> B is suppressed. Thus, both performance and cost are achieved.

In the electronic component of the first embodiment, the logic chip 90A and the memory chip 90B are mounted on the wiring layer 20, and the logic chip 90A and the memory chip 90B are connected by the connection conductor pattern 158S. Can be transmitted at high speed between the memory chip 90B and the memory chip 90B.

The manufacturing method of the electronic component of 1st Embodiment is demonstrated with reference to FIGS.
(1) A glass plate 30 having a thickness of about 1.1 mm is prepared (FIG. 1A).
The glass plate has a CTE of 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the mounted silicon IC chip is small, and transmits a 308 nm laser beam used in the peeling process described later. It is desirable that the rate is 90% or more.

(2) A release layer 32 mainly made of a thermoplastic polyimide resin is provided on the glass plate 30 (FIG. 1B).

(3) On the release layer 32, a resin film for an interlayer resin insulation layer (manufactured by Ajinomoto Co., Inc .: trade name; ABF-45SH) is laminated by vacuum pressure bonding while raising the temperature, and the first interlayer resin insulation layer 50 is provided. (See FIG. 1C). The resin film for interlayer resin insulation layers includes soluble particles having a particle size of 0.1 μm or less and inorganic particles.

(4) An electrode body opening 51 that penetrates the first interlayer resin insulation layer 50 and reaches the release layer 32 is provided by a CO2 gas laser (see FIG. 1D).

(5) The surface layer of the first interlayer resin insulation layer 50 is preliminarily provided with a catalyst such as palladium, and is immersed in an electroless plating solution for 5 to 60 minutes, so that the electroless plated film 52 is within a range of 0.1 to 5 μm. Is provided (FIG. 2A).

(6) A commercially available photosensitive dry film is affixed on the electroless plating film 52, a photomask film is placed and exposed, developed with sodium carbonate, and a plating resist 54 having a thickness of about 15 μm is formed. Provided (FIG. 2B).

(7) The electroless plating film 52 is used as a power feeding layer, and the electrolytic plating film 56 is formed by electrolytic plating (FIG. 2C).

(8) The plating resist 54 is peeled and removed with a solution containing monoethanolamine. Then, the electroless plating film 52 under the peeled plating resist is dissolved and removed by etching to form the first signal line 58 and the electrode 60 composed of the electroless plating film 52 and the electrolytic plating film 56 (FIG. 2D). )).

(9) Similar to (3) above, the second interlayer resin insulation layer 150 is formed on the first interlayer resin insulation layer 50 and the first signal line 58 (FIG. 3A).

(10) In the same manner as in (4) above, a via opening 151 reaching the first signal line 58 is formed in the second interlayer resin insulation layer 150 (FIG. 3B).

(11) Similarly to the above (5) to (8), the via conductor 160 is formed in the opening 151 of the second interlayer resin insulation layer 150, and the connection conductor pattern 158S is formed on the second interlayer resin insulation layer 150. Then, the second conductor pattern 158, the first mounting pad 158A, the second mounting pad 158B, and the via land 160L are formed (FIG. 3C). FIG. 9A shows the connection conductor pattern 158S, the second conductor pattern 158, the mounting pad 158A, the mounting pad 158B, and the via land 160L on the second interlayer resin insulating layer 150. A cc cross section in FIG. 9A corresponds to FIG.

(12) A solder resist layer 70 is formed on the second interlayer resin insulation layer 150. Thereafter, an opening 71 is provided in the solder resist layer 70 to expose the first mounting pad 158A, the second mounting pad 158B, and the test pad 158T (FIG. 3D). A plan view of the substrate in FIG. 3D is shown in FIG.

(13) Next, Ni plating is performed on the exposed portions of the first mounting pad 158A and the second mounting pad 158B, and then solder plating (Sn-Ag) is performed. The wiring board 100 is manufactured by forming the second solder bump 76B on the second mounting pad 158B with the solder bump 76A (FIG. 3E). The wiring substrate 100 is formed of a glass plate 30 and a wiring layer 20 formed on the glass plate 30.

(14) Next, by reflowing at about 260 ° C., the logic chip 90A is mounted on the wiring board 100 via the solder bumps 76A (FIG. 4A). At this time, since the thermal expansion coefficients of the glass plate 30 and the logic chip 90A are approximate, the thermal stress applied to the wiring layer 20 is reduced. A plan view of the substrate of FIG. 4A is shown in FIG. When the logic chip 90A is mounted on the wiring layer 20, a test probe (not shown) is applied to the test pad 158T and the second solder bump 76B on the second pad to perform a function test of the logic chip 90A. If a malfunction of the logic chip 90A is found in this test, the wiring board 100 is discarded.

(15) The memory chip 90B is mounted on the wiring substrate 100 in which the operation of the logic chip 90A is confirmed to be normal (FIG. 4B). Also at this time, since the thermal expansion coefficients of the glass plate 30 and the logic chip 90A are approximate, the thermal stress applied to the wiring layer 20 is reduced.

(16) An underfill 94 is filled between the wiring layer 20 and the logic chip 90A and the memory chip 90B (FIG. 4C).

(17) The logic chip 90A and the memory chip 90B are sealed with the sealing resin 96 in the mold (FIG. 4D).

(18) The sealing resin 96 is polished, and the upper surfaces of the logic chip 90A and the memory chip 90B are exposed (FIG. 5A). Thereby, it becomes possible to attach a heat sink directly to a logic chip. Furthermore, the height of the entire electronic component is also suppressed.

(19) Next, the laser beam of 308 nm is transmitted through the glass plate 30 and irradiated to the release layer 32, and the release layer 32 is softened. And the glass plate 30 is slid with respect to the wiring layer 20, and the glass plate 30 peels (FIG. 5 (B)).

(20) The peeling layer 32 is removed by ashing, and the first interlayer resin insulation layer 50 and the pad 60P of the electrode 60 are exposed (FIG. 5C).

(21) Then, a solder bump 77 is formed on the pad 60P of the electrode 60, and the electronic component 10 is completed (FIG. 5D).

(21) The electronic component 10 is mounted via the solder bumps 77 on the substrate 200 described above with reference to FIG. An underfill 198 is filled between the substrate 200 and the wiring layer 20 (FIG. 7).

In the electronic component 10 of the first embodiment, first, the test pad 158T, the first mounting pad 158A for mounting the logic chip 90A, and the memory chip 90B are mounted on the outermost interlayer resin insulating layer 150. Second mounting pads 158B and second conductive patterns 158 that connect at least a part of the first mounting pads 158A and the test pads 158T are formed.
Then, after the logic chip 90A is mounted on the first mounting pad 158A and the functional test of the logic chip 90A is performed via the test pad 158T (FIG. 4A), the memory chip is mounted on the second mounting pad 158B. 90B is mounted (FIG. 4B). For this reason, the logic chip can be easily tested before the memory chip is attached, and if the logic chip does not function, the attachment of the memory chip can be stopped, so that it is possible to avoid wasting the memory chip.

In the electronic component 10 of the first embodiment, after the logic chip 90A and the memory chip 90B are molded, the support plate 30 is peeled off. That is, the logic chip 90 </ b> A and the memory chip 90 </ b> B are mounted in a state where the wiring layer 20 having a low rigidity without a core substrate is supported by the support plate. For this reason, the curvature of the wiring layer 20 is suppressed as much as possible.

In the wiring substrate 100 of the first embodiment, a test pad 158T, a first mounting pad 158A for mounting a logic chip, and a second mounting pad 158B for mounting a memory chip 90B are provided, and the first mounting pad 158A is provided. A second conductor pattern 158 connecting at least a portion with the test pad 158T is provided. After the logic chip is mounted on the first mounting pad 158A and the function test of the logic chip is performed via the test pad 158T, the memory chip 90B is mounted on the second mounting pad 158B. For this reason, the logic chip can be easily tested before the memory chip is attached, and if the logic chip does not function, the attachment of the memory chip can be stopped, so that it is possible to avoid wasting the memory chip.

In the wiring board of the first embodiment, as shown in FIG. 9A, the test pads 158T are arranged outside the first mounting pad area (logic chip mounting area) 89A. Can be easily tested by applying the probe to the test pad.

FIG. 11A shows an arrangement example of the test pads 158T. In the first embodiment described above with reference to FIG. 9A, the test pad 158T is provided at the end of the second conductor pattern 158. In this arrangement example, a test pad 158T is provided in the middle of the second conductor pattern 158. In this arrangement example, since the test pads are arranged in the middle of the wiring, the degree of freedom in arrangement is improved.

FIG. 11B shows another arrangement example of the test pads 158T. In this arrangement example, the test pads 158T are arranged in a staggered manner. For this reason, arrangement density can be raised.

12A shows a pentagonal test pad 158T, and FIG. 12B shows a hexagonal test pad 158T. In this example, since the test pads are polygonal, the arrangement density can be increased more than the circular pads.

[Second Embodiment]
The electronic component manufacturing method and wiring board according to the second embodiment will be described with reference to FIG.
In the first embodiment, the second conductor pattern 158 that connects the first mounting pad 158A and the test pad 158T is disposed on the second interlayer resin insulation layer 150. On the other hand, in the second embodiment, as shown in FIG. 10A, the conductive pattern 58 that connects the first mounting pad 158A and the test pad 158T is the first layer under the second interlayer resin insulation layer 150. It is provided on the insulating layer. The conductor pattern 58 and the test pad 158T are connected via via conductors and via lands 160L. As shown in FIG. 10B, a solder resist layer 70 is provided on the second insulating layer, and the test pads 158T, the first mounting pads 158A, and the second mounting pads 158B are exposed from the openings 71 of the solder resist layer. Is done.

DESCRIPTION OF SYMBOLS 10 Electronic component 20 Wiring layer 50 1st interlayer resin insulation layer 90A Logic chip 90B Memory chip 100 Wiring board 150 2nd interlayer resin insulation layer 158 2nd conductor pattern 158T Test pad (1st conductor pattern)
158A First mounting pad 158B Second mounting pad 200 Wiring layer 230 Core substrate

Claims (8)

A method of manufacturing an electronic component comprising a wiring layer having an interlayer resin insulation layer and a conductor pattern formed on the interlayer resin insulation layer, and a first chip and a second chip mounted on the wiring layer. :
Forming an interlayer resin insulation layer on the support plate;
A first conductive pattern for testing, a first mounting pad for mounting the first chip, a second mounting pad for mounting the second chip, and the first mounting pad on the interlayer resin insulating layer Forming a second conductor pattern connecting at least a part of the first conductor pattern for testing with the second conductor pattern;
Mounting the first chip on the first mounting pad and performing a functional test of the first chip via the first conductive pattern for testing;
Mounting the second chip on the second mounting pad after the function test of the first chip;
Peeling the support plate. A method of manufacturing an electronic component according to claim 1, wherein:
The first conductor pattern for testing is provided outside the formation area of the first mounting pad. A method of manufacturing an electronic component according to claim 1, wherein:
The width of the first conductor pattern for testing is made larger than the width of the second conductor pattern. A method of manufacturing an electronic component according to claim 1, wherein:
The first conductor pattern for testing is a pad. A method of manufacturing an electronic component according to claim 1, wherein:
After mounting the second chip, the second chip and the first chip are molded, and the support plate is peeled off. A method of manufacturing an electronic component according to claim 1, wherein:
The first chip is logic, and the second chip is memory. A method of manufacturing an electronic component according to claim 1, wherein:
The first conductor pattern for testing is formed at an end of the second conductor pattern. A method of manufacturing an electronic component according to claim 1, wherein:
The support plate is made of glass.

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