JP5525405B2 - Current detection circuit, motor drive device - Google Patents

Description

  The present invention relates to a circuit for detecting a power source current of an inverter, and an apparatus for driving a motor using the circuit.

  The electric power steering device of an automobile uses high-precision motor control technology that assists steering by detecting a steering operation by a human. In general, the electric power steering device is a motor current detection device that detects the current flowing through the motor with high accuracy in order to operate the motor effectively, and the inverter current that protects the inverter when the inverter or the motor has a ground fault or power fault. A detection device is provided. Current detectors include those using Hall elements and those using shunt resistors, but those using shunt resistors are widely used.

  The inverter current detection device generally uses a method of calculating a current value from a potential difference between both ends of a current detection resistor connected to an output line from the battery. Patent Document 1 listed below describes an example of this current detection device.

A shunt resistor used for current detection generally has a small resistance value in order to reduce loss. Therefore, since the potential difference between both ends of the shunt resistor is small, it is necessary to amplify the voltage across the shunt resistor using an operational amplifier in order to accurately detect the current. The gain of the operational amplifier is determined by the ratio of the feedback resistor and the gain setting resistor. That is,
Operational amplifier gain = feedback resistance / gain setting resistance.

JP 2007-218664 A

  The current supplied from the power source to the inverter is an alternating current having a relatively high frequency. This frequency is generally several hundred kHz or more. Therefore, in the technique described in Patent Document 1, in order to detect the maximum value of the inverter current based on the voltage across the shunt resistor, it is necessary to sample the voltage value across every several hundred ns. This is because the maximum value cannot be detected unless the detection value is sampled at the time when the current is maximum.

  When sampling is performed at a high frequency, the load on the AD converter of the microprocessor increases, and it is necessary to use a higher-performance microprocessor. As a result, the cost of the current detection circuit is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a current detection circuit that can detect an inverter current with a small number of parts and at low cost and high accuracy.

  The current detection circuit according to the present invention includes an amplification circuit that amplifies the voltage across the current detection resistor, and a peak hold circuit that holds the maximum value of the amplification circuit output and amplifies the output of the amplification circuit.

  The current detection circuit according to the present invention keeps the maximum value for a predetermined time even when the output level of the amplifier circuit is lower than the maximum value. Thereby, even if sampling is performed at a frequency lower than the frequency of the current to be detected, the maximum value of the current can be obtained.

1 is a circuit diagram of an inverter device for driving a motor according to Embodiment 1. FIG. 2 is a timing chart for explaining an operation of detecting an inverter current in the circuit shown in FIG. 3 is a vector diagram showing the operation of the motor 7. FIG. It is a figure which shows the structure of the conventional current detection circuit. It is a figure which shows the structural example which incorporated the electric current detection circuit shown in FIG. 4 in the inverter apparatus for motor drive. The general frequency characteristic of an operational amplifier is shown. 6 is a timing chart for explaining an operation of detecting an inverter current in the conventional current detection circuit shown in FIG. 5. It is the figure which showed the phenomenon in which the amplification response of the operational amplifier 120 is delayed.

<Conventional current detection circuit>
Below, in order to make an understanding of this invention easy, the structure and operation | movement of the conventional current detection circuit described in patent document 1 are demonstrated first. Thereafter, the configuration and operation according to the embodiment of the present invention will be described.

  FIG. 4 is a diagram showing a configuration of a conventional current detection circuit. Hereinafter, each component of the circuit shown in FIG. 4 will be described.

  One end of the shunt resistor 108 is connected to the non-inverting input terminal of the operational amplifier 120 via the current limiting resistor 114. The other end of the shunt resistor 108 is connected to the inverting input terminal of the operational amplifier 120 via the gain setting resistor 113.

  The output terminal of the operational amplifier 120 is connected to the inverting input terminal via the feedback resistor 119. The gain setting resistor 113 and the inverting input terminal of the operational amplifier 120 are connected to a constant voltage generation circuit 115 via a constant voltage clamp resistor 116. The current limiting resistor 114 and the operational amplifier non-inverting input terminal are connected to a constant voltage generation circuit 115 via a constant voltage clamp resistor 117. The constant voltage clamp resistors 117 and 116 and the constant voltage generation circuit 115 are connected to GND via a voltage dividing resistor 118.

The gain of the operational amplifier 120 is determined by the ratio of the feedback resistor 119 and the gain setting resistor 113. That is,
Gain = feedback resistor 119 / gain setting resistor 113
It becomes.

  FIG. 5 is a diagram showing a configuration example in which the current detection circuit shown in FIG. 4 is incorporated in an inverter device for driving a motor. The motor drive inverter device shown in FIG. 5 includes a battery 109, an AC motor 107, and switching elements 101 to 106. Outputs 110 to 112 of the switching elements correspond to the phases of the AC motor 107.

  The inverter current flowing through the shunt resistor 108 has a relatively high frequency as described above. Therefore, in order for the microprocessor to detect the maximum value of the inverter current, it is necessary to increase the sampling frequency accordingly.

  In the present invention, even when the inverter current flowing through the shunt resistor 108 is smaller than the maximum value, the maximum value is maintained between the operational amplifier 120 and the microprocessor so that the microprocessor can obtain the maximum value. A peak hold circuit that can be used is provided. Thereby, the sampling frequency can be made lower than the frequency of the inverter current.

<Embodiment 1>
FIG. 1 is a circuit diagram of an inverter device for driving a motor according to Embodiment 1 of the present invention. The motor drive inverter device shown in FIG. 1 includes an inverter main circuit 29, an amplifier circuit 30, and a peak hold circuit 31. The inverter main circuit 29 generates a three-phase alternating current for driving the motor. The amplifier circuit 30 detects the inverter current flowing through the inverter main circuit 29 as a voltage across the shunt resistor 8 and amplifies the voltage. The peak hold circuit 31 holds the maximum voltage amplified by the amplifier circuit 30.

  The inverter main circuit 29 includes a battery 9, an AC motor 7, switching elements 1 to 6, and a shunt resistor 8 that detects an inverter current flowing through the inverter main circuit 29 as a voltage across the resistor.

  The shunt resistor 8 is provided between the anode side of the battery 9 and the reference voltage 10. The resistance value of the shunt resistor 8 is set to a relatively small value in order to suppress voltage loss. Further, since a large current flows through the shunt resistor 8, the shunt resistor 8 has a large capacity.

  For example, in the case of an inverter device for driving a motor used in an electric power steering device, the inverter current is 100 A or more. In this case, the resistance value of the shunt resistor 8 is about several mΩ. Therefore, the capacity of the shunt resistor 8 requires about several watts. Furthermore, since the minute potential difference generated in the shunt resistor 8 is amplified by the amplifier circuit 30 at the subsequent stage, it is necessary to use a resistor having a relatively small error in resistance value.

  A current limiting resistor 15 is provided between the non-inverting input terminal (+) of the operational amplifier 21 and one end of the shunt resistor 8. A constant voltage power source 18 is connected between the non-inverting input terminal (+) of the operational amplifier 21 and the current limiting resistor 15 via a constant voltage clamping resistor 16. The constant voltage power supply 18 is connected to GND through a voltage dividing resistor 19. The non-inverting input terminal (+) is connected to GND via the current limiting resistor 20.

  A gain setting resistor 14 is provided between the inverting input terminal (−) of the operational amplifier 21 and the other end of the shunt resistor 8. A constant voltage power source 18 is connected between the inverting input terminal (−) of the operational amplifier 21 and the gain setting resistor 14 via a clamping resistor 17.

A feedback resistor 22 is connected between the output terminal of the operational amplifier 21 and the inverting input terminal (−). The amplification factor of the operational amplifier 21 is determined by the ratio of the feedback resistor 22 and the gain setting resistor 14. That is, if the voltage generated in the shunt resistor 8 is V _shunt , the output of the operational amplifier 21 (or the amplifier circuit 30) is V _o1 , the resistance value of the feedback resistor 22 is R ₂₂ , and the resistance value of the gain setting resistor 14 is R _14. ,
V _o1 = V _shunt × (R ₂₂ / R ₁₄ )
It becomes. That is, by measuring the potential difference between both ends of the shunt resistor 8, the current (inverter current) flowing through the motor 7 can be detected.

  Since the resistance value of the shunt resistor 8 is small and the potential difference between both ends is small, the gain of the operational amplifier 21 must be set correspondingly large. For example, if the current detected using the shunt resistor 8 is about 0 to 70 A and the resistance value of the shunt resistor 8 is 0.5 mΩ, the potential difference between both ends of the shunt resistor 8 is only 35 mV at the maximum. On the other hand, the input voltage of the microprocessor that takes in the voltage amplified by the operational amplifier 21 is several V (generally 5 V). Therefore, in order to amplify 35 mV to several volts, setting the gain of the operational amplifier 21 to 10 times or more can be said to be efficient from the viewpoint of the resolution of the microprocessor.

In the first embodiment, the gain of the operational amplifier 21 is set to 12 times. Therefore,
R ₂₂ (= feedback resistor 22) / R ₁₄ (= gain setting resistor 14) = 12
Should be set to be.

Next, the peak hold circuit 31 will be described. The peak hold circuit 31 holds the maximum value of the signal V _o1 amplified by the amplifier circuit 30 (or the operational amplifier 21). The signal V _o1 is input to the non-inverting input terminal (+) of the comparator 25 provided in the peak hold circuit 31. The output of the comparator 25 is connected to the anode of the diode 26. A gain setting resistor 24 is connected between the cathode of the diode 26 and the inverting input terminal (−) of the comparator 25. The inverting input terminal (−) is connected to GND via the current limiting resistor 23. The output port to the microprocessor and the cathode of the diode 26 are connected to GND via a discharge resistor 28. The output port to the microprocessor and the cathode of the diode 26 are connected to GND via a capacitor 27.

The amplification factor of the peak hold circuit 31 is determined by the ratio between the gain setting resistor 24 and the current limiting resistor 23. That is, if the output signal of the peak hold circuit 31 is V _o2 , the resistance value of the gain setting resistor 24 is R ₂₄ , and the resistance value of the current limiting resistor 23 is R ₂₃ ,
V _o2 = V _o1 × (1 + R ₂₄ / R ₂₃ )
It becomes.

In the first embodiment, the gain of the peak hold circuit 31 is set to double (about 6 dB). Therefore,
R ₂₄ / R ₂₃ = 1
Should be set to be. The reason why the comparator 25 has an amplifying function is to prevent the amplification response of the operational amplifier 21 from being delayed by increasing the amplification factor of the operational amplifier 21.

The peak hold circuit 31 holds the signal _Vo2 amplified by the comparator 25 in the following procedure.

The capacitor 27 receives the amplified signal V _o2 and charges it. When the voltage of V _o1 falls _below the voltage value of V _o2 , that is, when the supply current from the battery 9 is lost, or when the value of the current flowing through the shunt resistor 8 is lowered, the diode 26 is cut off. The capacitor 27 discharges the electric charge charged with the voltage V _o2 through the discharge resistor 28, the gain setting resistor 24, and the current limiting resistor 23. When the capacitance of the capacitor 27 is C ₂₇ , the resistance value of the discharging resistor 28 is R ₂₈ , the resistance value of the gain setting resistor 24 is R ₂₄ , and the resistance value of the current limiting resistor 23 is R ₂₃ , the discharge time constant τ is ,
τ = 1 / (C ₂₇ × (R ₂₈ / (R ₂₄ + R ₂₃ ))
It becomes. By setting the discharge time constant τ, the maximum voltage of the peak hold voltage V _o2 can be held for a certain period of time. As a result, the microprocessor does not necessarily have to perform sampling at a frequency equivalent to the inverter current, so the burden on the microprocessor can be reduced by lowering the sampling frequency. In the first embodiment, the time constant τ is set to several ms in view of the switching frequency described below.

  The configuration of the motor drive inverter device according to the first embodiment has been described above. The “current detection circuit” in the present invention corresponds to the shunt resistor 8, the amplifier circuit 30, and the peak hold circuit 31.

  FIG. 2 is a timing chart for explaining the operation of detecting the inverter current in the circuit shown in FIG. Hereinafter, each signal shown in FIG. 2 will be described.

In order to rotate the motor 7, it is necessary to pass a three-phase alternating current through the inverter output terminals 11-13. The three-phase alternating current can be generated by turning on / off the switches 1-6. There are 2 ⁸ switching patterns of switches 1 to 6 as shown below.
(1) Switch 1: ON / Switch 4, 6 At least one: ON
(2) Switch 3: ON / Switch 2, 6 At least one: ON
(3) Switch 5: ON / Switch 2, 4 At least one: ON
(4) Switches 1, 3, 5 are all ON / or switches 2, 4, 6 are all ON

  In FIG. 2, as an example, a state in which the switch 1 is turned on and the switch 6 is turned on and a current flows through the motor 7 is shown. The ON time width of each switch is different because the inverter output voltage is controlled by the ON time width. This is generally called PWM (Pulse Width Modulation) control.

  2 shows a section 43 in which the switch 1 is turned on, a section 42 in which the switch 2 is turned on, a section 45 in which the switch 5 is turned on, and a section 44 in which the switch 6 is turned on. As described above, in principle, at least one of the two switches corresponding to each phase of the motor 7 must be turned on. However, since switches corresponding to the same phase may be simultaneously turned ON and short-circuited depending on variations in elements, a time zone 40 in which both switches of each phase are OFF is provided. This is called a short circuit prevention time or dead time. This time is generally about 1 to 3 μs.

  In FIG. 2, there is a section 41 where both ends of the section 43 and the section 44 overlap. In this section 41, a current path flows through the anode side of the battery 9, the shunt resistor 8, the switch 1, the armature winding of the motor 7, the switch 6, and the cathode side of the battery 9, and the rotational force of the motor 7 is reduced. Occur.

  FIG. 3 is a vector diagram showing the operation of the motor 7. Here, the motor 7 is a non-salient permanent magnet synchronous motor. Reference numerals 64 to 66 are electric coil windings in the motor 7, 67 is a permanent magnet in the motor, 69 is a magnetic flux generated by rotating the permanent magnet, and 74 is a speed generated in the electric coil winding by rotating the magnetic flux. The electromotive force vector, 62 is the inverter output vector, 68 is the phase angle to the field magnetic flux 69 with reference to the inverter output vector 62, 71 is the load angle between the inverter output vector and the speed electromotive force 74, and 73 is the electric current. The d-axis current converted to the rotation axis coordinate system, 72 is the q-axis current when the electron current is converted to the rotation coordinate system.

The torque T generated in the motor is assumed to flow no current through the d-axis.
T = p (number of motor pole pairs) × Iq × Φm
Thus, it can be seen that it is proportional to the current flowing through the electric coil.

  The amount of current flowing through the armature winding is proportional to the section 41 (time during which the PWM signal is ON) in FIG. Therefore, when the small torque is required, the section 41 is narrowed. When the large torque is required, the section 41 is widened, and the current to be supplied needs to be adjusted.

From the above, since the section 41 is narrow in the small torque region, the frequency of the potential difference V _shunt 46 generated in the shunt resistor becomes high. In the large torque region, since the section 41 is wide, the frequency of the potential difference V _shunt 46 generated in the shunt resistor is low. In order to cope with the duty change of V _shunt 46, a wide band operational amplifier 21 is required.

As described above, the potential difference V _shunt 46 when the inverter current flows through the shunt resistor 8 is a small signal of several tens of mV. The signal 47 is a voltage amplified by the operational amplifier 21 (12 times in the first embodiment).

  In the present invention, since gain is given to the peak hold circuit 31 in the subsequent stage, the signal 48 is a signal obtained by further amplifying the signal 47 (doubled in the first embodiment). The signal 48 is charged in the capacitor 27 via the diode 26. When the supply current from the battery 9 disappears or the inverter current value decreases, the diode 26 is cut off. At this time, the electric charge charged in the capacitor 27 is discharged. A section 50 in FIG. 2 represents the discharge time.

  In recent years, in order to reduce distortion harmonics generated from the inverter, the switching frequency is as high as several tens of kHz. Therefore, in the first embodiment, the time constant τ of the discharge time 50 is set sufficiently larger than the PWM cycle. Thereby, the peak hold circuit 31 can hold the maximum value of the potential difference for energizing the shunt resistor 8 for a time longer than the PWM cycle.

The comparator output V _o2 51 in FIG. 2 represents the charging / discharging process of the capacitor 27. As the capacitor 27 discharges, the voltage across the capacitor 27 gradually decreases from the maximum value. However, if the discharge time constant τ is sufficiently increased, the signal level corresponding to the maximum value of the inverter current is substantially equal. A signal level can be provided.

  Since the peak hold circuit 31 holds the maximum value of the inverter current for the above time, the microprocessor does not necessarily perform sampling at the same frequency as the inverter current, while the peak hold circuit 31 holds the maximum value. If the sampling is performed, the maximum value of the inverter current can be obtained. That is, it is possible to reduce the load related to the sampling process of the microprocessor.

<Embodiment 1: Summary>
As described above, the peak hold circuit 31 included in the current detection circuit according to the first embodiment includes the inverter in the period in which the output of the amplifier circuit 30 is smaller than the maximum value due to the inverter current being smaller than the maximum value. A voltage value corresponding to the maximum value of the current is held for a predetermined time. Thereby, since the microprocessor can perform sampling at a period lower than the frequency of the inverter current, it is possible to suppress a processing load such as AD conversion.

<Embodiment 2>
In the first embodiment, the configuration example in which the peak hold circuit 31 holds the detection signal corresponding to the maximum current flowing through the shunt resistor 8 for a predetermined time to reduce the sampling load of the microprocessor has been described. In Embodiment 2 of the present invention, a trade-off between the amplification factor of the operational amplifier 21 and the amplification factor of the comparator 25 will be described. Each circuit configuration is the same as that of the first embodiment.

  FIG. 6 shows a general frequency characteristic of the operational amplifier. An operational amplifier has a frequency range in which an input signal can be output with a set gain, which is called a gain bandwidth. When an input signal having a frequency larger than this frequency range is input, the gain generally decreases at −20 dB / dec.

  In the operational amplifier characteristics shown in FIG. 6, the open-time gain bandwidth 162 is about 20 kHz. When the frequency of the operational amplifier input signal is 20 kHz or higher, this band limitation is imposed, and the signal is output in a state where it is not amplified to the target level.

  That is, if the gain of the operational amplifier is increased too much, the amplification response becomes slow, the time required for amplification to the target level becomes long, and if the frequency of the input signal becomes high, it becomes impossible to follow. As described above, since the inverter current flowing through the shunt resistor 108 has a relatively high frequency, the gain of the operational amplifier 120 cannot be increased too much.

  Therefore, in practice, the bandwidth of the operational amplifier is increased by lowering the gain by feedback. In the case of the characteristic shown in FIG. 6, the bandwidth can be expanded to about 200 kHz by setting the feedback gain to about 25 dB.

  On the other hand, since the input voltage of the input terminal of the microprocessor is about several volts, in order to obtain the inverter current based on the detection signal, the voltage across the shunt resistor 108 is amplified to about several volts from the viewpoint of the resolution of the microprocessor. It is desirable to do. Since the actual voltage across the shunt resistor 108 is, for example, about several tens of mV, the amplification factor of the operational amplifier needs to be increased accordingly.

  However, the amplification factor of the operational amplifier is restricted due to the band limitation of the operational amplifier. On the other hand, in recent inverters, the PWM frequency is as high as several tens of kHz as described above, and the frequency of the inverter current is also as high as several MHz. Therefore, if the gain of the operational amplifier is too high, the operational amplifier cannot follow a high frequency, and the linearity of the response deteriorates.

  Furthermore, as described above, in the small torque region, the PWM ON cycle is short and the inverter current is high frequency, and in the large torque region, the PWM ON cycle is long and the inverter current is low frequency. Therefore, in the large torque region, the operational amplifier can amplify the signal with an amplification response sufficient to detect the inverter current, but in the small torque region, it exhibits an amplification response sufficient to detect the inverter current. Therefore, the amplification value originally assumed cannot be obtained. As a result, the detection error of the inverter current becomes large.

FIG. 7 is a timing chart for explaining the operation of detecting the inverter current in the conventional current detection circuit shown in FIG. Hereinafter, each signal shown in FIG. 7 will be described. Note that the sections 141 to 145 correspond to the sections 41 to 45 in FIG. A potential difference between both ends of the shunt resistor 108 is V _shunt 146, an amplification target level of the operational amplifier 120 is 148, and an actual output V _o1 of the operational amplifier 120 is 147.

In FIG. 7, it can be seen that the output V _o1 of the operational amplifier 120 does not rise vertically like the comparator output 48 of FIG. 2 but responds with a slight delay. For this reason, the output of the operational amplifier 120 does not reach the target level 148 within the interval in which the shunt resistor 108 is energized. This is because the gain of the operational amplifier 120 is increased too much and the amplification response is delayed.

  FIG. 8 is a graph showing a phenomenon in which the amplification response of the operational amplifier 120 is delayed. The error 171 is a difference between the theoretical value 170 and the operational amplifier output 172. The error 171 is large in the minute current region, and the error 172 is reduced in the large current region. This is because the PWM pulse width becomes wider in the large current region, and the frequency of the inverter current decreases.

  In order to solve the above problems, it is necessary to lower the gain of the operational amplifier 120 to increase the amplification response. However, if the gain of the operational amplifier 120 is simply lowered, the obtained signal level is lowered, so that the resolution when the microprocessor detects the inverter current is lowered accordingly.

For example, assume that the resolution of the microprocessor is 1.25 mV / LSB, the current of the battery 109 is 100 A, and the resistance value of the shunt resistor 108 is 0.5 mΩ. In this case, the potential difference Vin across the shunt resistor 108 is
Vin = 100 (A) × 0.5 (mΩ) = 50 (mV)
It becomes. When the gain of the operational amplifier 120 is 24 times, the maximum voltage value Vmax input to the microprocessor is
Vmax = 50 (mV) × 24 (times) = 1.2 (V) = 960 LSB
It becomes. The resolution of the microprocessor in this case is
100 (A) / 960 (LSB) = 104 (mA / LSB)
It becomes.

On the other hand, if the gain of the operational amplifier 120 is 12 times,
Vmax = 50 (mV) × 12 (times) = 600 (mV) = 480 (LSB)
It becomes. The resolution of the microprocessor in this case is
100 (A) / 480 (LSB) = 208 (mA / LSB)
It becomes. For this reason, in order to obtain the same resolution as when the gain is 24 times, the resolution of the AD converter needs to be twice that of the gain when the gain is 24 times.

  On the other hand, in the current detection circuit according to the present invention, since the peak hold circuit 31 has an amplification function, the amplification function can be shared by the amplification circuit 30 and the peak hold circuit 31 and the gain of the amplification circuit 30 can be lowered. . Therefore, the amplification response performance of the amplifier circuit 30 can be ensured, and this can be accurately detected even in a section where the frequency of the inverter current is high.

<Embodiment 2: Summary>
As described above, in the current detection circuit according to the present invention, the amplification circuit 30 has a characteristic that the amplification response is delayed when the amplification factor is increased. The amplification factor can detect the inverter current. The value is set so that a sufficient amplification response can be exhibited. Specifically, the amplification factor is set such that a specified amplification level can be output at a cycle faster than the maximum frequency of the inverter current. Thereby, even if the frequency of an inverter current becomes high, this can be detected reliably.

  In the current detection circuit according to the present invention, it is desirable that the amplification factor of the peak hold circuit 31 is set lower than the amplification factor of the amplification circuit 30. This is because the peak hold circuit 31 includes the capacitor 27. This is because the capacitor 27 generally has a delay characteristic, so if the amplification factor of the peak hold circuit 31 is increased, the delay amount is also amplified simultaneously. That is, the amplification factor of the amplifier circuit 30 and the amplification factor of the peak hold circuit 31 are in a trade-off relationship. It is necessary to determine what value to set each amplification factor based on the specific specification of the inverter device for driving the motor.

  1-6: Switching element, 7: AC motor, 8: Shunt resistor, 9: Battery, 10: Reference voltage, 14: Gain setting resistor, 15: Current limiting resistor, 16: Constant voltage clamping resistor, 17: Clamping resistor, 18: constant voltage power supply, 19: voltage dividing resistor, 20: current limiting resistor, 21: operational amplifier, 22: feedback resistor, 23: current limiting resistor, 24: gain setting resistor, 25: comparator, 26: Diode, 27: Capacitor, 28: Discharge resistor, 29: Inverter main circuit, 30: Amplifier circuit, 31: Peak hold circuit, 62: Inverter output vector, 64-66: Electron winding, 67: Permanent magnet 69: magnetic flux, 68: phase angle, 69: field magnetic flux, 71: load angle, 72: q-axis current, 73: d-axis current, 74: velocity electromotive force vector, 101-106: switch Ching element, 107: AC motor, 108: shunt resistor, 109: battery, 113: gain setting resistor, 114: current limiting resistor, 115: constant voltage generation circuit, 116: constant voltage clamp resistor, 117: constant voltage clamp Resistor, 118: voltage dividing resistor, 119: feedback resistor, 120: operational amplifier.

Claims (4)

A current detection circuit for detecting a current flowing through an inverter having a switching element,
A current detection resistor disposed between an anode side of a power source that supplies current to the inverter and the switching element;
An amplifier circuit for amplifying the voltage across the current detection resistor;
A peak hold circuit that holds the maximum value of the signal output from the amplifier circuit and amplifies the signal output from the amplifier circuit;
With
The peak hold circuit is:
A detection signal indicating a current value supplied to the inverter by the power source is output to the outside of the current detection circuit;
During a period when the signal level of the signal output from the amplifier circuit is lower than the maximum value, the detection signal is held outside the current detection circuit while maintaining the signal level indicating the maximum value for a predetermined time. Output,
The amplifier circuit is
The amplification response is delayed as the amplification factor is increased.
An amplification factor is set so as to have an amplification response performance capable of detecting a maximum current value when the frequency of a current supplied from the power supply is the highest. The peak hold circuit is:
An amplifier for amplifying a signal output from the amplifier circuit;
A feedback resistor connecting the output of the amplifier to the input of the amplifier;
A diode disposed between the output of the amplifier and the feedback resistor;
A capacitor connected to the output terminal of the diode;
With
The diode is
When the output from the amplifier falls below a predetermined level, it becomes a non-energized state,
The capacitor is
When the diode is energized, charge the charge,
The current detection circuit according to claim 1, wherein when the diode is in a non-energized state, the current is discharged and the detection signal having the maximum value is output to the outside of the current detection circuit. The current detection circuit according to claim 1, wherein an amplification factor of the peak hold circuit is set lower than an amplification factor of the amplification circuit. A current detection circuit according to any one of claims 1 to 3,
The inverter;
With
A motor driving apparatus that drives the motor by supplying an alternating current from the inverter to the motor.

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