JP5533573B2 - Semiconductor element - Google Patents

Description

  The present invention relates to a semiconductor element, and more particularly to an electrode structure of a semiconductor element.

  Conventionally, as an electrode structure of a semiconductor element, a two-layer structure of an ohmic contact layer made of Al, W, Cr, Ti or the like that makes good ohmic contact with a semiconductor layer and a bonding layer such as Au that has good adhesion to the wire, Alternatively, it is known to have a three-layer structure in which a barrier layer such as Pt is further provided between the two layers (see, for example, Patent Documents 1 and 2).

Japanese Patent No. 4099989 US Pat. No. 7,335,519

  However, it has been conventionally required to reduce the forward voltage (Vf) as a semiconductor element, and there is room for improvement particularly in the current diffusibility of the electrode itself.

  Accordingly, the present invention has been made in view of such circumstances, and it is an object of the present invention to provide a semiconductor element in which the forward voltage (Vf) is reduced by reducing the sheet resistance of the electrode and improving the current diffusibility. To do.

  According to the present invention, the above problem is solved by the following means.

The semiconductor light emitting device according to the present invention includes a semiconductor layer in which an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer are stacked in order from the upper surface side that is a light extraction surface, and the n-type nitride semiconductor layer. An n-side pad electrode provided on the upper surface of the semiconductor light-emitting element, wherein the n-side pad electrode is an Au layer on the outermost surface , a Ru layer, a Cu layer from the Au layer to the semiconductor layer side , The Ru layer has a structure in which the layers are sequentially stacked, and the thickness of the Cu layer is greater than or equal to the thickness of the Au layer .
As a result, the sheet resistance of the n-side pad electrode is reduced, and a semiconductor light emitting device with reduced forward voltage (Vf) can be obtained.
Note that the outermost surface according to the present invention refers to a surface to which an external connection member such as a wire, bump, or solder is connected in order to be electrically connected to the outside.

Further, the n-side pad electrode is formed by sequentially stacking a Pt layer and a Ti layer from the Ru layer to the semiconductor layer side, and the Ti layer is connected to an upper surface of the n-type nitride semiconductor layer. It is preferable.

Moreover, it is preferable to have a conductive substrate electrically connected to the p-type nitride semiconductor layer on the lower surface side of the p-type nitride semiconductor layer .

  According to the semiconductor element of the present invention, the forward voltage (Vf) can be reduced.

1 is a plan view schematically showing a semiconductor element according to a first embodiment. It is sectional drawing which shows typically the semiconductor element which concerns on 1st Embodiment shown in FIG. FIG. 3 is an enlarged cross-sectional view schematically showing a laminated structure of electrodes in the semiconductor element shown in FIGS. 1 and 2. It is a top view which shows typically the semiconductor element which concerns on 2nd Embodiment. FIG. 5 is a cross-sectional view taken along the line A-A ′ of FIG. 4 schematically showing a semiconductor element according to the second embodiment.

  Hereinafter, embodiments for implementing a semiconductor device according to the present invention will be described with reference to the drawings. Note that the size, positional relationship, and the like of the members shown in each drawing may be exaggerated for clarity of explanation. Furthermore, in the following description, the same names and symbols indicate the same or the same members in principle, and detailed description will be omitted as appropriate.

<First Embodiment>
FIG. 1 is a plan view schematically showing the semiconductor element according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing the semiconductor element according to the first embodiment shown in FIG. FIG. 3 is an enlarged cross-sectional view schematically showing a laminated structure of electrodes in the semiconductor element shown in FIGS.

  As shown in FIGS. 1, 2, and 3, the semiconductor element 10 according to the first embodiment includes semiconductor layers 2, 3, and 4 and an electrode 7 provided on the semiconductor layer. The electrode 7 is configured by laminating a first metal layer 75 on the outermost surface and at least a second metal layer 73 on the semiconductor layer side of the first metal layer 75.

  The semiconductor element 10 according to the first embodiment is a light emitting element, and includes an n-type nitride semiconductor layer 2, an active layer 3, and a p-type nitride semiconductor layer 4 stacked on a substrate 1. The semiconductor element 10 further includes an n-side electrode 7n electrically connected to the n-type nitride semiconductor layer 3 and a p-side electrode 5 electrically connected to the p-type nitride semiconductor layer 4 on the upper surface side. Further, an insulating protective layer 9 is provided on the surface. The n-side electrode 7n is a pad electrode (n-side pad electrode), and is formed directly on the surface of the n-type nitride semiconductor layer 2 exposed by removing a part of the p-type nitride semiconductor layer 4 and the active layer 3. The On the other hand, the p-side electrode 5 includes a translucent electrode 6 formed on almost the entire surface of the p-type nitride semiconductor layer 4 and a pad electrode (in a partial region on the translucent electrode 6). p-side pad electrode) 7p. The protective layer 9 covers the entire surface of the semiconductor element 10 except for the upper surfaces of the n-side electrode 7n and the p-side pad electrode 7p. Note that “upper” in this specification refers to the side provided with the semiconductor layers 2, 3, and 4 with respect to the substrate 1, and is the upward direction in FIG. 2.

(substrate)
The substrate 1 may be any substrate material capable of epitaxially growing a nitride semiconductor, and the size and thickness are not particularly limited. As such a substrate material, an insulating substrate such as sapphire or spinel (MgA1 ₂ O ₄ ) whose main surface is any one of C-plane, R-plane, and A-plane, silicon carbide (SiC), ZnS, ZnO , Si, GaAs, diamond, and oxide substrates such as lithium niobate and neodymium gallate that are lattice-bonded to nitride semiconductors.

(N-type nitride semiconductor layer, active layer, p-type nitride semiconductor layer)
n-type nitride semiconductor layer 2, the active layer 3, and a p-type nitride semiconductor layer 4 (appropriately referred to as collectively nitride semiconductor layer 2, 3, 4) is not particularly limited, for example, In _X A gallium nitride based compound semiconductor such as Al _Y Ga _1-XY N (0 ≦ X, 0 ≦ Y, X + Y <1) is preferably used.

(N-side electrode, p-side electrode)
The n-side electrode 7n is electrically connected to the n-type nitride semiconductor layer 2, and the p-side electrode 5 is electrically connected to the p-type nitride semiconductor layer 4 to supply current from the outside.
Here, a suitable gallium nitride compound semiconductor among nitride semiconductors is unlikely to be p-type, that is, the p-type nitride semiconductor layer 4 tends to have a relatively high resistance. Therefore, when the electrodes are connected only in a part of the region on the p-type nitride semiconductor layer 4, the current supplied to the semiconductor element 10 hardly spreads in the p-type nitride semiconductor layer 4, and light emission is not uniform in the plane. become. Therefore, the p-side electrode 5 needs to be connected on a larger area on the p-type nitride semiconductor layer 4 so that the current flows uniformly throughout the surface of the p-type nitride semiconductor layer 4. However, since the upper surface is the light extraction surface of the semiconductor element 10, the p-side electrode 5 is directly formed on the entire surface of the p-type nitride semiconductor layer 4 so as not to reduce the light extraction efficiency. A translucent electrode 6 is provided in a region (substantially the entire surface) having an area close to that. Further, the p-side electrode 5 is further provided on the translucent electrode 6 so as to be connected to an external circuit by wire bonding or the like. p-side pad electrode) 7p. The p-side pad electrode 7p has a planar view shape and area necessary for bonding so as not to block much light, and is smaller than the planar view shape of the translucent electrode 6, so that it is contained, that is, translucent. It is formed in a partial region on the electrode 6.

  On the other hand, in the low resistance n-type nitride semiconductor layer 2, the n-side electrode 7 n may have a smaller connection area, and therefore can be configured only with a pad electrode (n-side pad electrode) that does not transmit light. , Formed directly on n-type nitride semiconductor layer 2. Moreover, since the semiconductor element 10 according to the present embodiment includes the n-side pad electrode 7n on the upper surface side, the active layer 3 in the region for connecting the n-side pad electrode 7n on the n-type nitride semiconductor layer 2 and The p-type nitride semiconductor layer 4 is removed. Therefore, the n-side electrode (n-side pad electrode) 7n is necessary for bonding in the same manner as the p-side pad electrode 7p so as not to greatly reduce the amount of light emission, and is electrically connected to the n-type nitride semiconductor layer 2. It is formed in a planar view shape and area required for the above. The respective positions of the n-side pad electrode 7n and the p-side pad electrode 7p in plan view of the semiconductor element 10 are not particularly limited. What is necessary is just to design based on workability | operativity etc.

(Translucent electrode)
The translucent electrode 6 in the p-side electrode 5 is made of a conductive oxide. Although a metal thin film can also be used as the translucent electrode 6, since the conductive oxide is superior in translucency compared to the metal thin film, the semiconductor element 10 can be a light emitting element with high light emission efficiency. Examples of the conductive oxide include oxides containing at least one selected from the group consisting of Zn, In, Sn, and Mg, specifically ZnO, In ₂ O ₃ , SnO ₂ , and ITO. In particular, ITO can be suitably used because it has a high light transmittance in visible light (visible region) and is a material having a relatively high electrical conductivity.
The film thickness of the translucent electrode 6 is not particularly limited, but is preferably 5000 nm or less and more preferably about 100 to 1000 nm so that the sheet resistance does not become excessive. The shape of the translucent electrode 6 may be a shape that matches the planar view shape of the p-type nitride semiconductor layer 4 such as an integral rectangle. For example, a lattice shape, a mesh shape, a dot shape, a stripe shape, a mesh shape, etc. The light extraction efficiency may be improved by forming a pattern.

(Pad electrode)
In the semiconductor element 10 according to this embodiment, the n-side pad electrode 7n and the p-side pad electrode 7p have the same stacked structure, and are collectively referred to as a pad electrode 7 as appropriate. The pad electrode 7 includes a first metal layer 75 for connecting external connection members such as wires, bumps, and solder from the outside on the uppermost layer (outermost surface), and further on the semiconductor layer side of the first metal layer 75. In this configuration, at least the second metal layer 73 containing a metal material such as Cu is provided. As an example of this embodiment, here, an ohmic contact layer (Ti / Pt layer) 71 in which a Ti layer 71a and a Pt layer 71b are sequentially stacked on the upper surfaces of the translucent electrode 6 and the n-type nitride semiconductor layer 2, respectively. Further, a first barrier layer (Ru layer) 72, a second metal layer (Cu layer) 73, a third metal layer (Ru layer) 74, and a first metal layer (Au layer) 75 are stacked thereon in this order. Have a structure.
These layers 71, 72, 73, 74, and 75 can be formed by a known method such as a vapor deposition method or a sputtering method, and are preferably formed and laminated continuously. Moreover, the planar view shape of the pad electrode 7 is not particularly limited, and the pad electrode 7 can be formed into a desired shape by a lift-off method, etching using photolithography, or the like.

  The ohmic contact layer 71 is composed of two layers of Ti layer 71a and Pt layer 71b (referred to as Ti / Pt layer as appropriate). The Ti layer 71a is a layer in contact with the n-type nitride semiconductor layer 2 in the n-side pad electrode 7n and the translucent electrode 6 in the p-side pad electrode 7p. By providing the Ti layer 71a, the adhesion between the n-side pad electrode 7n and the n-type nitride semiconductor layer 2, and the p-side pad electrode 7p and the translucent electrode 6 is improved.

  The Pt layer 71b is a layer for improving light extraction efficiency from the semiconductor element 10 by reflecting light incident on the pad electrode 7 (particularly, light transmitted through the Ti layer 71a). Furthermore, the Pt layer 71b can be diffused into the first Ti layer 71a by annealing so that the ohmic contact between the pad electrode 7 and the translucent electrode 6 can be facilitated.

  The first barrier layer 72 is laminated between the Pt layer 71b and the second metal layer (Cu layer) 73, and is a layer for suppressing Cu from diffusing from the second metal layer 73 into the Pt layer 71b. is there. The first barrier layer 72 preferably includes at least one metal material selected from Ru, Rh, Ta, Ir, and W, and more preferably Ru. Thereby, the light extraction efficiency from the semiconductor element 10 can be improved by efficiently reflecting the light transmitted through the Pt layer 71b.

  Since the second metal layer 73 includes a metal material having a higher electrical conductivity than the metal material included in the first metal layer 75 on the outermost surface described later, the second metal layer 73 is connected to an external connection member (not shown). Current can be efficiently diffused from the first metal layer 75 through the second metal layer 73. That is, by reducing the sheet resistance of the pad electrode 7, the semiconductor element 10 with a reduced forward voltage (Vf) can be obtained. Further, at this time, it is preferable that the sheet resistance of the bad electrode 7 can be further reduced by setting the thickness of the second metal layer 73 to be equal to or greater than the thickness of the first metal layer 75. Here, Table 1 shows electrical conductivity at 20 ° C. of typical metal elements.

  As shown in Table 1, when an Au layer having excellent bonding properties is used as the first metal layer 75, Ag, Cu, or the like is preferably used as the metal material of the second metal layer 73. It is preferable to use Cu in which migration is difficult to occur and the material cost is relatively low.

  The third metal layer 74 is a layer for suppressing the metal material of the second metal layer 73 from diffusing into the first metal layer 75 and suppressing the forward voltage (Vf) from increasing. Ru, Rh , Ta, Ir, and W are preferably included. In particular, when the metal material of the first metal layer 75 is Au and the metal material of the second metal layer 73 is Cu as in this embodiment, the Cu of the second metal layer 73 diffuses into the first metal layer 75. Therefore, the third metal layer 74 between the first metal layer 75 and the second metal layer 73 acts effectively. The third metal layer 74 is preferably made of the same metal material as that of the first barrier layer 72, and the manufacturing process can be simplified.

The first metal layer 75 is provided to connect external connection members such as wires, bumps, and solder from the outside, and constitutes the surface (uppermost surface) of the pad electrode 7. The first metal layer 75 is excellent in adhesion to the external connection member, that is, bondability, and can be applied with metals such as Al (including Al alloy) and Au that are generally applied. Also, it is preferable to apply excellent Au. The first metal layer 75 preferably has a thickness of 100 nm or more, and more preferably 200 nm or more in order to maintain bonding properties. On the other hand, in terms of productivity, the thickness of the first metal layer 75 is preferably 1000 nm or less, more preferably 800 nm or less, and particularly preferably 500 nm or less.
Note that the thicknesses of these layers 71, 72, 73, 74, and 75 may be adjusted by, for example, film forming conditions using a sputtering apparatus.

(Protective layer)
The protective layer 9 covers the exposed surfaces (upper surface and side walls) of the nitride semiconductor layers 2, 3, and 4 in the semiconductor element 10, the surface of the translucent electrode 6, and the like. A membrane. Specifically, the region excluding the peripheral edge portion of the upper surface of the pad electrode 7 is used as a bonding region (pad portion), and the protective layer 9 is formed on the entire surface excluding the pad portion region. The protective layer 9 is made of a light-transmitting insulating film such as an oxide of Si, Ti, Ta, etc., and can be formed by a known method such as a vapor deposition method or a sputtering method, and its film thickness is particularly limited. Although it is not, it is preferable to set it as 100-1000 nm.

  Here, in the present embodiment, Au of the first metal layer 75 constituting the uppermost surface of the pad electrode 7 is inferior in adhesion to the protective layer 9 made of oxide, so that the protective layer 9 is peeled off from the end of the pad portion. There is a fear. In order to prevent this, it is preferable to form a film of Ni or the like as the adhesion layer 82 in a region on the upper surface of the first metal layer 75 and immediately below the protective layer 9. Further, in the case where the adhesion layer 82 is formed of Ni, if Ni diffuses from the adhesion layer 82 to the first metal layer 75, the bonding property is deteriorated. To prevent this, the second barrier layer is formed below the adhesion layer 82. 81 is preferably formed. The second barrier layer 81 can be formed of Pt, Ru, Rh, Ta, Ir, W, or the like. The thicknesses of the second barrier layer 81 and the adhesion layer 82 are not particularly limited, but in order to work properly, the second barrier layer 81 is 20 to 50 nm and the adhesion layer 82 is 1 to 20 nm. Is preferred. In addition, the two layers (for example, Pt / Ni layer) of the second barrier layer 81 and the adhesion layer 82 are appropriately referred to as a base layer 8. The underlayer 8 can also be formed by a known method such as a vapor deposition method or a sputtering method similarly to each metal layer constituting the pad electrode 7, and is continuously formed from the ohmic contact layer 71 to the underlayer 8. Can be membrane.

  The semiconductor element 10 according to the embodiment of the present invention having the above configuration includes the electrode 7 having a low sheet resistance and excellent current diffusibility. For this reason, the semiconductor element 10 according to the embodiment of the present invention is a semiconductor element with a reduced forward voltage (Vf).

(Method for manufacturing pad electrode of semiconductor element)
An example of the method for manufacturing a pad electrode of a semiconductor element according to the present invention will be described, including the manufacture of the semiconductor element according to the first embodiment.

  First, using a sapphire substrate as a substrate 1 and using a MOVPE reactor, a first buffer layer, a second buffer layer, and an n-side contact layer constituting an n-type nitride semiconductor layer 2 on the substrate 1 A third buffer layer and an n-side multilayer film layer, an active layer is grown on the n-side multilayer film layer, and then a p-type nitride semiconductor layer 4 is formed. A multilayer film layer and a p-side contact layer are grown in this order. Then, the substrate 1 (hereinafter referred to as a wafer) on which each layer of the nitride semiconductor is grown is annealed at about 600 to 700 ° C. in a nitrogen atmosphere in the processing chamber of the apparatus, so that the p-type nitride semiconductor layer 4 has a low resistance. Turn into.

  Next, a part of n-type nitride semiconductor layer 2 is exposed as a contact region for connecting n-side electrode (n-side pad electrode) 7n. A mask having a predetermined shape is formed on the annealed wafer with a photoresist, and p-type nitride semiconductor layer 4 and active layer 3, and n-type nitride semiconductor layer 2 are further formed by reactive ion etching (RIE). The n-side multilayer layer and the third buffer layer are removed to expose the n-side contact layer on the surface. After the etching, the resist is removed. The peripheral portion (scribe region) of the semiconductor element 10 (chip) may be etched simultaneously with the contact region.

  Thereafter, an ITO film is formed as a translucent electrode 6 on the entire surface of the wafer by a sputtering apparatus. Then, a mask having a shape corresponding to the plan view shape of the p-type nitride semiconductor layer 4 below is formed on the ITO film with a photoresist, etched, and light-transmitted on the p-type nitride semiconductor layer 4 The conductive electrode 6 is formed. After the etching, the resist is removed. Next, annealing is performed at about 500 ° C. in a nitrogen atmosphere, the ohmic contact between the translucent electrode 6 (ITO film) and the p-type nitride semiconductor layer 4, and the exposed n-type nitride of the contact region. The ohmic contact property of the semiconductor layer 2 to the n-side pad electrode 7n is improved.

  Next, a mask is formed on the exposed n-type nitride semiconductor layer 2 and a predetermined region in each of the translucent electrodes 6 with a photoresist, and a pad is formed on the mask by a sputtering apparatus. A total of eight metal films of Ti, Pt, Ru, Cu, Ru, Au constituting the electrode 7 and Pt, Ni constituting the base layer 8 are successively formed in a predetermined thickness. Thereafter, when the resist is removed together with the metal film thereon, the n-side pad electrode 7n and the p-side pad electrode 7p are formed in the predetermined region (lift-off method), and Pt, Ni in the same plan view shape thereon. These two layers of films are stacked.

  Next, in order to improve the ohmic contact property of the ITO film, the wafer is subjected to heat treatment (annealing) in a nitrogen atmosphere. The heat treatment temperature is preferably 280 ° C. or higher. On the other hand, if the temperature is too high, the nitride semiconductor layers 2, 3, and 4 are deteriorated by heat, and the ohmic contact properties of the n-type nitride semiconductor layer 2 and the p-type nitride semiconductor layer 4 are reduced. The temperature of the heat treatment is preferably 500 ° C. or less because there is a risk that the light emission intensity of the semiconductor element 10 is lowered. Moreover, although processing time is set according to temperature and thickness, such as Ti layer, about 10 to 20 minutes are preferable.

Thereafter, a SiO ₂ film is formed as a protective layer 9 on the entire surface of the wafer by a sputtering apparatus. That is, as a pad portion, a mask having a predetermined region on the Pt, Ni film on the pad electrode 7 is formed with a photoresist, and after etching the SiO ₂ film, the resist is removed. Ni and Pt are etched using the remaining SiO ₂ film (protective layer 9) as a mask to expose the Au layer 75 in the pad portion.

  Then, the wafer is separated by scribing, dicing or the like to form one semiconductor element 10 (chip). Further, before separation into chips, the substrate 1 may be ground (back grind) from the back surface of the wafer and thinned to a desired thickness.

  The manufacturing method of the pad electrode 7 of the semiconductor element according to the present invention by the above steps can simultaneously form the pad electrodes 7n and 7p on the p side and the n side respectively for the semiconductor element 10 according to the first embodiment. Therefore, productivity is improved.

Second Embodiment
FIG. 4 is a plan view schematically showing the semiconductor element according to the second embodiment. FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. 4 schematically showing the semiconductor element according to the second embodiment.

  In the semiconductor element according to the second embodiment, the n-side electrode 20 has substantially the same structure as the stacked structure of the electrodes according to the first embodiment. As shown in FIGS. The arrangement of the electrodes 20 and 30 with respect to 28 is different. In addition, about the same structure as the semiconductor element which concerns on 1st Embodiment, there is a part which abbreviate | omits description suitably.

  The semiconductor element according to the second embodiment includes a semiconductor layer 28, electrodes 20, 30, a protective layer 40, an insulating layer 42, a bonding layer 50, an adhesion layer 60, a conductive substrate 70, and a metallized layer 80. And at least.

  More specifically, the semiconductor layer 28 in this embodiment includes an n-type nitride semiconductor layer 22, an active layer 24, and a p-type nitride semiconductor layer 26 in order from the upper surface side. The n-type nitride semiconductor layer 22 is provided with a protective film 40 so that the n-side electrode 20 is connected to the upper surface, and at least a part of the n-side electrode 20 is exposed. As in the first embodiment, the n-side electrode 20 has a first metal layer on the outermost surface and a second metal layer (not shown) closer to the semiconductor layer than the first metal layer. The p-type nitride semiconductor layer 26 has a p-side electrode 30 connected to the lower surface, and an insulating layer 42 is provided so as to surround the p-side electrode 30. The p-side electrode 30 may have the same stacked structure as that of the n-side electrode 20, but is not limited thereto. Further, the protective layer 40 and the insulating layer 42 in the present embodiment are made of the same member, and are continuously provided on the side surface of the semiconductor layer 28 without an interface. The insulating layer 42 is disposed so as to face the n-side electrode 20 with the semiconductor 28 interposed therebetween, and the adhesion layer 60 is provided on the surface side in contact with the semiconductor layer 28. The bonding layer 50 is provided on the lower surfaces of the p-side electrode 30 and the insulating layer 42 and is electrically connected to the p-side electrode 30. Further, the bonding layer 50 is provided so as to fill a portion where the insulating layer 42 and the adhesion layer 60 are separated from the p-side electrode 30. In addition, a conductive substrate 70 and a metallized layer 80 are sequentially provided on the lower surface of the bonding layer 50.

  The semiconductor element according to the second embodiment having the above-described configuration can reduce the forward voltage (Vf), similarly to the semiconductor element according to the first embodiment.

  An example in which a semiconductor element was fabricated and the effect of the present invention was confirmed with respect to a laminated structure of electrodes will be described in comparison with a comparative example that does not satisfy the requirements of the present invention. In addition, this invention is not limited to this Example.

(Creation of semiconductor elements)
The semiconductor device having the structure according to the second embodiment shown in FIGS. 4 and 5 as Comparative Example 1 and Examples 1 to 3 is manufactured by the following method.
On a growth substrate (not shown) made of sapphire or the like, a semiconductor layer 28 is formed by growing an n-type nitride semiconductor layer 22, a light emitting layer 24, and a p-type nitride semiconductor layer 26 in this order using a MOVPE reactor. To do.

Next, a mask corresponding to the arrangement of the p-side electrode 30 is formed on the upper surface of the p-type nitride semiconductor layer 26 using a resist, and Ag, Ni, Ti, and Pt are successively and sequentially formed by sputtering. Thus, the p-side electrode 30 is formed. Thereafter, a mask was formed on the p-side electrode 30 using a resist, Ti was deposited by sputtering to form a Ti layer 60, and subsequently SiO ₂ was deposited to form an SiO ₂ layer 42. After that, the mask is removed. Subsequently, Pt, Au, and AuSn are sequentially formed on the SiO ₂ layer 42 from which the mask has been removed and the p-side electrode 30 to form the first bonding layer 50.

On the other hand, a conductive substrate 70 such as Si is prepared, and Au, Pt, TiSi ₂ are sequentially formed on the upper surface of the conductive substrate 70 to form the second bonding layer 50. Further, Ag is formed on the lower surface of the conductive substrate 70 to form the metallized layer 80.

  Next, the 1st joining layer 50 and the 2nd joining layer 50 are bonded together, and it heats and joins at about 150 ° C-350 ° C. As a result, a part of the first bonding layer 50 and a part of the second bonding layer 50 form a eutectic, and the semiconductor layer 28 and the conductive substrate 70 are bonded.

Next, laser irradiation or polishing is performed from the growth substrate side to remove the growth substrate, and then the exposed semiconductor layer (n-type nitride semiconductor layer) 22 is chemically polished (CMP). Further, on the polished surface, a mask is formed using a resist so that the n-side electrode 20 is formed at a portion facing the SiO ₂ layer 42 with the semiconductor layer 28 interposed therebetween and not overlapping the p-side electrode 30. . Then, after sputtering, Ti, Pt, Cu, Ru, and Au are formed on the semiconductor layer 22 in this order to form the n-side electrode 20, and then Ti, SiO ₂ , and Al are sequentially formed as an underlayer (not shown). Form a film. The specific structure of the n-side electrode 20 and the thickness of each layer are as shown in Table 2. The portion where the mask is provided, that is, the region where the n-side electrode 20 is not formed is perforated by RIE (reactive ion etching) to expose the semiconductor layer 22. Finally, after forming the protective layer 40 on the exposed semiconductor layer 22, the protective layer 40 and the underlayer are partially etched so that the surface (first metal layer) of the n-side electrode 20 is exposed as a pad portion. Thus, a semiconductor element is obtained.

  As described above, the forward voltage (Vf) is measured in order to evaluate the initial characteristics of the manufactured semiconductor element. The current value used for this measurement is 1A.

(Evaluation of initial characteristics)
Table 2 shows the relationship between the electrode structure and the forward voltage (Vf). In addition, the forward voltage (Vf) in Table 2 is a value obtained by rounding off three decimal places.

  As shown in Table 2, Comparative Example 1 having an electrode structure of “Ti / Pt / Ru / Au” has a forward voltage of 3.49 V, whereas a Cu layer is interposed between the Pt layer and the Ru layer. It can be seen that Examples 1 to 3 of “Ti / Pt / Cu / Ru / Au” have a forward voltage of 3.46 V, 3.41 V, and 3.39 V, all lower than the forward voltage of Comparative Example 1. Further, by setting the thickness of the Cu layer to 50 nm or more, that is, the thickness of the Au layer or more as in Example 2 and Example 3, the forward voltage is −0.08 than that of Comparative Example 1, respectively. , −0.10, which is greatly reduced. In particular, in Example 2, the decrease in forward voltage with respect to the thickness of the Cu layer is the largest.

  As described above, according to the present invention, the electrode has the Cu layer that is the second metal layer having higher electrical conductivity than the Au layer that is the first metal layer, that is, the current diffusion is reduced by reducing the sheet resistance of the electrode. By improving the property, a semiconductor element with reduced forward voltage (Vf) can be obtained.

  The present invention has been described in detail with reference to the embodiments and examples. However, the gist of the present invention is not limited to the above-described contents, and the scope of right is widely interpreted based on the description of the claims. There must be. Needless to say, the contents of the present invention can be widely modified and changed based on the above description.

  For example, the electrode of the semiconductor element according to the present invention is not limited to the semiconductor element according to the embodiment and the example (see FIGS. 2 and 5). For example, the n-side electrode is on the back surface (lower surface) side of the conductive substrate. It can also be applied to a provided semiconductor element (not shown). In the first embodiment, Au is applied to the first metal layer. However, a metal such as Al (including an Al alloy) that is excellent in bonding properties and generally applied may be applied. In addition, the structure of the semiconductor element may be appropriately changed as long as it does not depart from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Semiconductor element 1 Substrate 2,22 n-type nitride semiconductor layer 3,24 Active layer 4,26 p-type nitride semiconductor layer 5,30 p-side electrode 6 Translucent electrode 7p p-side pad electrode 7n, 20 n-side electrode (N-side pad electrode)
7 Pad electrode 71 Ohmic contact layer 71a Ti layer 71b Pt layer 72 First barrier layer 73 Second metal layer 74 Third metal layer 75 First metal layer 8 Underlayer 81 Second barrier layer 82 Adhesion layer 9, 40 Protective layer 28 Semiconductor layer 42 Insulating layer (SiO ₂ layer)
50 bonding layers (first bonding layer, second bonding layer)
60 Adhesion layer (Ti layer)
70 conductive substrate 80 metallized layer

Claims (3)

A semiconductor layer in which an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer are stacked in order from the upper surface side that is a light extraction surface, and an n-side pad provided on the upper surface of the n-type nitride semiconductor layer A semiconductor light emitting device having an electrode,
The n-side pad electrode, an Au layer on the outermost surface, the semiconductor layer side from the Au layer, a Ru layer, Cu layer has a structure in which Ru layer are sequentially laminated,
The semiconductor light emitting element, wherein the Cu layer has a thickness greater than or equal to the thickness of the Au layer . The n-side pad electrode is further configured by sequentially stacking a Pt layer and a Ti layer from the Ru layer to the semiconductor layer side,
  The semiconductor light emitting element according to claim 1, wherein the Ti layer is connected to an upper surface of the n-type nitride semiconductor layer. 2. The semiconductor light emitting device according to claim 1, further comprising a conductive substrate electrically connected to the p-type nitride semiconductor layer on a lower surface side of the p-type nitride semiconductor layer.

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