JP5535701B2 - Semiconductor integrated device manufacturing method and semiconductor integrated device - Google Patents

Description

  The present invention relates to a semiconductor integrated device, and more particularly to a method for manufacturing a MOS (Metal Oxide Semiconductor) type semiconductor integrated device having a multiple RESURF (Reduced Surface Field) lateral structure.

  Currently, as such a semiconductor integrated device, a P-type diffusion layer including an N-type diffusion region that controls a source region and a drain region is formed in an N-type epitaxial layer formed on a P-type semiconductor substrate. A structure in which a P-type buried diffusion layer and an N-type buried diffusion layer are stacked below the P-type diffusion layer has been proposed (see, for example, FIG. 1 of Patent Document 1). ). In such a semiconductor integrated device, the N-type buried diffusion layer is formed across the semiconductor substrate and the epitaxial layer. The breakdown voltage of the PN junction region formed by the N type buried diffusion layer and the P type buried diffusion layer is constructed to be lower than the breakdown voltage between the source and the drain. With this structure, when an overvoltage that destroys the transistor is applied to the drain electrode, the PN junction region formed by the N-type buried diffusion layer and the P-type buried diffusion layer breaks down. Thus, it is possible to prevent the destruction of the transistor due to the application of the overvoltage.

  Here, the current sent from the P-type buried diffusion layer through the N-type buried diffusion layer by such breakdown flows into the GND via the P body region and the source electrode formed in the source region, and is consumed. It has come to be.

  However, in the above configuration, since the P-type semiconductor substrate has a relatively high resistance, the potential of the buried diffusion layer cannot be reliably fixed to the GND potential, and the source / drain utilizing the characteristics of the RESURPP structure is utilized. There was a problem that the breakdown voltage could not be improved.

JP 2006-237223 A

  It is an object of the present invention to provide a semiconductor integrated device manufacturing method and a semiconductor integrated device capable of manufacturing a high breakdown voltage semiconductor integrated device without increasing the number of manufacturing steps.

  A method for manufacturing a semiconductor integrated device according to the present invention is a method for manufacturing a semiconductor integrated device in which a semiconductor integrated device is formed on a semiconductor substrate of a first conductivity type, for forming a channel stop region and a sinker region on the semiconductor substrate. A step of patterning the resist film, a step of applying a taper processing to the cross-sectional angle between the side surface of the resist film and the surface of the semiconductor substrate to be less than 90 degrees, and the resist film through the resist film. An ion implantation process for forming the channel stop region of the first conductivity type on the surface of the semiconductor substrate; and from the surface of the semiconductor substrate to below the channel stop region via the resist film An ion implantation process for forming the sinker region of the first conductivity type in the region, and removing the resist film. A step of forming a buried diffusion layer of the first conductivity type in contact with a lower side of the sinker region in the semiconductor substrate, and straddling the sinker region and the semiconductor substrate on a surface of the semiconductor substrate. Forming a body region of the first conductivity type and forming a diffusion region of a second conductivity type having a polarity opposite to the first conductivity type in contact with the body region.

A semiconductor integrated device according to the present invention is a semiconductor integrated device constructed on a semiconductor substrate of a first conductivity type, and has a polarity opposite to that of the first conductivity type formed on the surface of the semiconductor substrate. A well region of two conductivity type, a first diffusion region of the second conductivity type formed on the surface of the well region, a first metal electrode formed on the surface of the first diffusion region, and the well A first oxide film formed on the surface of the region in contact with the first diffusion region; a second diffusion region of the second conductivity type formed on the surface of the semiconductor substrate; and a surface of the semiconductor substrate. A body region of the first conductivity type formed in contact with the second diffusion region; a second metal electrode formed across the surfaces of the second diffusion region and the body region; and the first Oxide film, well region, front A semiconductor substrate, a gate electrode film formed across the surface of each of the second diffusion regions, a second oxide film formed in contact with the body region on the surface of the semiconductor substrate, and in the semiconductor substrate The first conductivity type channel stop layer formed in contact with the lower surface of the second oxide film, and both the semiconductor substrate and the well region are embedded in the semiconductor substrate and the well region. The first conductivity type buried diffusion layer is formed in the semiconductor substrate so as to be in contact with and cover the upper surface of the buried diffusion layer, the lower portion of the body region, and the lower surface of the channel stop layer. The first conductivity type sinker layer.

  In the present invention, the source-drain breakdown voltage is increased by embedding the first conductivity type buried diffusion layer in both of the first conductivity type semiconductor substrate and the second conductivity type well region. By providing a sinker layer (which has a lower electrical resistance than the semiconductor substrate) between the body region in contact with the diffusion region formed on the surface of the semiconductor substrate and the buried diffusion layer, the breakdown voltage is further improved. I try to plan. In addition, the resist film provided on the surface of the semiconductor substrate to form the sinker layer is subjected to a taper processing in which the crossing angle between the side surface of the resist film and the surface of the semiconductor substrate should be less than 90 degrees. Yes. As a result, it is possible to successively perform an ion implantation process for forming a channel stop region and an ion implantation process for forming a sinker region using such a resist film. That is, the ion implantation process for forming the channel stop region and the ion implantation process for forming the sinker region can be performed without exchanging the resist film. Therefore, the source-drain breakdown voltage can be further increased without significantly increasing the number of manufacturing steps.

FIG. 1A is a top transparent view of a power MOSFET as a semiconductor integrated device according to the present invention. FIG. 1B is a diagram showing a cross-sectional structure of the power MOSFET at Y1-Y1 in FIG. 1A. FIG. 2 is a flowchart showing a manufacturing procedure of the power MOSFET shown in FIGS. 1A and 1B. It is a figure which shows the cross-section in the middle of manufacture of power MOSFET (step S1-S4). It is a figure which shows the cross-sectional structure in the middle of manufacture of power MOSFET (step S5). It is a figure which shows the cross-sectional structure in the middle of manufacture of power MOSFET (step S6). It is a figure which shows the cross-sectional structure in the middle of manufacture of power MOSFET (step S7, S8). It is a figure which shows the cross-section in the middle of manufacture of power MOSFET (step S8-S12).

  A sinker layer having a lower electrical resistance than the semiconductor substrate is provided between the body region in contact with the diffusion region formed on the surface of the semiconductor substrate and the buried diffusion layer. Further, the resist film provided on the surface of the semiconductor substrate in order to form such a sinker layer is subjected to a taper processing in which the crossing angle between the side surface and the bottom surface of the semiconductor substrate should be less than 90 degrees.

  1A and 1B are diagrams showing the structure of an n-channel power MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor) as a semiconductor integrated device according to the present invention. Note that FIG. 1A is a transmission diagram when the power MOSFET is viewed from above, and only the forms of a well region 103 and a buried diffusion layer 107, which will be described later, are extracted and shown.

  As shown in FIGS. 1A and 1B, an n-channel well region 103 (hereinafter referred to as an n-well region 103) that serves as a drain region is formed in a p-channel semiconductor substrate 101. The surface of the n-well region 103 is exposed from the surface of the semiconductor substrate 101 so as to be flush with the surface of the semiconductor substrate 101.

  A LOCOS (local oxidation of silicon) oxide film 104 as a field oxide film is formed on the surface of the n-well region 103 in a form protruding from the surface. A gate electrode film 105 is formed at one end of the LOCOS oxide film 104, and an n-channel drain diffusion region 106 is formed at the other end.

  In the n well region 103, a p-channel buried diffusion layer 107 (hereinafter referred to as a p buried diffusion layer 107) is formed below the LOCOS oxide film 104. A drain electrode 108 is formed on the upper surface of the drain diffusion region 106.

  An n-channel source diffusion region 109 is formed in the vicinity of the n-well region 103 on the surface of the semiconductor substrate 101. As shown in FIG. 1B, the gate electrode film 105 is formed across the surfaces of the LOCOS oxide film 104, the n-well region 103, the semiconductor substrate 101, and the source diffusion region 109. Further, a LOCOS oxide film 110 is formed on the surface of the semiconductor substrate 101 so as to separate adjacent transistors in a form protruding from the surface. The LOCOS oxide film 110 and the source diffusion region 109 are separated from each other. A p-channel body region 111 (hereinafter referred to as p body region 111) is formed between the two. A source electrode 112 that is a metal electrode is formed in contact with the upper surfaces of the source diffusion region 109 and the p body region 111. The surfaces of the LOCOS oxide film 104, the gate electrode film 105, the drain diffusion region 106, the source diffusion region 109, the LOCOS oxide film 110, and the p body region 111 are covered with an oxide film 113.

In the semiconductor substrate 101, in a region below the source diffusion region 109, the LOCOS oxide film 110, and the p body region 111, a p buried diffusion layer 107 buried in the n well region 103 is formed as shown in FIG. 1A. It is formed in a form that wraps around in a ring shape. That is, the p buried diffusion layer 107 is a series of buried diffusion layers that are buried in both of the n well region 103 and the semiconductor substrate 101 as shown in FIGS. 1A and 1B.
In the semiconductor substrate 101, a channel stop layer 115 which is a p-channel type diffusion layer is formed on the lower surface of the LOCOS oxide film 110. The channel stop layer 115 can suppress the generation of an n-type inversion layer and suppress the surface leakage current between adjacent transistors via the LOCOS oxide film 110. Therefore, since the size of the LOCOS oxide film 110 itself provided for element isolation can be reduced, high integration can be achieved.

  Further, in the semiconductor substrate 101, as shown in FIG. 1B, a sinker as a p-channel type diffusion layer that connects and connects a part of the lower surface of the p body region 111 and the lower surface of the channel stop layer 115, respectively. Layer 116 is formed. The lower surface of the sinker layer 116 is in contact with the p buried diffusion layer 107.

  Hereinafter, a method of manufacturing the power MOSFET shown in FIGS. 1A and 1B will be described according to the manufacturing flow shown in FIG.

  First, the n-well region 103 is formed on the semiconductor substrate 101 as shown in FIG. 3A (step S1). Next, as shown in FIG. 3A, regions where the LOCOS oxide films 104 and 110 are to be formed are patterned in the pad oxide film PS and the silicon nitride film SM (step S2). Next, as shown in FIG. 3A, the resist film RM for forming the above-described channel stop layer 115 and sinker layer 116 is patterned (step S3). Note that the film thickness TH of the resist film RM as shown in FIG. 3A is thicker than about 1.0 μm required for the ion implantation process (about 40 KeV) for forming the channel stop layer 115, for example, 4.0 μm. To do.

Next, as shown in FIG. 3A, the resist film RM is subjected to a taper processing so that the crossing angle Q between the side surface FL and the surface of the semiconductor substrate 101 is less than 90 degrees, in particular, 70 degrees or less ( Step S4). As such processing, for example, the resolution at the bottom edge portion of the resist film RM is suppressed by defocus processing such that the focus is adjusted to the surface of the semiconductor substrate 101 during exposure or exposure amount reduction processing. Alternatively, the upper portion of the resist film RM may be self-contracted by resist curing. Next, as shown in FIG. 3B, ion implantation processing for forming a channel stop region is performed from the upper surface side of the semiconductor substrate 101 (step S5). As a result, a p-channel type channel stop region SA is formed near the surface of the semiconductor substrate 101 as shown in FIG. 3B. Subsequently, as shown in FIG. 3C, ion implantation processing for forming a sinker region is performed from the upper surface side of the semiconductor substrate 101 (step S6). In this ion implantation process, the p buried diffusion layer 107 formed at a depth of about 2.4 μm from the surface of the semiconductor substrate 101 is connected to the p body region 111 formed at a depth of about 0.3 μm. In order to take a role, boron is ion-implanted at 800 KeV and 1.0E13 ions / cm ² so that the peak reaches a depth of about 2.0 μm. As a result, as shown in FIG. 3C, a p-channel type sinker region CA having a concentration higher than that of the semiconductor substrate 101 is formed on the lower surface of the channel stop region SA formed near the surface of the semiconductor substrate 101. That is, the sinker region CA having a lower electrical resistance than the semiconductor substrate 101 is formed in contact with the lower surface of the channel stop region SA. A part of the sinker area CA is exposed from the surface of the semiconductor substrate 101 as shown in FIG. 3C.

  Next, the resist film RM is removed (step S7), and a LOCOS oxidation is performed on the surface of the semiconductor substrate 101 and the n-well region 103 in a region not covered with the pad oxide film PS and the silicon nitride film SM as shown in FIG. 3D. After forming the films 104 and 110, the pad oxide film PS and the silicon nitride film SM are removed (step S8). As a result, a channel stop layer 115 based on the channel stop region SA is formed on the lower surface of the LOCOS oxide film 110. Next, boron is ion-implanted at 1200 KeV so that a peak reaches a position at a depth of about 2.4 μm in the n-well region 103, so that p buried diffusion is performed below the LOCOS oxide film 104 as shown in FIG. 3E. A partial region of layer 107 (hereinafter referred to as an n-well buried region) is formed. Further, boron is ion-implanted at 1200 KeV so as to reach a peak at a depth of about 2.4 μm with respect to the region below the LOCOS oxide film 110 in the semiconductor substrate 101, as shown in FIG. 3E. A partial region of the p buried diffusion layer 107 (hereinafter referred to as a substrate buried region) is formed in the substrate 101 (step S9). Next, an n-channel drain diffusion region 106 is formed in a region sandwiched between two LOCOS oxide films 104 adjacent to each other on the surface of the n-well region 103 and sandwiched between LOCOS oxide films 104 and 110 adjacent to each other. In this region, an n-channel source diffusion region 109 is formed (step S10). Next, p body region 111 is formed in a region sandwiched between source diffusion region 109 and LOCOS oxide film 110. By forming the p body region 111 and the p buried diffusion layer 107, the p body region 111 and the channel stop layer 115 are formed between the p buried diffusion layer 107 formed in the semiconductor substrate 101 as shown in FIG. 3E. Then, a sinker layer 116 based on the sinker area CA is formed (step S11). As a result, p buried diffusion layer 107 and p body region 111 are connected through sinker layer 116. Next, as shown in FIG. 3E, a gate electrode film 105 is formed so as to continuously cover a part of the surface of each of the LOCOS oxide film 104, the n-well region 103, the semiconductor substrate 101, and the source diffusion region 109 (step). S12). Next, as shown in FIG. 1B, a drain electrode 108 as a metal electrode is formed on the upper surface of the drain diffusion region 106, and a source electrode 112 as a metal electrode is straddled across the upper surfaces of the source diffusion region 109 and the p body region 111, respectively. Is formed (step S13). 1B, an oxide film 113 is formed so as to cover the surfaces of the LOCOS oxide film 104, the gate electrode film 105, the drain diffusion region 106, the source diffusion region 109, the LOCOS oxide film 110, and the p body region 111. Form (step S14).

  Through the manufacturing process as described above, a power MOSFET having a structure as shown in FIGS. 1A and 1B is obtained.

  Hereinafter, the operation inside the power MOSFET having the structure shown in FIGS. 1A and 1B will be described.

  In such a power MOSFET, a p buried diffusion layer 107 is formed across both the p channel type semiconductor substrate 101 and the n well region 103. Here, a first NP junction region is formed by n well region 103 and drain diffusion region 106 and n well buried region in p buried diffusion layer 107. The n well region 103, the drain diffusion region 106, and the semiconductor substrate 101 form a second NP junction region.

  Incidentally, the semiconductor substrate 101 interposed between the substrate buried region in the p buried diffusion layer 107 and the source electrode 112 has a relatively high resistance. Therefore, it is difficult to bring the p buried diffusion layer 107 close to the GND potential of the source electrode 112, and the source-drain breakdown voltage cannot be significantly increased.

  Therefore, in the power MOSFET shown in FIGS. 1A and 1B, the electric power between the p body region 111 formed in the source electrode 112 and the substrate buried region in the p buried diffusion layer 107 is lower than that of the semiconductor substrate 101. The sinker layer 116 having resistance is connected. As a result, the potential of the n-well buried region is connected to the source electrode 112 via the substrate buried region, the sinker layer 116 and the p body region 111, and can be brought close to the GND potential of the source electrode 112. Become. As a result, when a voltage is applied to the drain electrode, both the first NP junction region and the second NP junction region are depleted, so that the characteristics of the RESURF structure can be fully utilized, and the source-drain breakdown voltage can be increased. Can be greatly increased.

  Further, in the present invention, the sinker layer 116 serving as a path connected to the source electrode 112 via the substrate buried region and the p body region 111 is provided in order to bring the potential of the n well buried region close to the GND potential. In steps S3 to S6 shown in FIG. That is, the sinker layer 116 is formed together with the channel stop layer 115 by ion implantation using the resist film RM as shown in FIGS. 3A to 3C. That is, the resist film RM is subjected to taper processing so that the crossing angle Q between the side surface FL and the surface of the semiconductor substrate 101 is less than 90 degrees (particularly 70 degrees or less), thereby forming a channel stop region. Therefore, the ion implantation process (step S5) for forming the ion beam and the ion implantation process for forming the sinker region (step S6) can be realized without exchanging the mask (resist film RM). Therefore, it is possible to form the sinker layer 115 for increasing the breakdown voltage between the source and the drain without significantly increasing the number of manufacturing steps.

101 Semiconductor substrate 107 p buried diffusion layer 109 source diffusion region 110 LOCOS oxide film 111 p body region 115 channel stop layer 116 sinker layer

Claims (5)

A method for manufacturing a semiconductor integrated device in which a semiconductor integrated device is formed on a semiconductor substrate of a first conductivity type,
Patterning a resist film for forming a channel stop region and a sinker region on the semiconductor substrate;
Subjecting the resist film to a taper processing to make the crossing angle between the side surface of the resist film and the surface of the semiconductor substrate less than 90 degrees;
Performing an ion implantation process to form the channel stop region of the first conductivity type on the surface of the semiconductor substrate through the resist film;
Performing an ion implantation process for forming the sinker region of the first conductivity type in a region from the surface of the semiconductor substrate to the lower side of the channel stop region via the resist film;
Removing the resist film;
Forming a buried diffusion layer of the first conductivity type in contact with a lower side of the sinker region in the semiconductor substrate;
Forming a body region of the first conductivity type straddling the sinker region and the semiconductor substrate on a surface of the semiconductor substrate, and a second conductivity type having a polarity opposite to the first conductivity type in contact with the body region; And a step of forming a diffusion region.   2. The method of manufacturing a semiconductor integrated device according to claim 1, wherein an intersection angle between the side surface of the resist film and the surface of the semiconductor substrate is 70 degrees or less.   3. The method of manufacturing a semiconductor integrated device according to claim 1, wherein an electric resistance of the sinker region is lower than an electric resistance of the semiconductor substrate. A semiconductor integrated device constructed on a first conductivity type semiconductor substrate,
A well region of a second conductivity type opposite in polarity to the first conductivity type formed on the surface of the semiconductor substrate;
A first diffusion region of the second conductivity type formed on the surface of the well region;
A first metal electrode formed on a surface of the first diffusion region;
A first oxide film formed in contact with the first diffusion region on the surface of the well region;
A second diffusion region of the second conductivity type formed on the surface of the semiconductor substrate;
A body region of the first conductivity type formed in contact with the second diffusion region on the surface of the semiconductor substrate;
A second metal electrode formed across the surface of each of the second diffusion region and the body region;
A gate electrode film formed across the surfaces of the first oxide film, the well region, the semiconductor substrate, and the second diffusion region;
A second oxide film formed in contact with the body region on the surface of the semiconductor substrate;
A channel stop layer of the first conductivity type formed in contact with the lower surface of the second oxide film in the semiconductor substrate;
A buried diffusion layer of the first conductivity type embedded in the semiconductor substrate and the well region across both the semiconductor substrate and the well region;
A sinker layer of the first conductivity type formed so as to be in contact with and cover the upper surface of the buried diffusion layer, the lower portion of the body region, and the lower surface of the channel stop layer in the semiconductor substrate; And a semiconductor integrated device.   5. The semiconductor integrated device according to claim 4, wherein an electric resistance of the sinker layer is lower than an electric resistance of the semiconductor substrate.

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