JP5541219B2 - Semiconductor switching element driving device - Google Patents

Description

  The present invention relates to a semiconductor switching element driving device that drives a semiconductor switching element by applying a driving current to a control terminal of the semiconductor switching element.

Conventionally, a drive circuit for driving an IGBT has been proposed in, for example, Patent Document 1. Specifically, in Patent Document 1, a first drive circuit that supplies a first current to a control terminal (gate) of an IGBT, a second drive circuit that supplies a second current, and a voltage of the control terminal A drive circuit in which a voltage monitor for detecting a value is connected is proposed. In such a drive circuit, when the voltage at the control terminal of the IGBT is lower than the threshold voltage, only the first drive circuit is used as the control terminal. When the first current is supplied and the voltage of the control terminal reaches the threshold voltage, the second current is supplied to the control terminal in addition to the first current. Thereby, the current change of the current between the collector and the emitter when the IGBT is turned on is suppressed to be small, and the period of the mirror region where the voltage of the control terminal is constant is shortened.

  It is generally known that by increasing the current applied to the control terminal of the IGBT, the rising slew rate of the control terminal voltage is increased and the switching speed is increased.

JP 2008-29059 A

  However, in the surge generation period until the IGBT starts to flow current from the completely off state to the control terminal, the voltage of the control terminal reaches the mirror voltage which is a constant voltage and the mirror period in which the mirror voltage is maintained is completed. If the current flowing through the control terminal is increased to increase the switching speed and the slew rate of the voltage at the control terminal is increased, a surge voltage is likely to be generated, and the semiconductor switching element may be destroyed.

  Thus, since the switching speed and the surge voltage are in a contradictory relationship, if the current flowing through the control terminal is reduced in order to suppress the generation of the surge voltage, the switching speed is slowed down, and the voltage at the control terminal becomes the mirror voltage. It takes time to make a transition to a higher drive voltage (completely on state). Therefore, it is extremely difficult to achieve both suppression of the surge voltage and shortening of the voltage transition time.

  Further, in Patent Document 1, since a voltage monitor (gate voltage monitoring circuit) is used to determine the timing for increasing the current applied to the control terminal, there is a problem that the circuit scale of the drive circuit increases. .

  In the above description, the drive circuit for driving the IGBT as the semiconductor switching element has been described. Of course, the IGBT is an example of the element, and the same problems as described above also occur for the other semiconductor switching elements.

  An object of the present invention is to provide a semiconductor switching element driving device capable of reducing the circuit scale while suppressing the occurrence of surge and improving the switching speed of the semiconductor switching element.

  In order to achieve the above object, according to the first aspect of the present invention, the control terminal (11) has the control terminal (11), and the voltage of the control terminal (11) reaches the mirror voltage according to the drive current applied to the control terminal (11). A semiconductor switching element (10) that reaches a drive voltage higher than the mirror voltage later is provided.

  The semiconductor switching element (10) is driven by applying a driving current to the control terminal (11) of the semiconductor switching element (10), and the voltage of the control terminal (11) of the semiconductor switching element (10) is Control of the semiconductor switching element (10) and the drive means (60) set so that the time from the mirror voltage to the drive voltage is shortened as the magnitude of the drive current applied to the control terminal (11) increases. The voltage at the terminal (11) is detected, and when the voltage at the control terminal (11) becomes larger than the mirror voltage, a mirror interval end signal is output indicating that the mirror interval in which the mirror voltage is maintained has ended. And a state detecting means (20).

  Further, the short-circuit state of the semiconductor switching element (10) is detected, and when the mirror section end signal is input, the detection of the short-circuit state is started and the control signal indicating that the detection of the short-circuit state is started is output. When a control signal is input from the means (30) and the short-circuit detection means (30), the detection time until the detection of the short-circuit state by the short-circuit detection means (30) is terminated using the input of the control signal as a trigger, A time setting means (40) for outputting a time setting signal indicating that the detection time has elapsed after the detection time has elapsed, and when the time setting signal is input from the time setting means (40), the input of the time setting signal is used as a trigger. Signal generating means (50) for outputting a current control signal for increasing the drive current applied to the control terminal (11) of the semiconductor switching element (10). , And a.

  Then, the drive means (60) determines the amount of drive current applied to the control terminal (11) according to the current control signal from the signal generation means (50) until the voltage at the control terminal (11) reaches the mirror voltage. It is characterized by an increase in the amount of drive current applied to the control terminal (11).

  According to this, since the drive current to be applied to the control terminal (11) is increased after the detection of the short-circuit state where there is no fear of surge, the generation of surge voltage can be suppressed. Moreover, since the drive current applied to the control terminal (11) is increased, the time until the voltage of the control terminal (11) of the semiconductor switching element (10) reaches the drive voltage can be shortened, and the switching speed can be increased. Can be improved.

  Further, a configuration in which the short-circuit detection means (30) starts detecting the short-circuit state of the semiconductor switching element (10) after the end of the mirror section, and the drive current is increased after the detection time when the short-circuit state detection ends. Therefore, it is not necessary to add a new means for monitoring the voltage of the control terminal (11). Therefore, the circuit scale of the semiconductor switching element driving device can be reduced.

  In the invention according to claim 2, in the short circuit detection section in which the short circuit detecting means (30) detects the short circuit state of the semiconductor switching element (10), the voltage of the control terminal (11) of the semiconductor switching element (10) is set to the mirror voltage. Clamping means (90) for holding the clamp voltage higher than that of the drive voltage.

  Then, the time setting means (40) outputs the time setting signal to the clamp means (90) and the signal generation means (50), thereby causing the clamp means (90) to release the holding of the clamp voltage and the signal generation means. The drive current applied to the control terminal (11) is increased in the drive means (60) by causing the current control signal to be output to (50).

  Thus, the drive current that flows through the drive means (60) at the timing when the clamp voltage at the control terminal (11) of the semiconductor switching element (10) is released can be increased. For this reason, since the voltage of the control terminal (11) can be raised from the clamp voltage to the drive voltage in a short time, the switching speed of the semiconductor switching element (10) can be improved.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the driving means (60) is connected to the variable resistor (65) provided between the power source (70) and the control terminal (11). The flowing drive current is applied to the control terminal (11), and the drive current applied to the control terminal (11) is increased by decreasing the resistance value of the variable resistor (65) according to the current control signal. Can do.

  As in the invention described in claim 4, in the invention described in claim 3, the drive means (60) is configured such that the resistance value of the variable resistor (65) decreases stepwise in accordance with the current control signal. The drive current applied to the control terminal (11) can be increased stepwise.

  As in the invention described in claim 5, in the invention described in claim 1 or 2, the driving means (60) is connected to the power source (70) and the variable resistance (61) through which the reference current flows, and the control Output means (66) for outputting a comparison or difference between the drive current applied to the terminal (11) and the reference current, and the resistance value of the variable resistor (61) through which the reference current flows according to the current control signal is increased. Thus, the drive current applied to the control terminal (11) can be increased by changing the output of the output means (66).

  And, as in the invention described in claim 6, in the invention described in claim 5, the drive means (60) is configured such that the resistance value of the variable resistor (61) increases stepwise in accordance with the current control signal. The drive current applied to the control terminal (11) can be increased stepwise.

  As in the invention according to claim 7, in the invention according to claim 1 or 2, the drive means (60) includes a resistor (61) through which a reference current flows, and a drive current applied to the control terminal (11). Comparing means (66) for comparing with the reference current, and by changing the output of the comparing means (66) when the reference current flowing through the resistor (61) increases according to the current control signal, the control terminal ( The drive current applied to 11) can be increased.

  As in the invention described in claim 8, in the invention described in claim 7, the driving means (60) is configured such that the reference current flowing through the resistor (61) increases stepwise according to the current control signal. The drive current applied to the control terminal (11) can be increased stepwise.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a conceptual diagram of a semiconductor switching element driving device according to a first embodiment of the present invention. It is a concrete circuit block diagram of a time setting means. It is the figure which showed an example of the delay circuit. It is a timing chart for demonstrating operation | movement of a time setting means. It is the figure which showed the specific circuit structure of the drive means and the signal generation means. It is a figure for demonstrating the action | operation of the semiconductor switching element drive device shown by FIG. It is a circuit block diagram of the semiconductor switching element drive device which concerns on 2nd Embodiment of this invention. It is a circuit block diagram of the semiconductor switching element drive device which concerns on 3rd Embodiment of this invention. 3 is a timing chart for explaining the operation of a logic circuit. It is a figure for demonstrating the action | operation of the semiconductor switching element drive device shown by FIG. It is a circuit block diagram of the semiconductor switching element drive device which concerns on 4th Embodiment of this invention. It is a conceptual diagram of the semiconductor switching element drive device concerning a 5th embodiment of the present invention. It is a figure for demonstrating operation | movement of the semiconductor switching element drive device shown by FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The semiconductor switching element driving device shown in the present embodiment is a device that drives a semiconductor switching element such as an IGBT or a power MOSFET with a constant current.

  FIG. 1 is a conceptual diagram of a semiconductor switching element driving apparatus according to the present embodiment. As shown in this figure, the semiconductor switching element driving device includes a semiconductor switching element 10, a state detecting means 20, a short circuit detecting means 30, a time setting means 40, a signal generating means 50, a driving means 60, It has.

  The semiconductor switching element 10 is a switching element for driving a load (not shown). In the present embodiment, an Nch type IGBT is employed as the semiconductor switching element 10. The semiconductor switching element 10 has a control terminal 11 which is a gate, and this control terminal 11 is connected to the driving means 60. A load (not shown) is connected to either the source side or the drain side of the semiconductor switching element 10. Such a semiconductor switching element 10 is driven according to the drive current (i) applied to the control terminal 11 and reaches a drive voltage higher than the mirror voltage after the voltage at the control terminal 11 reaches the mirror voltage. To work.

  The state detection means 20 detects the voltage (voltage state) of the control terminal 11 of the semiconductor switching element 10. Here, the “voltage state” means that the voltage of the control terminal 11 is a mirror voltage or a drive voltage. Such a state detection unit 20 is configured to determine the voltage state of the control terminal 11 from, for example, the potential difference of a resistor (not shown) connected to the semiconductor switching element 10.

  And the state detection means 20 outputs the mirror area end signal which shows that the mirror area where the mirror voltage was maintained was complete | finished when the voltage of the detected control terminal 11 became larger than a mirror voltage. The “mirror section end signal indicating the end of the mirror section” corresponds to a change in signal from a high level to a low level or a change in signal from a low level to a high level.

  The short circuit detection means 30 detects a short circuit state (that is, an overcurrent) of the semiconductor switching element 10. This short-circuit detection means 30 is a protection function generally associated with the semiconductor switching element 10 such as an IGBT. The short circuit detection means 30 detects the potential difference between the emitter and the collector, and performs short circuit detection by comparison with a set threshold voltage. Of course, the short-circuit state may be detected and determined in another energization path of the semiconductor switching element 10.

  In this embodiment, when the short-circuit detection unit 30 receives the mirror section end signal from the state detection unit 20, the short-circuit detection unit 30 starts detecting the short-circuit state. Along with this, the short circuit detection means 30 outputs a control signal indicating that the detection of the short circuit state has been started to the time setting means 40. The “control signal indicating that the detection of the short circuit state has started” is, for example, a pulse signal. The rise of the pulse signal from the low level to the high level indicates the start of detection of the short circuit state.

  The time setting means 40 measures the detection time from when the short-circuit detection means 30 starts detecting the short-circuit state to when it is completed. Specifically, when the control signal is input from the short-circuit detection unit 30, the time setting unit 40 measures the detection time until the detection of the short-circuit state by the short-circuit detection unit 30 is ended using the input of the control signal as a trigger. Here, “using the input of a control signal as a trigger” means that the control signal rises from a low level to a high level. Then, after the detection time has elapsed, the time setting means 40 outputs a time setting signal indicating that the detection time has elapsed to the signal generation means 50. The “time setting signal indicating that the detection time has elapsed” indicates, for example, that the time setting signal has fallen from a high level to a low level.

  FIG. 2 is a diagram showing a specific circuit configuration of the time setting means 40. As shown in this figure, the time setting means 40 includes a delay circuit 41 and an AND circuit 42. The delay circuit 41 is a circuit that receives a control signal, which is a pulse signal, and outputs the control signal after being delayed by a predetermined time.

  The delay circuit 41 is an RC circuit composed of a resistor 43 and a capacitor 44 as shown in FIG. That is, the time constant of the RC circuit is set to the detection time (ta) of the short circuit state. The delay circuit 41 may be one in which a diode 45 is connected to both ends of a resistor 43 as shown in FIG. The AND circuit 42 is a logic circuit that outputs a high level signal when a plurality of input signals are at a high level, and outputs a low level signal in all other cases.

  FIG. 4 is a timing chart showing the operation when a control signal is input to the time setting means 40. Assuming that the input of the control signal in the AND circuit 42 is A, the inverted input of the delay circuit 41 is B, and the output of the AND circuit 42 is O, as shown in FIG. When the output O becomes high level and the input B of the delay circuit 41 becomes high level with a delay, the output O of the AND circuit 42 becomes low level at that timing. The period during which the output O of the AND circuit 42 is at a high level corresponds to the “detection time ta” from when the short-circuit detection means 30 starts detecting the short-circuit state to when it ends. When the output of the AND circuit 42 changes to a low level after the detection time ta, this indicates that the measurement of the detection time ta is complete.

  When the time setting signal is input from the time setting unit 40, the signal generation unit 50 increases the driving current i applied to the control terminal 11 of the semiconductor switching element 10 with respect to the driving unit 60 using the input of the time setting signal as a trigger. A current control signal for output. Here, “using the input of a time setting signal as a trigger” indicates that the time setting signal has changed from a high level to a low level.

  The driving means 60 generates a driving current i to be applied to the control terminal 11 of the semiconductor switching element 10, and drives the semiconductor switching element 10 by applying this driving current i to the control terminal 11. This drive current i is a current that determines the capability of the drive means 60, that is, the switching speed. The time until the voltage at the control terminal 11 of the semiconductor switching element 10 reaches the drive voltage from the mirror voltage is set to be shorter as the magnitude of the drive current i applied to the control terminal 11 becomes larger. The shorter this time, the faster the switching speed.

  The driving means 60 is configured to drive the semiconductor switching element 10 on / off according to a driving signal input from the outside. And since the time until the voltage of the control terminal 11 of the semiconductor switching element 10 reaches the drive voltage from the mirror voltage becomes shorter as the magnitude of the drive current i becomes larger, the drive means 60 corresponds to the magnitude of the drive current i. The semiconductor switching element 10 is changed from the mirror voltage to the drive voltage over time.

  In the semiconductor switching element driving apparatus described above, specific configurations of the driving unit 60 and the signal generating unit 50 will be described with reference to FIG.

  First, the driving means 60 will be described. As shown in FIG. 5, the driving means 60 includes a resistor 61 (R2 in FIG. 5), a variable constant current circuit 62, a first changeover switch 63, and a second changeover switch 64.

  The resistor 61 has one end connected to the power source 70 and the other end connected to the signal generating means 50. Hereinafter, the resistor 61 is referred to as a “second resistor 61”.

  The variable constant current circuit 62 includes a first resistor 65 (R1 in FIG. 5), an operational amplifier 66, and a switching element 67.

  The first resistor 65 is a sensing resistor through which a current corresponding to the drive current i flowing through the control terminal 11 of the semiconductor switching element 10 flows. One end of the first resistor 65 is connected to the power supply 70 (VB in FIG. 5), and the other end is connected to the switching element 67.

  The operational amplifier 66 adjusts the magnitude of the drive current i flowing to the control terminal 11 of the semiconductor switching element 10 by performing feedback control of the current flowing to the first resistor 65 based on the voltage on the other end side of the second resistor 61. It plays a role.

  The non-inverting input terminal (+) of the operational amplifier 66 is connected to the connection point between the other end side of the second resistor 61 and the signal generating means 50. As a result, the first voltage corresponding to the other end of the second resistor 61 is applied to the non-inverting input terminal (+) of the operational amplifier 66. That is, when the voltage of the power source 70 is VB, the current flowing through the second resistor 61 is Ia, and the resistance value of the second resistor 61 is R2, the first voltage is a voltage obtained by subtracting the reference voltage from the power source voltage of the power source 70. It corresponds to (VB-Ia × R2).

  On the other hand, the inverting input terminal (−) of the operational amplifier 66 is connected to the other end side of the first resistor 65. As a result, the second voltage corresponding to the other end of the first resistor 65 is applied to the inverting input terminal (−) of the operational amplifier 66. That is, if the current flowing through the first resistor 65 is i and the resistance value of the first resistor 65 is R1, the second voltage is a voltage obtained by subtracting the voltage drop of the first resistor 65 from the power supply voltage of the power supply 70 (VB -I * R1).

  The switching element 67 is a semiconductor element driven by the output of the operational amplifier 66. In the present embodiment, a Pch type MOSFET is used as the switching element 67. The gate of the switching element 67 is connected to the output terminal of the operational amplifier 66, and the source is connected to the other end side of the first resistor 65. Further, the drain of the switching element 67 is connected to the control terminal 11 of the semiconductor switching element 10.

  The first changeover switch 63 provided in the driving unit 60 is connected between the power supply 70 and the output terminal of the operational amplifier 66. In the present embodiment, a Pch-type MOSFET is employed as the first changeover switch 63. Therefore, the source of the first changeover switch 63 is connected to the power supply 70, and the drain is connected to the output terminal of the operational amplifier 66.

  On the other hand, the second changeover switch 64 is connected between the control terminal 11 and a reference voltage line such as ground. In the present embodiment, an Nch type MOSFET is employed as the second changeover switch 64. Therefore, the source of the second changeover switch 64 is connected to the control terminal 11 of the semiconductor switching element 10, and the drain is connected to a reference voltage line such as ground.

  Further, an inverter 68 is connected to the gate of the first changeover switch 63. Therefore, a drive signal is input to the first changeover switch 63 via the inverter 68, and a drive signal is directly input to the second changeover switch 64. According to this, in each changeover switch 63, 64, a signal input to the other is inverted with respect to a signal input to one.

  The signal generating means 50 is configured as a current source capable of varying the amount of current (Ia) flowing through the second resistor 61, and is connected between the other end of the second resistor 61 and a reference voltage line such as ground. Has been. The signal generating unit 50 includes a switch 51, a first constant current source 52, and a second constant current source 53.

  The first constant current source 52 is connected to the other end side of the second resistor 61 via the switch 51. The second constant current source 53 is directly connected to the other end side of the second resistor 61. The switch 51 is turned on / off according to the time setting signal. In the present embodiment, the switch 51 is turned on when the time setting signal falls from the high level to the low level.

  The current capability of the first constant current source 52 and the current capability of the second constant current source 53 may be the same or different. The current capability of each of the constant current sources 52 and 53 may be set depending on how the magnitude of the current flowing through the second resistor 61 is designed by turning on / off the switch 51.

  With such a configuration, when the switch 51 is turned on by the time setting signal, the first current obtained by adding the current flowing through the first constant current source 52 and the current flowing through the second constant current source 53 to the second resistor 61 is added. Value current flows as Ia. On the other hand, when the switch 51 is turned off by the time setting signal, the current flowing through the first constant current source 52 is disconnected from the path between the power supply 70 and the reference voltage line such as the ground. Only the current flowing through the constant current source 53 flows as Ia. That is, assuming that the current value of the current flowing through the second constant current source 53 is the second current value, a current having a second current value smaller than the first current value flows through the second resistor 61 when the switch 51 is off. .

  And the voltage of the other end side of the 2nd resistance 61 changes because the electric current value of the electric current which flows into the signal generation means 50 changes. The voltage on the other end side of the second resistor 61 corresponds to the current control signal of the signal generating means 50.

  The above is the circuit configuration of the semiconductor switching element driving device according to the present embodiment. In the present embodiment, the drive signal is input from, for example, an external ECU.

  Next, the operation of the semiconductor switching element driving device shown in FIG. 5 will be described with reference to FIG. FIG. 6 shows the waveform of the voltage v at the control terminal of the semiconductor switching element 10 and the waveform of the drive current i for driving the semiconductor switching element 10.

  Here, when the drive signal is at a high level, the first changeover switch 63 is turned on and the power supply voltage is applied to the gate of the switching element 67, so that the switching element 67 is turned off. Further, the second changeover switch 64 is turned on, a current flows from the control terminal 11 to a reference voltage line such as the ground, and the semiconductor switching element 10 is turned off. On the other hand, when the drive signal is at a low level, the first changeover switch 63 is turned off, so that the switching element 67 is driven by the output of the operational amplifier 66. As described above, the driving unit 60 performs an operation of turning off the semiconductor switching element 10 according to the high level driving signal and turning on the semiconductor switching element 10 according to the low level driving signal.

  First, when the drive signal input to the drive means 60 is switched from the high level to the low level, the first changeover switch 63 and the second changeover switch 64 are turned off, and the switching element 67 is driven by the operational amplifier 66. Thereby, the path | route called the power supply 70, the 1st resistance 65, the switching element 67, and the control terminal 11 is formed. Then, the drive current i flows through the control terminal 11 of the semiconductor switching element 10.

  Further, since the switch 51 of the signal generating unit 50 is turned off, a current having a second current value flowing through the second constant current source 53 of the signal generating unit 50 flows through the second resistor 61. Accordingly, when the drive current i flows through the control terminal 11, the gate voltage of the semiconductor switching element 10 rises with a slope corresponding to the magnitude of the drive current i. When the gate voltage reaches the threshold voltage of the semiconductor switching element 10, the semiconductor switching element 10 is turned on, and the voltage v at the control terminal 11 reaches the mirror voltage. The mirror voltage is a voltage determined by characteristics such as an amplification factor of the IGBT which is the semiconductor switching element 10 and is constant in the mirror section shown in FIG.

  Here, the variable constant current circuit 62 is connected to the first resistor 65 so that the first voltage corresponding to the other end of the first resistor 65 and the second voltage corresponding to the other end of the second resistor 61 are equal. The magnitude of the flowing current is feedback controlled.

  Specifically, since the potential of each input terminal of the operational amplifier 66 of the variable constant current circuit 62 becomes the same potential, the first voltage (VB−i × R1) corresponding to the other end side of the first resistor 65 and the second voltage. The operational amplifier 66 controls the switching element 67 so that the second voltage (VB−Ia × R2) corresponding to the other end side of the resistor 61 becomes equal. Accordingly, the drive current i flowing through the first resistor 65 is i = (Ia × R2) / R1, and the current flowing through the first resistor 65 is applied to the control terminal 11 of the semiconductor switching element 10 as a constant constant current.

  As represented by the above formula (i = (Ia × R2) / R1), a driving current i proportional to the magnitude of the current flowing through the second resistor 61 flows through the first resistor 65. . Since only the current flowing through the second constant current source 53 flows through the second resistor 61 as the current Ia, a current proportional to the second current value flows through the first resistor 65.

  Surge will almost never occur when entering the mirror section. That is, the occurrence of surge ends. Moreover, the detection of the short circuit state of the semiconductor switching element 10 is not yet started in the mirror section.

  When the mirror period ends, the voltage v at the control terminal 11 rises again. Here, the state detection means 20 detects that the voltage v of the control terminal has become larger than the mirror voltage, and outputs a mirror section end signal. The short circuit detection means 30 starts detecting the short circuit state of the semiconductor switching element 10 and outputs the above-described control signal. Thereby, the time setting means 40 measures the detection time ta shown in FIG. This detection time ta is a short-circuit detection section in which the short-circuit detection means 30 detects the short-circuit state of the semiconductor switching element 10.

  When the time setting means 40 measures the detection time ta, a time setting signal that changes from a high level to a low level is output. Thereby, the switch 51 of the signal generation means 50 is turned on. Therefore, a current having a first current value obtained by adding the current flowing through the first constant current source 52 of the signal generating unit 50 and the current flowing through the second constant current source 53 flows through the second resistor 61 as Ia. Then, a current proportional to the first current value larger than the second current value flows through the first resistor 65, and the current flowing through the first resistor 65 than when the switch 51 of the signal generating means 50 is turned off. Will increase. Therefore, as shown in FIG. 6, the drive current i increases after the end of the short-circuit detection period, and accordingly, the rising speed of the voltage v at the control terminal 11 of the semiconductor switching element 10 also increases. Note that when the short-circuit detection section ends, detection of the short-circuit state in the short-circuit detection means 30 also ends.

  Thereafter, the voltage v at the control terminal 11 of the semiconductor switching element 10 reaches the maximum drive voltage. This drive voltage is a power supply voltage or a voltage having substantially the same potential as the power supply voltage, and is a voltage for fully turning on the IGBT which is the semiconductor switching element 10.

  As described above, the drive unit 60 applies the current amount of the current flowing through the second resistor 61 from the second current value to the first current value according to the current control signal from the signal generation unit 50 and applies it to the operational amplifier 66. The drive current i applied to the control terminal 11 until the voltage v of the control terminal 11 reaches the mirror voltage is increased by increasing the voltage (VB−Ia × R2) to be applied. The amount of current increases. For this reason, since the time until the voltage v of the control terminal 11 reaches the drive voltage is shortened, the switching speed is improved.

  On the other hand, when the magnitude of the drive current i is not changed even after the short-circuit detection period, the voltage v of the control terminal 11 after the mirror section becomes the magnitude of the drive current i as shown by the one-dot chain line in FIG. Since it continues to rise with the corresponding inclination, it takes a further time Δtb to reach the drive voltage. In other words, in this embodiment, the time for the voltage v of the control terminal 11 to reach the drive voltage is increased by this time difference Δtb.

  As described above, the present embodiment is characterized in that the drive current i applied to the control terminal 11 is increased after the detection of the short-circuit state performed after the mirror section where the occurrence of a surge is expected. Yes.

  As described above, since the drive current i is increased after the mirror section in which the occurrence of the surge is a concern, the occurrence of the surge can be suppressed. In addition, since the drive current i applied to the control terminal 11 is increased after the detection of the short-circuit state where there is no fear of surge, the voltage of the control terminal 11 of the semiconductor switching element 10 can reach the drive voltage quickly. Therefore, the switching speed can be improved while suppressing the occurrence of surge.

  Furthermore, the timing which increases the drive current i uses each signal output from the state detection means 20, the short circuit detection means 30, and the time setting means 40. For this reason, the amount of the drive current i flowing to the control terminal 11 can be controlled without adding a new means such as a comparator for monitoring the voltage v of the control terminal 11. Therefore, the circuit scale of the semiconductor switching element driving device can be reduced.

  As for the correspondence relationship between the description of the present embodiment and the description of the claims, the second resistor 61 corresponds to the “resistance” in the claims, and the operational amplifier 66 is the “comparison means” in the claims. Corresponding to

(Second Embodiment)
In the present embodiment, parts different from the first embodiment will be described. In the first embodiment, the current Ia passed through the second resistor 61 is increased in order to increase the drive current i. However, in the present embodiment, the current Ia passed through the second resistor 61 is kept constant and the second resistor 61 is increased. The resistance value is changed.

  FIG. 7 is a diagram showing a circuit configuration of the semiconductor switching element driving apparatus according to the present embodiment. As shown in this figure, the driving means 60 has a constant current source 69 for supplying a constant reference current Ia.

  Further, the signal generating means 50 includes a second resistor 61 and a switch 51. The second resistor 61 is configured by connecting a resistor 61a having a resistance value R2 and a resistor 61b having a resistance value R3 in series. The resistor 61b is connected to the power source 70, and the resistor 61a is connected to the constant current source 69. A connection point between the resistor 61 a and the constant current source 69 is connected to the non-inverting input terminal (+) of the operational amplifier 66.

  Further, a switch 51 is connected in parallel to the resistor 61b. When the switch 51 is turned on, the resistance value of the second resistor 61 is the resistance value of only the resistor 61a. On the other hand, when the switch 51 is turned off, the resistance value of the second resistor 61 becomes a combined resistance value of the resistors 61a and 61b. Thus, the second resistor 61 is configured such that the resistance value is variable by the switch 51. In the present embodiment, the switch 51 is turned off when the time setting signal falls from the high level to the low level.

  In such a configuration, the voltage on the opposite side (constant current source 69 side) of the resistor 61a to the side to which the resistor 61b is connected corresponds to the current control signal of the signal generating means 50.

  The operational amplifier 66 outputs a comparison or difference between the drive current applied to the control terminal 11 and the reference current. That is, the first voltage corresponding to the other end of the first resistor 65 and the second voltage corresponding to the other end of the second resistor 61, that is, the other end of the resistor 61a are applied to the operational amplifier 66, and the first The operational amplifier 66 drives the switching element 67 so that the voltage and the second voltage are equal.

  When the switch 51 is turned on and the reference current Ia flows only through the resistor 61a, the drive current i flowing through the first resistor 65 is expressed as i = (Ia × R2) / R1 as described above, and the first resistor A current proportional to the resistance value R2 of the resistor 61a flows through 65. On the other hand, if the switch 51 is turned off and the reference current Ia flows through both the resistor 61a and the resistor 61b, the drive current i flowing through the first resistor 65 is expressed as i = (Ia × (R2 + R3)) / R1, A current proportional to the sum of the resistance value R2 of the resistor 61a and the resistance value R3 of the resistor 61b flows through the one resistor 65.

  Therefore, the driving means 60 changes the output of the operational amplifier 66 to the control terminal 11 by changing the output value of the second resistor 61 through which the reference current Ia flows in accordance with the current control signal (that is, when the switch 51 is turned off). The drive current i to be applied is increased.

  As described above, the drive current i applied to the control terminal 11 of the semiconductor switching element 10 can be increased or decreased by adjusting the resistance value of the second resistor 61.

  As for the correspondence between the description of the present embodiment and the description of the claims, the second resistor 61 corresponds to the “variable resistor” in the claims, and the operational amplifier 66 has the “output means” in the claims. ".

(Third embodiment)
In the present embodiment, parts different from the second embodiment will be described. The present embodiment is characterized in that the drive current i is increased stepwise by changing the resistance value of the second resistor 61 stepwise by providing the second resistor 61 in multiple stages.

  FIG. 8 is a diagram showing a circuit configuration of the semiconductor switching element driving apparatus according to the present embodiment. As shown in this figure, in this embodiment, the signal generation means 50 includes a second resistor 61 and switches 54 and 55. The second resistor 61 includes three resistors, a resistor 61a, a resistor 61b, and a resistor 61c. These are connected in series between a power source 70 and a constant current source 69. The resistance value of each resistor may be the same or different.

  Further, a switch 54 is connected in parallel to the resistor 61b, and a switch 55 is connected in parallel to the resistor 61c. According to this, since the combined resistance value of the second resistor 61 changes depending on whether the switches 54 and 55 are turned on or off, the current control signal input to the operational amplifier 66, that is, the second voltage changes. Here, in the present embodiment, the switches 54 and 55 are turned off when the time setting signals (X1 and X2 described later) rise from the low level to the high level.

  The semiconductor switching element driving device includes two time setting means 40 and 46. The configuration of each of these time setting means 40 and 46 is the same as that shown in FIG. 2, one of the time setting means 40 is set to a delay time B1, and the other time setting means 46 is set to be more than B1. A long delay time B2 is set. Therefore, when pulse-like control signals are simultaneously input from the short-circuit detection means 30 to the time setting means 40 and 46, the time setting signal O1 is output from one time setting means 40 after B1, and the other time is set after B2. A time setting signal O2 is output from the setting means 46.

  Further, the semiconductor switching element driving device includes a logic circuit 80. The logic circuit 80 is a circuit configured to generate time setting signals X1 and X2 for turning off the switches 54 and 55 based on the time setting signals O1 and O2 from the time setting means 40 and 46, respectively. .

  FIG. 9 is a timing chart for explaining the operation of the logic circuit 80. As shown in this figure, the time setting signal O1 generated by one of the time setting means 40 is a signal that is at a high level from the rise of the control signal (A) to the rise of the control signal after the delay time B1. . Further, the time setting signal O2 generated by the other time setting means 46 is a signal that is at a high level from the rise of the control signal (A) to the rise of the control signal after the delay time B2.

  Then, when the time setting signal O1 falls from the high level to the low level, the logic circuit 80 outputs the high level time setting signal X1. Thereby, the switch 54 of the signal generation means 50 is turned off. Further, the logic circuit 80 outputs a high level time setting signal X2 when the time setting signal O2 falls from a high level to a low level. Thereby, the switch 55 of the signal generation means 50 is turned off.

  As described above, a change in the voltage v of the control terminal 11 when the second resistor 61 is configured by three resistors will be described with reference to FIG. In addition, since it is the same as 1st Embodiment until a short circuit detection area is complete | finished, this embodiment mainly demonstrates after a short circuit detection area.

  First, since each of the switches 54 and 55 of the signal generating means 50 is in an ON state until the short-circuit detection section is completed, the resistance value of the second resistor 61 is R2 of the resistor 61a, and the resistance value is obeyed. The drive current i (= (Ia × R2) / R1) is applied to the control terminal 11.

  When the short-circuit detection period ends, that is, when the delay time B1 elapses, the time setting signal O1 output from one of the time setting means 40 changes from the high level to the low level. The output time setting signal X1 changes from the low level to the high level. Thereby, since the switch 54 is turned off, the resistance value of the second resistor 61 becomes a combined resistance value of R2 of the resistor 61a and R3 of the resistor 61b, and the resistance value increases. Therefore, since the drive current i is i = (Ia × (R2 + R3)) / R1, as shown in FIG. 10, the drive current i is increased by one step, and the rate of increase of the voltage v at the control terminal 11 is also increased by one step. Get faster.

  Thereafter, when the time setting signal O2 output from the other time setting means 46 changes from the high level to the low level, the time setting signal X2 output from the logic circuit 80 changes from the low level to the high level. Thereby, since the switch 55 is turned off, the resistance value of the second resistor 61 becomes a combined resistance value of all the resistance values R2 to R4, and the resistance value further increases. Therefore, the drive current i becomes i = (Ia × (R2 + R3 + R4)) / R1, so that the drive current i further increases by one step as shown in FIG. 10, and the rate of increase of the voltage v at the control terminal 11 is further increased. One step faster.

  As described above, the driving means 60 applies the drive current applied to the control terminal 11 when the resistance value of the second resistor 61 increases stepwise in accordance with the current control signal, that is, the change of the second voltage input to the operational amplifier 66. i can also be increased in steps.

(Fourth embodiment)
In the present embodiment, parts different from the first to third embodiments will be described. In each of the above embodiments, the drive current i applied to the control terminal 11 is increased by changing the resistance value of the second resistor 61 and the current value of the signal generating means 50. However, in this embodiment, the first resistor The driving current i is increased by changing the resistance value of 65.

  FIG. 11 is a diagram showing a circuit configuration of the semiconductor switching element driving apparatus according to the present embodiment. As shown in this figure, the signal generating means 50 includes a first resistor 65 and a switch 54. The first resistor 65 is configured by connecting a resistor 65a having a resistance value R1 and a resistor 61b having a resistance value R3 in series. The resistor 61 b is connected to the power supply 70, and the resistor 65 a is connected to the switching element 67. Further, a switch 54 is connected in parallel to the resistor 61b.

  In the present embodiment, the switch 54 is turned off when the time setting signal rises from a low level to a high level. Thereby, since the resistance value of the first resistor 65 is R1 + R3, the drive current i is i = (Ia × R2) / (R1 + R3), and the drive current i is reduced. This drive current i is applied to the control terminal 11 until the short-circuit detection section is completed. On the other hand, when the time setting signal falls from the high level to the low level, the switch 54 is turned on. As a result, the resistance value of the first resistor 65 is only R1 of the resistor 65a and becomes smaller than that when the switch 54 is OFF, so that the drive current i becomes i = (Ia × R2) / R1, and the drive current i is To increase. Such a drive current i is applied to the control terminal 11 after the end of the short-circuit detection period.

  As described above, the drive current i flowing through the first resistor 65 provided between the power source 70 and the control terminal 11 is applied to the control terminal 11, and the resistance of the first resistor 65 is determined according to the current control signal. The drive means 60 can also be configured to increase the drive current applied to the control terminal 11 as the value decreases.

(Fifth embodiment)
In the present embodiment, parts different from the first to fourth embodiments will be described. In recent years, semiconductor switching elements 10 such as IGBTs tend to reduce the short-circuit tolerance of the elements themselves due to cost reduction. Here, if a short-circuit current continues to flow through the semiconductor switching element 10 due to a short circuit accident of the device, the element itself undergoes a rapid temperature rise and breaks down. Energy) is called short-circuit tolerance. In the configuration of protecting after detecting a short circuit due to this low short circuit withstand capability, the short circuit withstand capability may be exceeded while the short circuit is being detected, and protection may not be in time. Therefore, the present embodiment is characterized in that the voltage of the control terminal 11 is held at a clamp voltage higher than the mirror voltage and lower than the drive voltage in the short-circuit detection period at the end of the mirror period.

  FIG. 12 is a conceptual diagram of the semiconductor switching element driving device according to the present embodiment. As shown in this figure, the semiconductor switching element driving device includes a clamping means 90.

  The clamping means 90 avoids abrupt fluctuations in the voltage applied to the control terminal 11 by clamping the voltage applied to the control terminal 11 to a clamp voltage higher than the mirror voltage and lower than the drive voltage. It is a circuit that plays a role of preventing destruction of the element 10 due to overshoot or surge. The clamp means 90 is connected between the control terminal 11 and a reference voltage line such as a ground.

  The clamp means 90 includes a switch 91 connected to the control terminal 11. The switch 91 is turned off in accordance with a time setting signal input from the time setting means 40 to the clamping means 90. The clamp means 90 holds the voltage of the control terminal 11 of the semiconductor switching element 10 at the clamp voltage in the short-circuit detection section in which the short-circuit detection means 30 detects the short-circuit state of the semiconductor switching element 10, so that the time setting signal is changed from the high level. When falling to the low level, the switch 91 is turned off. In other words, the time setting unit 40 outputs the time setting signal to the signal generation unit 50, thereby causing the clamp unit 90 to cancel the holding of the clamp voltage. Other configurations are the same as those of the first embodiment, for example.

  FIG. 13 is a diagram for explaining the operation of the semiconductor switching element driving device shown in FIG. The operation is the same as that of the first embodiment until the mirror section ends. The clamping means 90 turns on the switch 91 in response to a command from an external ECU or the like.

  And if the voltage v of the control terminal 11 rises after a mirror area, it will transfer to a short circuit detection area (clamp period) at arbitrary timings. At this time, since the switch 91 of the clamping means 90 is on, the voltage v of the control terminal 11 is higher than the mirror voltage, but is clamped to a voltage lower than the drive voltage. When the time setting signal is output from the time setting unit 40 after the short-circuit detection period is completed, the signal generation unit 50 outputs a current control signal to increase the driving current i applied to the control terminal 11 to the driving unit 60. To do. The clamping means 90 releases the clamp by turning off the switch 91. Thereby, at the end of the short-circuit detection period, the voltage v of the control terminal 11 rises at a stretch from the clamp voltage toward the drive voltage. Therefore, as compared with the case where the drive current i is not increased (one-dot broken line), the switching speed is increased by the time difference Δtb to reach the full-on period.

  As described above, the semiconductor switching element driving device is provided with the clamping means 90, and the driving current i flowing from the driving means 60 can be increased at the timing when the clamp voltage of the control terminal 11 is released at the end of the short circuit detection period. Thereby, the switching speed of the semiconductor switching element 10 can be improved while preventing the semiconductor switching element 10 from being destroyed.

(Other embodiments)
The configuration of the semiconductor switching element driving device shown in each of the above embodiments is merely an example, and is not limited to the configuration described above, and other configurations can be adopted. For example, in the signal generation unit 50 of the first embodiment, the drive current i applied to the control terminal 11 is increased stepwise by increasing the amount of current (Ia) flowing through the second resistor 61 stepwise. You can also. In this case, the signal generating means 50 may be provided with a plurality of constant current sources, and the amount of current (Ia) flowing through the second resistor 61 may be changed stepwise by switching the switches connected to each.

  In addition, in the second to fourth embodiments, the configuration in which the resistance value is changed to increase the drive current i can also be configured to include the clamping means 90 shown in the fifth embodiment. Of course, the drive current i may be increased stepwise in the configuration including the clamp means 90.

  Further, when the drive current i is increased step by step, the number of steps from the mirror voltage (or clamp voltage) to the drive voltage is appropriately set by adjusting the switching speed.

  Further, the level of the signal (for example, the low level or the high level) in which each switch shown in the above embodiments is turned on / off is an example, and can be set as appropriate. Of course, the level of each signal can be set appropriately as well.

DESCRIPTION OF SYMBOLS 10 Semiconductor switching element 11 Control terminal 20 State detection means 30 Short-circuit detection means 40 Time setting means 50 Signal generation means 60 Drive means 70 Power supply 80 Logic circuit 90 Clamp means

Claims (8)

A semiconductor switching element having a control terminal (11) and having a drive voltage higher than the mirror voltage after the voltage of the control terminal (11) reaches a mirror voltage according to a drive current applied to the control terminal (11) (10) and
The semiconductor switching element (10) is driven by applying a driving current to the control terminal (11) of the semiconductor switching element (10), and the control terminal (11) of the semiconductor switching element (10) Drive means (60) set so that the time until the voltage reaches the drive voltage from the mirror voltage decreases as the magnitude of the drive current applied to the control terminal (11) increases,
A mirror that detects the voltage of the control terminal (11) of the semiconductor switching element (10) and maintains the mirror voltage when the voltage of the control terminal (11) becomes higher than the mirror voltage. State detection means (20) for outputting a mirror section end signal indicating that the section has ended;
The short circuit state of the semiconductor switching element (10) is detected. When the mirror section end signal is input, the short circuit state is detected and a control signal indicating that the short circuit state has been detected is output. Short-circuit detection means (30);
When the control signal is input from the short-circuit detection means (30), the detection time until the detection of the short-circuit state by the short-circuit detection means (30) is completed using the input of the control signal as a trigger, and the detection time Time setting means (40) for outputting a time setting signal indicating that the detection time has elapsed after elapse of time;
When the time setting signal is input from the time setting means (40), the current for increasing the drive current applied to the control terminal (11) of the semiconductor switching element (10) using the input of the time setting signal as a trigger Signal generating means (50) for outputting a control signal,
The drive means (60) determines the amount of drive current applied to the control terminal (11) according to the current control signal from the signal generation means (50), and the voltage of the control terminal (11) is the mirror voltage. The semiconductor switching element driving device is characterized in that it increases more than the amount of driving current applied to the control terminal (11) before reaching. In the short-circuit detection section in which the short-circuit detection means (30) detects the short-circuit state of the semiconductor switching element (10), the voltage of the control terminal (11) of the semiconductor switching element (10) is higher than the mirror voltage. Comprising clamping means (90) for holding the clamping voltage lower than the driving voltage;
The time setting means (40) outputs the time setting signal to the clamp means (90) and the signal generation means (50), thereby causing the clamp means (90) to release the holding of the clamp voltage. The drive current applied to the control terminal (11) is increased in the drive means (60) by causing the signal generation means (50) to output the current control signal. Semiconductor switching element driving device.   The drive means (60) applies a drive current flowing in a variable resistor (65) provided between a power supply (70) and the control terminal (11) to the control terminal (11). 3. The semiconductor switching according to claim 1, wherein a drive current applied to the control terminal is increased when a resistance value of the variable resistor decreases in accordance with the current control signal. Element driving device.   The drive means (60) increases the drive current applied to the control terminal (11) stepwise as the resistance value of the variable resistor (65) decreases stepwise according to the current control signal. The semiconductor switching element driving device according to claim 3, wherein:   The drive means (60) is connected to a power source (70) and outputs a comparison or difference between a variable resistor (61) through which a reference current flows and a drive current applied to the control terminal (11) and a reference current. Output means (66), and changing the output of the output means (66) when the resistance value of the variable resistor (61) through which the reference current flows according to the current control signal is increased. 3. The semiconductor switching element driving device according to claim 1, wherein the driving current applied to the terminal (11) is increased.   The drive means (60) increases the drive current applied to the control terminal (11) stepwise as the resistance value of the variable resistor (61) increases stepwise according to the current control signal. 6. The semiconductor switching element driving device according to claim 5, wherein:   The drive means (60) includes a resistor (61) through which a reference current flows, and a comparison means (66) for comparing the drive current applied to the control terminal (11) with the reference current. The reference current flowing in (61) is increased in accordance with the current control signal, so that the drive current applied to the control terminal (11) is increased by changing the output of the comparison means (66). The semiconductor switching element drive device according to claim 1 or 2.   The drive means (60) increases the drive current applied to the control terminal (11) stepwise as the reference current flowing through the resistor (61) increases stepwise according to the current control signal. The semiconductor switching element driving device according to claim 7.

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