JP5541507B2 - Alignment marker overlap determination circuit, alignment marker overlap determination method, and program - Google Patents

Description

  The present invention relates to an alignment marker duplication determination circuit, an alignment marker duplication determination method, and a program in data communication performed by distributing data to a plurality of lanes and inserting an alignment marker for each lane.

  In the IEEE (The Institute of Electrical and Electronic Engineers) 802.3ba Task Force (TF), a standard specification of a communication method of 40 gigabits (Gb) per second or more is being advanced. In the IEEE 802.3ba communication system, communication data is encoded by a 64B / 66B encoding system (data is encoded by adding a 2-bit synchronization header every 64 bits (bits) to form a 66-bit block (Block). The communication data is divided into a plurality of virtual lanes (VL). The virtual lane is associated with a physical communication path, and communication is performed using the physical communication path. At this time, the number of lanes (number of channels) of the physical communication path may be a divisor of the number of virtual lanes, and the degree of freedom of the physical communication path is high. For example, in 100 Gigabit Ethernet (“Ethernet” is a registered trademark), the communication data that has been blocked is distributed to 20 virtual lanes. Two virtual lanes may be collected and transmitted in association with a communication channel of 10 channels, or five virtual lanes may be collected and transmitted in association with a communication channel of 4 channels. .

  Also, in the IEEE 802.3ba communication method, the transmission device uses an alignment marker (Alignment Marker) that is composed of 66 bits as in the communication data block and indicates the synchronization timing between virtual lanes and the virtual lane number. Insert and transmit to the lane at the same timing. With this alignment marker, the reception device can acquire the communication data in the same arrangement order and the same synchronization timing as when the transmission device distributes the communication data to the virtual lane (for example, see Non-Patent Document 1).

FIG. 7 is a diagram showing an example of an alignment and synchronization circuit that aligns and synchronizes data blocks transmitted by the IEEE 802.3ba communication method. The alignment / synchronization circuit 1023 shown in the figure is included in a receiving apparatus based on the IEEE 802.3ba communication method. The alignment and synchronization circuit 1023 distributes received data from line 0 to line (n−1) (n minus 1; n is a positive integer indicating the number of virtual lanes) in units of blocks by 64B / 66B encoding. Accepts parallel input of a series of data blocks.
Here, line 0 to line (n−1) correspond to virtual lane 0 to virtual lane (n−1) in the transmission device on a one-to-one basis. That is, in each of line 0 to line (n−1), a data block transmitted to the virtual lane corresponding to the line among virtual lane 0 to virtual lane (n−1) in the transmission device is the line. Are sent in the same time order as the time order sent to the virtual lane corresponding to. However, the line number of a certain line does not necessarily match the virtual lane number of the virtual lane corresponding to the line. That is, the line order and the virtual lane order are not necessarily the same.
The alignment / synchronization circuit 1023 that has received the input of the data block sequence converts the data block sequence (a series of data blocks arranged in the time direction) transmitted from each of the lines 0 to (n−1) into the arrangement order in the transmission device, That is, the transmission apparatus rearranges the data block sequence in the order of the virtual lane numbers of the virtual lanes. The alignment / synchronization circuit 1023 synchronizes the data block strings.

Specifically, alignment marker detection circuits 1110-0 to 1110-(n−1) receive the received data distributed to the lines and output the received data to the deskew synchronization circuit 1120.
In addition, the alignment marker detection circuits 1110-0 to 1110- (n-1) store in advance the alignment marker determined for each virtual lane in association with the virtual lane number. The alignment marker detection circuits 1110-0 to 1110- (n-1) detect the same block as the alignment marker stored in advance from each block included in the received data received. The alignment marker in the received data is detected.
The alignment marker detection circuits 1110-0 to 1110-(n−1) that have detected the alignment marker in the received data output a synchronization establishment signal indicating that the alignment marker has been detected to the deskew synchronization circuit 1120. . In addition, the alignment marker detection circuits 1110-0 to 1110-(n−1) read out the virtual lane numbers stored in association with the detected alignment markers and output them to the rescue synchronization circuit 1120.

  Next, the rescue synchronization circuit 1120 rearranges the reception data output from the alignment marker detection circuits 1110-0 to 1110- (n-1) in the order of virtual lane numbers. That is, the rescue synchronization circuit 1120 receives the data block string of the line i and the virtual lane number j from the alignment marker detection circuit 1110-i (i is an integer of 0 ≦ i ≦ n−1). The input data block sequence is assigned to virtual lane j.

  Further, the deskew synchronization circuit 1120 is configured such that the data phase difference between the virtual lanes (data is the deskew synchronization circuit 1120) based on the synchronization establishment signal output from the alignment marker detection circuits 1110-0 to 1110- (n-1). ) Is detected. Based on the detected data phase difference, the deskew synchronization circuit 1120 performs phase absorption for storing and delaying previously input data in a buffer, and aligns the data phases of the virtual lanes. Thereby, the rescue synchronization circuit 1120 restores the virtual lane in the transmission device, that is, outputs the reception data in the same order and the same synchronization timing as when the transmission device distributes the communication data to the virtual lane.

"100GE and 40GE PCS and MLD Proposal", [online], January 2008, IEEE802.3ba Task Force, [Search May 25, 2010], Internet <URL: http://www.ieee802.org/3 /ba/public/jan08/gustlin_01_0108.pdf>

However, at least the IEEE 802.3ba communication method disclosed in Non-Patent Document 1 does not disclose a method for detecting an erroneous setting of the alignment marker in the transmitting device, and the receiving device may not be able to detect the erroneous setting appropriately. is there.
For example, in FIG. 7, it is assumed that data of virtual lane 1 is input from line 0 and data of virtual lane 2 is input from line 1. Here, when the alignment marker is erroneously set in the transmission device and the alignment marker indicating the virtual lane 1 is inserted into the virtual lane 2, the deskew synchronization circuit 1120 detects the data input of the virtual lane 2. Can not. Therefore, it is conceivable that the rescue synchronization circuit 1120 waits for data in the virtual lane 2 and discards (times out) the data after a predetermined time has elapsed. As a result, the receiving device cannot correctly decode the received data.

  Here, the alignment synchronization circuit 1023 does not include a means for detecting an incorrect setting of the alignment marker, and cannot determine the cause of the timeout. That is, it cannot be determined whether the timeout is due to an incorrect setting of the alignment marker or due to other causes such as noise contamination during communication. For this reason, it becomes difficult for the user of the receiving apparatus to take a measure for eliminating the timeout, or it takes time to identify the cause and take a measure.

  The present invention has been made in consideration of such circumstances, and its purpose is to misalign alignment markers in data communication performed by distributing data to a plurality of lanes and inserting alignment markers for each lane. An alignment synchronization circuit, a data alignment method, and a program.

  The present invention has been made to solve the above-described problem. An alignment marker duplication determination circuit according to an aspect of the present invention is data that is distributed to a plurality of series and input in parallel, An alignment marker detection circuit for detecting the alignment marker from data including an alignment marker indicating a synchronization timing and an arrangement order of each of the series, and the arrangement order indicated by the alignment marker detected by the alignment marker detection circuit, And an arrangement order duplication determination circuit that outputs a signal indicating duplication of the alignment markers when it is determined that any one of the series is the same.

  An alignment marker duplication determination method according to an aspect of the present invention is an alignment marker duplication judgment method of an alignment marker duplication judgment circuit, in which the alignment marker detection circuit is divided into a plurality of series and input in parallel. An alignment marker detection step for detecting the alignment marker from data including an alignment marker indicating a synchronization timing between the sequences and an arrangement order of each of the sequences, and an arrangement order duplication determination circuit including the alignment marker detection step. An alignment order duplication determination step for outputting a signal indicating duplication of the alignment markers when it is determined that any one of the series is shown to be in the same order by the alignment marker detected in It is characterized by comprising.

A program according to an aspect of the present invention is data that is distributed to a plurality of series and input in parallel to a computer as an alignment marker duplication determination circuit, and includes synchronization timing between the series and each of the series from data including alignment marker indicating the order, and the alignment markers tested des step of detecting the alignment marker by the alignment marker detected by said alignment marker detecting step, either a plurality of the sequences in the same order When it is determined that it is shown, the program for executing an arrangement order overlap determination step for outputting a signal indicating overlap of the alignment markers.

  According to the present invention, it is possible to detect an erroneous setting of an alignment marker in data communication performed by distributing data to a plurality of lanes and inserting an alignment marker for each lane.

1 is a configuration diagram illustrating a schematic configuration of a communication system including an alignment synchronization circuit according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the alignment synchronizing circuit 23 in the embodiment. 2 is a configuration diagram illustrating a schematic configuration of a lane number duplication determination circuit 130 in the same embodiment. FIG. 5 is a timing chart showing an operation of the alignment synchronization circuit 23 when a data block sequence in which alignment markers are correctly set is input in the embodiment. 4 is a timing chart showing an operation of the alignment synchronization circuit 23 when a data block including an erroneously set alignment marker is input in the embodiment. 4 is a configuration diagram illustrating a schematic configuration of an alignment synchronization circuit that outputs virtual lane numbers that are not detected in the embodiment. FIG. It is a figure which shows the example of the alignment synchronizing circuit which aligns and synchronizes the data block transmitted by the communication system of IEEE802.3ba.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram showing a schematic configuration of a communication system including an alignment synchronization circuit according to an embodiment of the present invention.
In FIG. 1, the communication system 1 includes a transmission device 10 and a reception device 20. The transmission device 10 includes a 64B / 66B encoding circuit 11, a virtual lane distribution circuit 12, an alignment marker insertion circuit 13, a physical lane distribution circuit 14, and a transmission circuit 15. The receiving device 20 includes a receiving circuit 21, a line distribution circuit 22, an alignment synchronization circuit (alignment marker duplication determination circuit) 23, a virtual lane combination circuit 24, a 64B / 66B decoding circuit 25, and an alarm display circuit 26. It comprises.

  The communication system 1 is a communication system in which communication target data is distributed over a plurality of lanes and an alignment marker is inserted for each lane for communication. As a communication system that performs such communication, for example, a communication system based on the communication scheme of IEEE802.3ba can be cited. However, the present invention is not limited to a communication system based on the IEEE 802.3ba communication method, but is applied to various communication systems in which communication target data is blocked and distributed to a plurality of lanes, and an alignment marker is inserted for each lane for communication. Applicable. In particular, the present invention can be applied not only to a communication system that inserts alignment markers for each virtual lane, but also to a communication system that inserts alignment markers for each physical lane.

The transmission apparatus 10 transmits input communication target data to the reception apparatus 20 via an n-channel communication path (hereinafter, each channel of the communication path is referred to as a “physical lane”). The 64B / 66B encoding circuit 11 performs 64B / 66B encoding on input communication target data, blocks the data, and outputs the block to the virtual lane distribution circuit 12.
The virtual lane distribution circuit 12 distributes the communication target data blocked by the 64B / 66B encoding circuit 11 to n virtual lanes (series) of virtual lane 0 to virtual lane (n−1), and aligns the alignment marker. Output to the insertion circuit 13.

  The alignment marker insertion circuit 13 inserts an alignment marker into each virtual lane. That is, the alignment marker insertion circuit 13 inserts alignment markers between data blocks at intervals of a predetermined number of blocks with respect to the arrangement of data blocks input for each virtual lane. Here, the alignment marker is a data block inserted to indicate the synchronization timing between virtual lanes. The contents of the alignment marker (value of each bit) are predetermined for each virtual lane, and the alignment marker identifies the virtual lane (indicating a virtual lane number). The alignment marker insertion circuit 13 outputs the arrangement of data blocks including the alignment marker to the physical lane distribution circuit 14 for each virtual lane.

The physical lane distribution circuit 14 includes m (m is a positive integer and a divisor of n) data blocks output from the alignment marker insertion circuit 13 in n (n is a positive integer) virtual lane. Reassign to physical lane. Specifically, the physical lane distribution circuit 14 collects n parallel data in m parallel by, for example, collecting data by time division multiplexing for each n / m (n for m) virtual lanes. Redistribute.
The transmission circuit 15 transmits the data block to the reception device 20 via the m physical lanes based on the distribution of the physical lane distribution circuit 14.

The receiving device 20 restores communication target data based on the data block transmitted from the transmitting device 10. The reception circuit 21 receives a data block transmitted from the transmission device 10 via m physical lanes.
The line distribution circuit 22 distributes the data block received by the reception circuit 21 to n lines of line 0 to line (n−1) in the reverse procedure of the physical lane distribution circuit 14. That is, the line distribution circuit 22 performs processing for separating data for n / m (n for m) virtual lanes grouped on one physical lane for each physical lane. Thus, the arrangement of the data blocks for each virtual lane input to the physical lane distribution circuit 14 is restored.
However, the lines in the line distribution circuit 22 may be arranged in a different order from the virtual lanes input to the physical lane distribution circuit 14. That is, each of the lines 0 to (n−1) corresponds to one virtual lane in the transmission device 10. Each line outputs the data blocks sent to the corresponding virtual lane in the order of time sent to the corresponding virtual lane. However, the line number of a certain line does not necessarily match the virtual lane number of the virtual lane corresponding to the line.

For example, when the physical lane 0 and the physical lane 1 are reversed between the transmission device 10 and the reception device 20, that is, the physical lane 0 of the transmission device 10 is connected to the reception device 20 as the physical lane 1, and the transmission device Let us consider a case where the physical lane 2 is connected to the receiving apparatus 20 as the physical lane 0. In this case, the virtual lane associated with physical lane 0 in the transmission apparatus 10 corresponds to the line associated with physical lane 1 in the reception apparatus 20. That is, data transmitted to the virtual lane associated with physical lane 0 by the transmission apparatus 10 is transmitted to a line associated with physical lane 1 at the reception apparatus 20. Also, the virtual lane associated with physical lane 1 in the transmission apparatus 10 corresponds to the line associated with physical lane 0 in the reception apparatus 20. For this reason, in the transmission apparatus 10, a virtual lane number corresponding to a physical lane having a smaller physical lane number is assigned a smaller virtual lane number, and in the receiving apparatus 20, a line corresponding to a physical lane having a smaller physical lane number is assigned a smaller line number. If attached, the arrangement order of the virtual lanes in the transmission apparatus 10 and the arrangement order of the lines in the reception apparatus 20 are reversed.
The line distribution circuit 22 outputs the restored data block arrangement to the alignment synchronization circuit 23 line by line.

The alignment synchronization circuit 23 detects an alignment marker from the arrangement of the data blocks for each line output from the line distribution circuit 22. When the detected alignment marker overlaps between virtual lanes, the alignment synchronization circuit 23 outputs a signal indicating alignment marker overlap to the alarm display circuit 26. On the other hand, if the detected alignment markers do not overlap, the alignment synchronization circuit 23 determines the arrangement of the data blocks output for each line in the arrangement order of the corresponding virtual lanes of each line based on the detected alignment markers. By rearranging, virtual lanes in the same order as the virtual lanes input to the physical lane distribution circuit 14 of the transmission device 10 are restored.
However, the restored virtual lane may have a data phase difference between the virtual lanes due to a difference in communication speed on the communication path or a difference in processing speed between the transmission circuit 15 and the reception circuit 21. Therefore, the alignment synchronization circuit synchronizes the data blocks between the restored virtual lanes based on the detected alignment marker. The alignment / synchronization circuit 23 outputs the synchronized data block to the virtual lane combination circuit 24 for each virtual lane.

The virtual lane combining circuit 24 outputs the data output from the alignment and synchronization circuit 23 for each virtual lane in the reverse procedure of allocating the communication target data blocked by the virtual lane distribution circuit 12 of the communication device 10 to the virtual lane. Combine blocks. As a result, the virtual lane combination circuit 24 restores the communication target data which is output from the 64B / 66B encoding circuit of the transmission apparatus 10 and is made into 66B blocks before the virtual lane distribution circuit 12 distributes the virtual lanes.
The 64B / 66B decoding circuit 25 performs 64B / 66B decoding on the 66B block communication target data output from the virtual lane combination circuit 24. As a result, the 64B / 66B decoding circuit 25 restores the communication target data before being 64B / 66B encoded, which is input to the transmission device 10.
The alarm display circuit 26 includes display means such as a liquid crystal display. When a signal indicating alignment marker duplication is input from the alignment synchronization circuit 23, the alarm display circuit 26 displays an alignment marker duplication alarm.

FIG. 2 is a configuration diagram showing a schematic configuration of the alignment synchronization circuit 23. In the figure, the alignment synchronization circuit 23 includes an alignment marker detection circuit 110-0 to 110- (n-1) (n is a positive integer indicating the number of virtual lanes), a skew synchronization circuit 120, and a lane number duplication determination circuit. (Arrangement order overlap determination circuit) 130.
When the alignment synchronization circuit 23 acquires the reception data distributed into the lines (sequences) in units of blocks by 64B / 66B encoding, the alignment synchronization circuit 23 arranges the acquired reception data in the order of the virtual lane numbers in the transmission device 10, thereby The virtual lanes in the same order are restored, and the restored virtual lanes are synchronized.

The alignment marker detection circuits 110-0 to 110- (n-1) receive the input of the received data distributed to the lines and output the received data received to the deskew synchronization circuit 120.
Here, the alignment marker detection circuits 110-0 to 110- (n-1) store in advance the alignment marker determined for each virtual lane in association with the virtual lane number. The alignment marker detection circuits 110-0 to 110- (n-1) detect the same block as the alignment marker stored in advance from each block included in the received data received. The alignment marker in the received data is detected. Then, the alignment marker detection circuits 110-0 to 110- (n-1) remove the alignment marker from the received data received, and the remaining data blocks are arranged in the form of a data block sequence for each line. 120 is output.

  The alignment marker detection circuits 110-0 to 110- (n-1) that have detected the alignment marker in the received data output a synchronization establishment signal indicating that the alignment marker has been detected to the rescue synchronization circuit 120. At the same time, the alignment marker detection circuits 110-0 to 110- (n-1) read out the virtual lane numbers stored in association with the detected alignment markers and output them to the rescue synchronization circuit 120.

  The deskew synchronization circuit 120 rearranges the reception data output from the alignment marker detection circuits 110-0 to 110- (n-1) in the order of virtual lane numbers. That is, the rescue synchronization circuit 120 receives the data block string of line i and the virtual lane number j from the alignment marker detection circuit 110-i (i is an integer satisfying 0 ≦ i ≦ n−1). The input data block sequence is assigned to virtual lane j.

  Further, the rescue synchronization circuit 120 detects the data phase difference between the virtual lanes based on the synchronization establishment signal output from the alignment marker detection circuits 110-0 to 110- (n-1). Here, the alignment marker insertion circuit 13 of the transmission device 10 inserts the synchronization establishment signal into each virtual lane at the same timing. Therefore, the shift between the lines of the timing at which the synchronization establishment signal is output from the alignment marker detection circuits 110-0 to 110- (n-1) indicates the data phase difference between the lines. Further, the correspondence between the line and the virtual lane is indicated by a virtual lane number output from the alignment marker detection circuits 110-0 to 110- (n-1). Therefore, the skew synchronization circuit 120 detects the shift between the lines of the timing at which the synchronization establishment signal is output from the alignment marker detection circuits 110-0 to 110- (n-1), so that the data level between the lines is detected. Detect phase difference. Then, the rescue synchronization circuit 120 determines the data phase difference between the detected lines based on the virtual lane numbers output from the alignment marker detection circuits 110-0 to 110- (n-1). By replacing with a phase difference, a data phase difference between virtual lanes is detected.

Based on the detected data phase difference between the virtual lanes, the deskew synchronization circuit 120 performs phase absorption for storing and delaying the previously input data in a buffer (Buffer), and the data phase of each virtual lane is determined. Align. Accordingly, the rescue synchronization circuit 120 restores the virtual lane output from the virtual lane distribution circuit 12 of the transmission device 10. In other words, the rescue synchronization circuit 120 outputs received data in the same order and the same synchronization timing as when the virtual lane distribution circuit 12 distributes communication data to virtual lanes.
When the lane number duplication determination circuit 130 determines that the virtual lane numbers output from the alignment marker detection circuits 110-0 to 110- (n-1) are the same in any of the virtual lanes, the alignment marker And a signal indicating alignment marker duplication is output to the alarm display circuit 26.

FIG. 3 is a configuration diagram showing a schematic configuration of the lane number duplication determination circuit 130.
In the figure, a lane number duplication determination circuit 130 includes an AND circuit 131 and a lane number comparison circuit 132.
The lane number duplication determination circuit 130 determines the presence or absence of duplication of virtual lane numbers based on the virtual lane numbers output from the alignment marker detection circuits 110-0 to 110- (n-1).
The AND circuit 131 takes an AND (logical product) of the synchronization establishment signals output from the alignment marker detection circuits 110-0 to 110-(n−1), and outputs the calculation result to the lane number comparison circuit 132.
When the calculation result output from the AND circuit 131 is “1”, the lane number comparison circuit 132 detects that the alignment marker detection circuits 110-0 to 110- (n−1) all detect the alignment marker. If the virtual lane numbers output from the alignment marker detection circuits 110-0 to 110- (n-1) are the same for any of the lines 0 to (n-1), it is determined. When it is determined that the virtual lane number is the same for any one of the lines 0 to (n−1), the lane number comparison circuit 132 outputs a signal indicating alignment marker duplication.

Next, the operation of the alignment synchronization circuit 23 will be described with reference to FIG. 4 and FIG.
FIG. 4 is a timing chart showing the operation of the alignment synchronization circuit 23 when a data block sequence in which alignment markers are correctly set is input.
This figure shows an example in the case of n = 4. Line 0 corresponds to virtual lane 1, line 1 corresponds to virtual lane 2, line 2 corresponds to virtual lane 3, and line 3 is virtual. This corresponds to lane 0. In addition, the horizontal axis of FIG.

The alignment marker detection circuit 110-0 indicates the same virtual lane number “1” and continues (that is, there is no alignment marker indicating another virtual lane number between the two alignment markers). After time t4 when reading a and a04, a synchronization establishment signal indicating that the alignment marker has been detected and the detected virtual lane number “1” are output to the lane number duplication determination circuit 130.
Then, after reading out two consecutive alignment markers indicating the same virtual lane number “1”, the alignment marker detection circuit 110-0 tries to detect the alignment markers at the same interval, and detects the alignment markers a05 and a06. To do.

In this way, the alignment marker detection circuit detects an alignment marker by reading two consecutive alignment markers that indicate the same virtual lane number from the line, and detects that the alignment marker has been detected after the time when the alignment marker is detected. The synchronization establishment signal shown and the detected virtual lane number are output to the lane number duplication determination circuit 130.
Then, after detecting the alignment marker, the alignment marker detection circuit tries to detect the alignment marker at the same intervals as the two alignment markers. When an alignment marker having the same virtual lane number as the detected alignment marker is read, the alignment marker detection circuit continues to output the synchronization establishment signal to the lane number duplication determination circuit 130 and the detected virtual lane number. On the other hand, when the alignment marker indicating the same virtual lane number as the detected alignment marker cannot be read, the alignment marker detection circuit outputs the synchronization establishment signal to the lane number duplication determination circuit 130 and the detected virtual lane number. Exit.

Here, the alignment marker detection circuit 110-0 does not read the alignment marker from the position indicated by the symbol a02. As described above, the case where the alignment marker is not read may be a case where the alignment marker is not transmitted because communication is suspended, or a case where reading of the alignment marker from the received signal fails due to noise mixing or the like. Similarly, the alignment markers 110-2 and 110-3 do not read the alignment marker at the position of the reference sign a26 and the position of the reference sign a31, respectively.
Further, the alignment marker detection circuit 110-0 reads the alignment marker indicating the virtual lane number “3” from the alignment marker a01. That is, the alignment marker detection circuit 110-0 acquires virtual lane numbers that are different from each other at the position of the code a01 and the positions of the codes a03 to a06. As described above, when the alignment marker detection circuit acquires different virtual lane numbers on the same line, the transmission apparatus 10 may change the correspondence relationship between the virtual lane and the physical lane for each session or every predetermined time. Conceivable.

In addition, after time t1 when the alignment marker detection circuit 110-1 reads the two consecutive alignment markers a11 and a12 indicating the same virtual lane number “2”, and the detected virtual lane number “2”. Is output to the lane number duplication determination circuit 130.
Also, the alignment marker detection circuit 110-2 cannot read the alignment marker indicating the virtual lane number from the time t2 when the two consecutive alignment markers a21 and a22 indicating the same virtual lane number “3” are read. Until then, the synchronization establishment signal and the detected virtual lane number “3” are output to the lane number duplication determination circuit 130.

The lane number duplication determination circuit 130 outputs synchronization establishment signals from all of the alignment marker detection circuits 110-0 to 110-3 (that is, outputs a signal indicating that alignment markers have been detected in all virtual lanes). And when it is determined that the virtual lane number is the same in any of the plurality of lines, it is determined that there is an alignment marker duplication error, and a signal indicating alignment marker duplication is output to the alarm display circuit 26.
In the example of FIG. 4, the virtual lane number is different for each alignment marker at times t4 to t5 when the synchronization establishment signals are output from all of the alignment marker detection circuits 110-0 to 110-3. The determination circuit 130 does not output a signal indicating alignment marker duplication.

FIG. 5 is a timing chart showing the operation of the alignment synchronization circuit 23 when a data block including an erroneously set alignment marker is input.
As in the case of FIG. 4, this figure shows an example of n = 4, where line 0 corresponds to virtual lane 1, line 1 corresponds to virtual lane 2, and line 2 corresponds to virtual lane 3. Correspondingly, line 3 corresponds to virtual lane 0. In addition, the horizontal axis of FIG.

In FIG. 5, the alignment markers included in each of line 0, line 2, and line 3 are the same as those in FIG.
On the other hand, in FIG. 5, alignment markers a111 to a116 included in the line 1 indicate the virtual lane number “1”. FIG. 5 is different from FIG. In FIG. 5, alignment markers indicating the same virtual lane number “1” are inserted in line 0 and line 1. As described above, when the virtual lane number is duplicated, the alignment marker inserted by the alignment marker insertion circuit of the transmission apparatus 10 is erroneously set, and thereby the same alignment marker is inserted into a plurality of virtual lanes. It may be possible. In the example of FIG. 5, the alignment marker inserted into the virtual lane 2 by the alignment marker insertion circuit is erroneously set. As a result, the alignment marker inserted into the virtual lane 1 and the alignment marker inserted into the virtual lane 2 are It is conceivable that the same alignment marker (alignment marker indicating the virtual lane number “1”) is set.

  Since the alignment markers a111 to a116 included in the line 1 indicate the virtual lane number “1”, unlike the case of FIG. 4, the alignment marker detection circuit 110-1 uses the virtual lane number “1” as the lane number comparison circuit. It outputs to 132. On the other hand, signals output from the alignment marker detection circuits 110-0, 110-2, and 110-3 to the lane number comparison circuit 132 are the same as those in FIG.

  As described above, in the example of FIG. 5, the virtual output from the alignment marker detection circuit 110-0 at the times t 4 to t 5 when the synchronization establishment signals are output from all of the alignment marker detection circuits 110-0 to 110-3. The lane number and the virtual lane number output from the alignment marker 110-1 are both “1” and the same. Accordingly, the lane number duplication determination circuit 130 determines that there is an alignment marker duplication error and outputs a signal indicating alignment marker duplication to the alarm display circuit 26.

Here, the transmission apparatus 10 does not output a signal indicating overlapping alignment markers except for the case where synchronization establishment signals are output from all of the alignment marker detection circuits 110-0 to 110-3. Alternatively, when the correspondence relationship between the virtual lane and the physical lane is changed at regular intervals, it is possible to prevent as much as possible from erroneously determining that there is an alignment marker duplication error.
For example, in FIG. 4, the virtual lane number “3” indicated by the alignment marker a01 is the number of the previous session, and the alignment marker detection circuit 110-0 assigns the virtual lane number “3” to the lane number until the time indicated by a02. Assume that the data is output to the duplication determination circuit 130. An alignment marker indicating the virtual lane number “3” exists immediately before the alignment marker a21, and the alignment marker detection circuit 3 sends the virtual lane number “3” to the lane number duplication determination circuit 130 from the time of the alignment marker a21. Assume that it is outputting. Here, if the lane number duplication determination circuit 130 outputs the alignment marker duplication signal when the virtual lane number is the same for a plurality of lines regardless of the synchronization establishment signal, the virtual lane number duplication is performed for the line 0 and the line 2. Since both lane numbers are “3”, the lane number duplication determination circuit 130 outputs an alignment marker duplication signal. Therefore, it is merely a session boundary, and it is determined that there is an alignment marker duplication error even when an incorrect alignment marker is not set.

  On the other hand, since the alignment marker detection circuit 110-3 does not detect the alignment marker at the position indicated by reference sign a31 in FIG. 4, no synchronization establishment signal is output from the time indicated by reference sign a31 to the time indicated by reference sign a33. Therefore, by preventing the lane number duplication determination circuit 130 from outputting a signal indicating alignment marker duplication unless the synchronization establishment signal is output from all of the alignment marker detection circuits 110-0 to 110-3. It can be avoided that there is an alignment marker duplication error.

  Note that a method for preventing the transmission apparatus 10 from erroneously determining that there is an alignment marker duplication error when changing the correspondence between the virtual lane and the physical lane is limited to the method using the synchronization establishment signal described above. Absent. For example, only when the lane number comparison circuit 132 (FIG. 3) continues to determine that the virtual lane number is the same for a plurality of lines for a predetermined time or longer, it is determined that there is an alignment marker duplication error and there is an alignment marker duplication. May be output. In this case, the lane number duplication determination circuit 130 does not need to include the AND circuit 131, and the circuit configuration can be simplified.

As described above, the alignment marker detection circuits 110-0 to 110- (n-1) detect the alignment markers included in the line. When it is determined that the virtual lane number indicated by the detected alignment marker is the same in a plurality of lines, the lane number duplication determination circuit 130 determines that there is an alignment marker duplication error and alerts the alignment marker duplication signal. Output to the display circuit 26.
As described above, the alignment synchronization circuit 23 can detect an erroneous setting of the alignment marker by determining whether the virtual lane number is the same in any of a plurality of lines.

When the alignment marker detection circuits 110-1 to 110-(n−1) detect the alignment marker, the alignment marker detection circuits 110-1 to 110-(n−1) output a synchronization establishment signal and a virtual lane number to the lane number duplication determination circuit 130. Then, the lane number duplication determination circuit 130 determines that the synchronization establishment signals are output from all of the alignment marker detection circuits 110-1 to 110- (n-1) and that the virtual lane numbers are the same in a plurality of lines. Then, it is determined that there is an alignment marker duplication error, and an alignment marker duplication signal is output to the alarm display circuit 26.
As described above, the transmission apparatus is configured such that signals indicating alignment marker duplication are not output except when the synchronization establishment signals are output from all of the alignment marker detection circuits 110-0 to 110- (n-1). 10 can reduce the possibility of erroneously determining that there is an alignment marker duplication error when the correspondence relationship between the virtual lane and the physical lane is changed for each session or every fixed time.

  The alignment marker duplication signal output from the alignment synchronization circuit 23 is not limited to a signal indicating only that there is an alignment marker duplication. For example, the lane number duplication determination circuit 130 (FIG. 2) may output the virtual lane number determined to be the same. Thereby, the user of the receiving device 20 can specify the alignment marker that has been set in duplicate, and when correcting the erroneous setting of the transmitting device 10, it can be expected that the erroneous setting location can be specified quickly.

Alternatively, the alignment synchronization circuit may output a virtual lane number that has not been detected.
FIG. 6 is a configuration diagram illustrating a schematic configuration of an alignment synchronization circuit that outputs virtual lane numbers that are not detected. In the figure, an alignment synchronization circuit (alignment marker duplication determination circuit) 523 includes an alignment marker detection circuit 110-0 to 110- (n-1), a deskew synchronization circuit 120, a lane number duplication determination circuit 130, and a lack. Lane number detection circuit (missing arrangement order detection circuit) 640. In the same figure, the same reference numerals (110-0 to 110- (n-1), 120, 130) are assigned to the parts having the same functions corresponding to the respective parts in FIG.

The missing lane number detection circuit 640 stores a predetermined virtual lane number, and when an alignment marker duplication signal is input from the lane number duplication determination circuit 130, the alignment marker detection circuits 110-0 to 110- (n Based on the virtual lane number output in -1), the missing virtual lane number (virtual lane number not indicated by the alignment marker) is detected and output to the alarm display circuit 26.
For example, when the virtual lane numbers “1”, “1”, “3”, and “0” described in FIG. 5 are output from the alignment marker detection circuit, the missing lane number detection circuit 640 stores in advance. Of the virtual lane numbers “0”, “1”, “2”, “3”, it is detected that the virtual lane number “2” has not been input, and this virtual lane number “2” is displayed as an alarm display circuit 26. Output to.

Thus, the missing lane number detection circuit 640 detects the missing virtual lane number, so that the user of the receiving device 20 can specify the missing virtual lane, and the transmission device 10 is erroneously set. When correcting the error, it can be expected that the erroneous setting location can be identified quickly.
In addition, when the alignment marker duplication signal is input from the lane number duplication determination circuit 130, the missing lane number detection circuit 640 detects a virtual lane number that is not indicated by the alignment marker. The missing virtual lane number can be detected without waiting for timeout without being input any more. Therefore, the user of the receiving device 20 can quickly recognize that the alignment marker is set incorrectly and the missing virtual lane number.

A program for realizing all or part of the functions of the alignment / synchronization circuit 23 and the alignment / synchronization circuit 523 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system. The processing of each unit may be performed by executing. Here, the “computer system” includes an OS and hardware such as peripheral devices.
Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used.
The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Furthermore, the “computer-readable recording medium” dynamically holds a program for a short time like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, a volatile memory in a computer system serving as a server or a client in that case, and a program that holds a program for a certain period of time are also included. The program may be a program for realizing a part of the functions described above, and may be a program capable of realizing the functions described above in combination with a program already recorded in a computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design changes and the like without departing from the gist of the present invention.

  The present invention is suitable for use in an alignment marker duplication determination circuit, an alignment marker duplication determination method, and a program in data communication performed by distributing data to a plurality of lanes and inserting an alignment marker for each lane.

DESCRIPTION OF SYMBOLS 1 Communication system 10 Transmission apparatus 11 64B / 66B encoding circuit 12 Virtual lane distribution circuit 13 Alignment marker insertion circuit 14 Physical lane distribution circuit 15 Transmission circuit 20 Reception apparatus 21 Reception circuit 22 Line distribution circuit 23, 523 Alignment synchronization circuit 24 virtual lane combination circuit 25 64B / 66B decoding circuit 26 alarm display circuit 110-0 to 110- (n-1) alignment marker detection circuit 120 deskew synchronization circuit 130 lane number duplication determination circuit 131 AND circuit 132 lane number comparison circuit 640 Missing lane number detection circuit

Claims (6)

An alignment marker detection circuit for detecting the alignment marker from data distributed to a plurality of series and input in parallel, the data including an alignment marker indicating a synchronization timing between the series and an arrangement order of each of the series When,
Arrangement order duplication determination that outputs a signal indicating duplication of the alignment markers when it is judged that the arrangement order indicated by the alignment markers detected by the alignment marker detection circuit is the same in any one of the series Circuit,
An alignment marker duplication determination circuit comprising: When the alignment marker detection circuit detects the alignment marker in any of the series, a signal indicating that the alignment marker has been detected in the series, and an arrangement order of the series indicated by the detected alignment marker, The arrangement order overlap determination circuit outputs a signal indicating that the alignment marker is detected in all the sequences from the alignment marker detection circuit, and the sequence order overlap determination circuit outputs the sequence order overlap determination circuit. The alignment marker duplication determination circuit according to claim 1, wherein a signal indicating duplication of the alignment markers is output when it is determined that the arrangement order is the same for any one of the series.   The alignment marker duplication according to claim 1, wherein the arrangement order duplication determination circuit outputs a number indicating the same arrangement order in the plurality of series as a signal indicating duplication of the alignment markers. Judgment circuit.   When the arrangement order duplication determination circuit determines that there is a duplication error of the alignment marker, the arrangement order duplication determination circuit further includes a missing arrangement order detection circuit that detects an arrangement order that is not indicated by the alignment marker in a predetermined arrangement order. The alignment marker duplication determination circuit according to claim 1 or 2, characterized in that: An alignment marker overlap determination method of an alignment marker overlap determination circuit,
An alignment marker detection circuit is data that is distributed to a plurality of series and input in parallel, and the alignment marker is extracted from data including an alignment marker that indicates a synchronization timing between the series and an arrangement order of each of the series. An alignment marker detection step to detect,
When the alignment order duplication determination circuit determines that the alignment markers detected in the alignment marker detection step indicate that any one of the series is in the same arrangement order, the alignment marker overlap A sequence order duplication determination step for outputting a signal indicating
An alignment marker duplication determination method comprising: To computer as alignment marker duplication judgment circuit,
A data input in parallel are distributed to a plurality of streams, the data including alignment marker indicating the order of each of the synchronization timing and the sequence between the sequences, out alignment marker detection to detect the alignment markers Graphics and steps,
An array that outputs a signal indicating an overlap of the alignment markers when it is determined by the alignment marker detected in the alignment marker detection step that any one of the series is in the same arrangement order An order overlap determination step;
A program for running

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