JP5545176B2 - Amplifier phase compensation circuit and amplifier circuit - Google Patents

Description

  The present invention relates to an amplifier phase compensation circuit and an amplifier circuit.

  FIG. 1A is a diagram illustrating the amplifier 101, and FIG. 1B is a diagram illustrating the phase characteristics of the amplifier 101. The amplifier 101 amplifies the signal at the input terminal 102 and outputs it to the output terminal 103. The phase characteristic in FIG. 1B shows a differential value of the phase with respect to the output power. The differential value of the phase is a differential value of the phase of the output signal with respect to the input signal. The phase characteristic has a linear operation region 111 and nonlinear operation regions 112 and 113. A region 112 is a non-linear operation region having a convex portion characteristic, and a region 113 is a non-linear operation region having a concave portion characteristic.

  In general, the amplifier 101 used in the wireless communication device is required to linearly amplify the amplitude without changing the phase of the input signal. However, in the amplifier 101 using a semiconductor element, as the input signal power increases, a phenomenon in which the phase of the output signal rotates (phase distortion characteristics) appears, and nonlinear operation regions 112 and 113 are generated. Since the phase distortion distorts the output signal of the amplifier 101, the output spectrum causes a problem of protruding a mask defined by the wireless standard. Further, communication using a phase modulation method or the like causes a communication error. For this reason, there is a demand for eliminating the nonlinear operation regions 112 and 113 and ensuring a flat linear operation region even when the output power is high.

  FIG. 2 is a diagram illustrating a phase compensation circuit 201 that compensates for the phase of the amplifier 101. The phase compensation circuit 201 is connected between the input terminal 102 and the input terminal of the amplifier 101. The phase compensation circuit 201 generates distortion (predistortion) that is an inverse characteristic of the phase distortion generated by the amplifier 101 itself, and inputs the distortion to the input terminal of the amplifier 101, thereby canceling the phase distortion of the output of the amplifier 101. .

3A to 3C are diagrams for explaining the phase compensation of the phase compensation circuit 201. FIG. FIG. 3A is a diagram illustrating a configuration example of the phase compensation circuit 201. The phase compensation circuit 201 includes a p-channel field effect transistor 301. p-channel field effect transistor 301 has a gate connected to the input terminal of the amplifier 101, and a source and a drain connected to the reference potential node. The amplifier 101 amplifies the signal 202 at the input terminal 102 and outputs it to the output terminal 103.

FIG. 3B shows the characteristics of the p-channel field effect transistor 301. The horizontal axis represents the gate-source voltage Vgs of the transistor 301, and the vertical axis represents the gate-source capacitance Cgs of the transistor 301. p-channel field-effect transistor 30 1 is shown with respect to an increase in the gate and source voltage Vgs, the characteristics of the gate and the source capacitance Cgs is reduced. When increasing the power of input signal 202 to the transistor 30 1, to come raised bias of the gate of the transistor 30 1, the gate and source capacitance Cgs is reduced. Since the passage phase of the signal 202 is advanced by the decrease in the gate-source capacitance Cgs, the phase delay generated in the amplifier 101 itself can be compensated.

  FIG. 3C shows the phase characteristic 311 of the amplifier 101 and the phase characteristic 312 of the phase compensation circuit 201 similar to those in FIG. The phase compensation circuit 201 compensates for a phase delay (a component increasing with respect to the reference) generated in the region 112 (FIG. 1B) near the medium power in the phase characteristic 311 of the amplifier 101. A distortion phase characteristic 312 which is the reverse characteristic is generated. Thereby, the distortion of the phase characteristic 311 of the amplifier 101 can be reduced.

  However, the phase compensation circuit 201 has the following two problems. First, since the level of the input signal 202 is small, the modulation width 302 of the gate-source capacitance Cgs is small, and a phase advance sufficient to compensate for the phase delay of the amplifier 101 cannot be generated. Second, it is difficult to match the peak of the phase characteristic 312 by the phase compensation circuit 201 with the peak (target output power) of the phase characteristic 311 of the amplifier 101.

  Further, there is known a predistortion type amplifier that compensates for distortion generated in the amplifier when the modulated wave signal is amplified by the amplifier based on the envelope information of the modulated wave signal.

  Further, it comprises a cascade circuit of a phase modulator and an amplitude modulator, a first function generator, a second function generator, and an envelope detector, and has an inverse characteristic of a non-linear circuit having no delay characteristic, A predistorter that removes nonlinear distortion of an output signal of a nonlinear circuit by being inserted on the input side in a transmission system including the nonlinear circuit is known.

  Also, an amplifier that amplifies the modulated wave, a detector that detects the output of the amplifier, a comparator that detects an envelope error by comparing the envelope of the detector output and the envelope reference signal, and the envelope error signal and the envelope reference There is known a linear amplifier having an adder for calculating a sum with a signal and supplying the output of the adder as a power source to the amplifier.

  In addition, in the amplitude phase change device for changing the amplitude and phase of the signal, a distribution means for distributing the signal into a plurality of signals, a phase shift means for changing the phase of each of the distribution signals, and the plurality of distributions whose phases have been changed. There is known an amplitude phase change device including a signal synthesizing signal and a synthesizing unit that obtains a combined signal having an amplitude change amount and a phase change amount according to the phase change amount of each distribution signal by the phase shift means. .

JP 2002-223129 A JP 56-66909 A Japanese Patent Laid-Open No. 5-175771 JP 2001-326541 A

  An object of the present invention is to provide an amplifier phase compensation circuit and an amplifier circuit capable of improving the phase compensation accuracy of the amplifier.

  The phase compensation circuit of the amplifier includes a first capacitor connected between an input terminal and a first node, a second capacitor connected between the first node and the input terminal of the first amplifier, and a gate. Is connected to the first node, the source and drain are connected to the first potential node, an envelope detection circuit for detecting the envelope of the signal at the input terminal, and the envelope detection circuit And a second amplifier for amplifying the envelope detected by the step and outputting to the first node.

  By amplifying the envelope of the input signal, the phase distortion of the first amplifier can be compensated with high accuracy.

FIG. 1A is a diagram illustrating an amplifier, and FIG. 1B is a diagram illustrating phase characteristics of the amplifier. It is a figure which shows the phase compensation circuit which compensates the phase of an amplifier. 3A to 3C are diagrams for explaining phase compensation of the phase compensation circuit. 4A and 4B are diagrams for explaining the amplifier circuit having the phase compensation circuit of the amplifier according to the first embodiment. 5A and 5B are diagrams showing simulation results of the circuit of FIG. 6A and 6B are diagrams for explaining an amplifier circuit having a phase compensation circuit of an amplifier according to the second embodiment. 7A and 7B are diagrams illustrating simulation results of the circuit of FIG. It is a circuit diagram which shows the structural example of the amplifier circuit which has the phase compensation circuit of the amplifier by 3rd Embodiment. It is a figure which shows the simulation result of the circuit of FIG. It is a figure which shows the phase characteristic of a 1st amplifier. It is a circuit diagram which shows the structural example of the amplifier circuit which has the phase compensation circuit of the amplifier by 4th Embodiment.

(First embodiment)
FIGS. 4A and 4B are diagrams for explaining an amplifier circuit having a phase compensation circuit for an amplifier according to the first embodiment. FIG. 4A is a circuit diagram showing a configuration example of an amplifier circuit having a phase compensation circuit for an amplifier according to the first embodiment. A phase compensation circuit is connected in front of the first amplifier 401. The phase compensation circuit includes a first capacitor 404, a second capacitor 405, a first field effect transistor 406, a third capacitor 407, a detector 411, a low-pass filter (low-pass filter) 412, and a second amplifier 413. , And a resistor 414 to compensate the phase of the first amplifier 401.

A modulated wave input signal 421 is input to the input terminal 402. The first capacitor 404 is connected between the input terminal 402 and the first node N1. The second capacitor 405 is connected between the first node N 1 and the input terminal of the first amplifier 401. The first field-effect transistor 406 is a p-channel field effect transistor, a gate connected to the first node N1, a source and a drain connected to a first potential node Vr. The third capacitor 407 is connected between the first potential node Vr and the reference potential node (ground potential node). The first potential supplied to the first potential node Vr is a DC bias potential that can be variably controlled.

  The envelope (envelope) detection circuit includes a detector 411 and a low-pass filter 412, and detects the envelope 422 of the signal 421 at the input terminal 402. The second amplifier 413 is a variable gain amplifier capable of controlling the gain, amplifies the envelope 422 detected by the envelope detection circuit, and outputs the amplified envelope 423 to the first node N1 via the resistor 414. The detector 411 detects the signal 421 at the input terminal 402 by rectifying it with a diode. The low pass filter 412 attenuates the high frequency component of the output signal of the detector 411, passes the low frequency component, and outputs the envelope 422 to the second amplifier 413. The first amplifier 401 amplifies the signal input from the first node N 1 via the second capacitor 405 and outputs the amplified signal to the output terminal 403.

4 (B) is a diagram showing characteristics of the first field effect transistor 40 6. The horizontal axis represents the gate-source voltage Vgs of the transistor 406, and the vertical axis represents the gate-source capacitance Cgs of the transistor 406. p-channel field effect transistor 40. 6 shows relative increase in the gate and source voltage Vgs, the characteristics of the gate and the source capacitance Cgs is reduced. When the power of the input envelope 423 to the transistor 406 increases, the gate bias of the transistor 406 increases, so that the gate-source capacitance Cgs decreases. Since the passage phase of the signal 421 is advanced due to the decrease in the gate-source capacitance Cgs, the phase delay generated in the first amplifier 401 itself can be compensated.

  Since the amplitude of the envelope 422 of the input signal 421 is small, the modulation width of the gate-source capacitance Cgs is small. On the other hand, the modulation width of the gate-source capacitance Cgs can be increased by inputting the amplified envelope 423 to the gate of the transistor 406 as in this embodiment. The second amplifier 413 can control the gain by controlling the amplitude of the envelope 423 and controlling the modulation of the capacitor Cgs. That is, the second amplifier 413 can compensate the phase of the nonlinear operation region 112 by amplifying with a gain corresponding to the phase differential value of the nonlinear operation region 112 in FIG.

  Further, by adjusting the first potential of the first potential node Vr, the capacitance Cgs can be modulated even with the power of the small input signal 421, and the peak position of the nonlinear operation region 112 in FIG. Can be controlled.

As described above, this embodiment performs phase compensation by envelope detection. First, the input signal 421 is detected by the detector 411 and the envelope 422 is detected. The second amplifier 413 amplifies the envelope 422 and outputs it to the transistor 406. At this time, by increasing the gain of the second amplifier 413, the amplitude of the envelope 423 can be increased so that the modulation of the capacitance Cgs of the transistor 406 is increased. Further, by controlling the fixed bias potential of the first potential node Vr, the level of the bias voltage Vgs at which the capacitor Cgs is modulated can be freely controlled. Thereby, it is possible to control the input power to which the phase modulation is applied.

5A and 5B are diagrams showing simulation results of the circuit of FIG. 4A, in which the differential value of the phase on the vertical axis is plotted against the input power on the horizontal axis. Phase compensation circuit by using a p-channel field effect transistor 40 6, it is possible to generate a phase characteristic having a recess.

  FIG. 5A shows phase characteristics when the first potential of the first potential node Vr is changed. A characteristic 501 is a characteristic when the first potential of the first potential node Vr is increased, and the peak position of the phase characteristic can be set on the left side (side with a small input power). The characteristic 502 is a characteristic when the first potential of the first potential node Vr is lowered, and the peak position of the phase characteristic can be set on the right side (the side with higher input power). In this way, the peak position of the phase characteristic can be set by controlling the first potential of the first potential node Vr.

  FIG. 5B shows phase characteristics when the gain of the second amplifier 413 is changed. A characteristic 511 is a characteristic when the gain of the second amplifier 413 is reduced, and the modulation width (vibration width) of the phase characteristic can be set small. A characteristic 512 is a characteristic when the gain of the second amplifier 413 is increased, and the modulation width of the phase characteristic can be set large. Thus, by controlling the gain of the second amplifier 413, the modulation width (phase compensation amount) of the phase characteristic can be set.

  According to the present embodiment, the phase of the nonlinear operating region 112 in FIG. 1B is compensated with high accuracy by controlling the first potential of the first potential node Vr and the gain of the second amplifier 413. , Phase distortion can be reduced.

(Second Embodiment)
FIGS. 6A and 6B are diagrams for explaining an amplifier circuit having a phase compensation circuit for an amplifier according to the second embodiment. FIG. 6A is a circuit diagram showing a configuration example of an amplifier circuit having a phase compensation circuit for an amplifier according to the second embodiment. The circuit of the second embodiment (FIG. 6A) is different from the circuit of the first embodiment (FIG. 4A) in that an n-channel field effect transistor 606 is used instead of the p-channel field effect transistor 406. It is provided. Hereinafter, the points of the present embodiment different from the first embodiment will be described. The first field effect transistor 606 is an n-channel field effect transistor, and has a gate connected to the first node N1, and a source and a drain connected to the first potential node Vr.

FIG. 6B is a diagram showing the characteristics of the n-channel field effect transistor 606. The horizontal axis represents the gate-source voltage Vgs of the transistor 606, and the vertical axis represents the gate-source capacitance Cgs of the transistor 606. The characteristic shown in FIG. 6B is opposite to the characteristic shown in FIG. n-channel field effect transistor 60. 6 shows relative increase in the gate and source voltage Vgs, the characteristics of the gate and the source capacitance Cgs is increased. When increasing the power of the input envelope 423 to the transistor 60 6, to come raised bias of the gate of the transistor 60 6, the gate and source capacitance Cgs is increased. Since the passage phase of the signal 421 is delayed due to the increase in the gate-source capacitance Cgs, the phase advance generated in the first amplifier 401 itself can be compensated.

  The second amplifier 413 can compensate the phase of the nonlinear operation region 113 by performing amplification with a gain corresponding to the phase differential value of the nonlinear operation region 113 of FIG. Further, by adjusting the first potential of the first potential node Vr, the capacitance Cgs can be modulated even with the power of the small input signal 421, and the peak position of the nonlinear operation region 113 in FIG. Can be controlled.

FIGS. 7A and 7B are diagrams showing simulation results of the circuit of FIG. 6A, in which the differential value of the phase on the vertical axis is plotted against the input power on the horizontal axis. Phase compensation circuit, by using the n-channel field effect transistor 60 6, it is possible to generate a phase characteristic having a convex portion.

  FIG. 7A shows the phase characteristics when the first potential of the first potential node Vr is changed. A characteristic 701 is a characteristic when the first potential of the first potential node Vr is increased, and the peak position of the phase characteristic can be set to the left side (the side where the input power is small). The characteristic 702 is a characteristic when the first potential of the first potential node Vr is lowered, and the peak position of the phase characteristic can be set on the right side (the side with higher input power). In this way, the peak position of the phase characteristic can be set by controlling the first potential of the first potential node Vr.

  FIG. 7B shows phase characteristics when the gain of the second amplifier 413 is changed. A characteristic 712 is a characteristic when the gain of the second amplifier 413 is reduced, and the modulation width (vibration width) of the phase characteristic can be set small. A characteristic 711 is a characteristic when the gain of the second amplifier 413 is increased, and the modulation width of the phase characteristic can be set large. Thus, by controlling the gain of the second amplifier 413, the modulation width (phase compensation amount) of the phase characteristic can be set.

  According to the present embodiment, by controlling the first potential of the first potential node Vr and the gain of the second amplifier 413, the phase of the nonlinear operation region 113 in FIG. , Phase distortion can be reduced.

(Third embodiment)
FIG. 8 is a circuit diagram showing a configuration example of an amplifier circuit having a phase compensation circuit for an amplifier according to the third embodiment. This embodiment is a combination of the first embodiment and the second embodiment. A phase compensation circuit is connected in front of the first amplifier 401. The phase compensation circuit includes a first capacitor 404, a second capacitor 405, a fourth capacitor 801, field effect transistors 406a to 406d, capacitors 407a to 407c, a detector 411, a low-pass filter (low-pass filter) 412, and an amplifier. 413a to 413d, resistors 414a to 414d, and switches 802a to 802d, which compensate the phase of the first amplifier 401.

  The first capacitor 404 is connected between the input terminal 402 and the first node N1. The second capacitor 405 is connected between the first node N1 and the second node N2. The fourth capacitor 801 is connected between the second node N 2 and the input terminal of the first amplifier 401.

The first field-effect transistor 406a is an n-channel field-effect transistor, a gate connected to the first node N1 through the switch 802a, a source and a drain connected to a first potential node Vrn1. The third capacitor 407a is connected between the first potential node Vrn1 and the reference potential node. The first potential supplied to the first potential node Vrn1 is a DC bias potential that can be variably controlled.

The first field-effect transistor 406b, which is an n-channel field effect transistor, a gate connected to the first node N1 through the switch 802b, a source and a drain connected to the potential node Vrn2. The capacitor 407b is connected between the potential node Vrn2 and the reference potential node. The potential supplied to the potential node Vrn2 is a DC bias potential that can be variably controlled.

The second field effect transistor 406c are p-channel field effect transistor, a gate connected to the second node N2 via a switch 802c, a source and a drain connected to the second potential node Vrp1. The fifth capacitor 407c is connected between the second potential node Vrp1 and the reference potential node. The second potential supplied to the second potential node Vrp1 is a DC bias potential that can be variably controlled.

The second field effect transistor 406d are p-channel field effect transistor, a gate connected to the second node N2 via a switch 802d, a source and a drain connected to the potential node VRP2. The capacitor 407d is connected between the potential node Vrp2 and the reference potential node. The potential supplied to the potential node Vrp2 is a DC bias potential that can be variably controlled.

  The envelope detection circuit includes a detector 411 and a low-pass filter 412 as in the first and second embodiments, and detects the envelope of the signal at the input terminal 402.

  The second amplifier 413a is a variable gain amplifier capable of controlling the gain, amplifies the envelope detected by the envelope detection circuit, and outputs the amplified envelope to the first node N1 via the resistor 414a.

  The amplifier 413b is a variable gain amplifier capable of controlling the gain, amplifies the envelope detected by the envelope detection circuit, and outputs the amplified envelope to the first node N1 via the resistor 414b.

  The third amplifier 413c is a variable gain amplifier capable of controlling the gain, amplifies the envelope detected by the envelope detection circuit, and outputs the amplified envelope to the second node N2 via the resistor 414c.

  The amplifier 413d is a variable gain amplifier capable of controlling the gain, amplifies the envelope detected by the envelope detection circuit, and outputs the amplified envelope to the second node N2 via the resistor 414d.

  The first amplifier 401 amplifies signals input from the first node N1 and the second node N2 via the fourth capacitor 801, and outputs the amplified signal to the output terminal 403.

  The first field effect transistors 406a and 406b and the second field effect transistors 406c and 406d have mutually complementary channels. Although the case where two first field effect transistors 406a and 406b and two second field effect transistors 406c and 406d are used has been described as an example, similarly, three or more first field effect transistors 406a are used. , 406b and three or more second field effect transistors 406c, 406d may be used.

  In FIG. 1B, the case of the phase characteristic having one convex region 112 and one concave region 113 has been described as an example. However, according to the present embodiment, one and two or more convex regions are provided. It is possible to compensate the phase of the phase characteristic having the region 112 and the one or more recessed regions 113. The plurality of first field effect transistors 406a and 406b are used to compensate the phase of the plurality of convex regions 112, and the plurality of second field effect transistors 406c and 406d are used to form the plurality of concave regions 113. The phase can be compensated. By controlling the switches 802a to 802d, the phases of various phase characteristics can be compensated. According to the present embodiment, by connecting the n-channel field effect transistors 406a and 406b and the p-channel field effect transistors 406c and 406d, it is possible to obtain respective modulation characteristics of phase advance and phase delay.

FIG. 9 is a diagram showing a simulation result of the circuit of FIG. 8, in which the differential value of the phase on the vertical axis is plotted against the input power on the horizontal axis. p-channel field effect transistor 406c, 406 d that can generate a phase characteristic area 901 of the recess of the leading phase by using the phase characteristic of the convex portion of the phase delay by using the n-channel field-effect transistor 406a, 406 b Region 902 can be generated. According to the present embodiment, it is possible to generate both phase advance and phase lag characteristics 901 and 902 as the input power increases. The first amplifier 401 has, for example, the phase characteristic shown in FIG. 1B, and the phase characteristic shown in FIG. 1B and the phase characteristic shown in FIG. A linear operation region having a constant phase differential value over a wide range of input power can be realized.

(Fourth embodiment)
FIG. 10 is a diagram illustrating the phase characteristic 311 of the first amplifier 401. As described above, in the first amplifier 401, the phase of the output signal rotates as the input power increases. However, in the first amplifier 401 using silicon CMOS, as in the recessed region 1002, the phase is changed. In some cases, the degree of advance is so intense that the peak of the phase advance region 1002 cannot be compensated. That is, the phase characteristic 311 within the predetermined range 1001 can be easily phase compensated, but the phase characteristic 311 outside the predetermined range 1001 may be difficult to compensate. In the present embodiment, a phase compensation circuit of an amplifier for solving this problem is shown.

  FIG. 11 is a circuit diagram showing a configuration example of an amplifier circuit having a phase compensation circuit for an amplifier according to the fourth embodiment. The circuit of the fourth embodiment (FIG. 11) includes a delay device 1101, a limiting amplifier 1102, an exclusive OR circuit 1103, and a low-pass filter 1104 compared to the circuit of the third embodiment (FIG. 8). A phase difference detection circuit including this is added. Note that, here, a case where one first field-effect transistor 406a and one second field-effect transistor 406c are used is shown as an example, but two or more of each are provided as in the third embodiment. May be. Hereinafter, differences of the present embodiment from the third embodiment will be described.

  The delay device 1101 delays the input signal of the first amplifier 401 and outputs the delayed signal. The delay time of the delay device 1101 is equal to the time for the input signal of the first amplifier 401 to pass through the first amplifier 401. The limiting amplifier 1102 converts the output signal 1110 of the delay device 1101 into a binary signal 1112, and converts the output signal 1111 of the first amplifier 401 into a binary signal 1113. If the output signal 1110 of the delay device 1101 is larger than the threshold value, the binary signal 1112 becomes a high level, and if the output signal 1110 of the delay device 1101 is smaller than the threshold value, the binary signal 1112 becomes a low level. Similarly, if the output signal 1111 of the first amplifier 401 is larger than the threshold value, the binary signal 1113 becomes a high level, and if the output signal 1111 of the first amplifier 401 is smaller than the threshold value, the binary signal 1113 becomes a low level. . The limiting amplifier 1102 can convert the signals 1110 and 1111 oscillating with a sine wave into square wave signals 1112 and 1113. The exclusive OR circuit 1103 receives the signals 1112 and 1113 and outputs an exclusive OR signal 1114 of the signals 1112 and 1113. If the levels of the signals 1112 and 1113 are the same, the exclusive OR signal 1114 becomes a low level, and if the levels of the signals 1112 and 1113 are different, the exclusive OR signal 1114 becomes a high level. The exclusive OR signal 1114 is a pulse-like signal, and the pulse width increases as the phase difference between the signals 1112 and 1113 increases. The low-pass filter 1104 converts the exclusive OR signal 1114 into a DC signal by attenuating the high frequency component of the exclusive OR signal 1114 and passing the low frequency component, and outputs it to the second amplifier 413a. To do.

  The delay device 1101, the limiting amplifier 1102, the exclusive OR circuit 1103, and the low-pass filter 1104 constitute a phase difference detection circuit, and detect the phase difference between the input signal and the output signal of the first amplifier 401. The second amplifier 413a amplifies with a gain corresponding to the phase difference detected by the phase difference detection circuit. The greater the phase difference between the two, the wider the pulse width of the exclusive OR signal 1114 and the higher the level of the output DC signal of the low-pass filter 1104. The second amplifier 413 a amplifies the output signal of the low-pass filter 412 with a gain corresponding to the output signal of the low-pass filter 1104.

  The amount of phase modulation can be changed by changing the gain of the second amplifier 413a. When the phase of the output signal of the first amplifier 401 deviates greatly from the input signal of the first amplifier 401, the gain of the second amplifier 413a is set in accordance with the phase difference by the loop of the phase difference detection circuit. fluctuate. As the phase difference increases, the gain of the second amplifier 413a increases, and the amount of phase modulation obtained thereby increases. If the phase difference is reduced by this loop, the pulse width of the exclusive OR signal 1114 is narrowed, so that the DC signal level input to the second amplifier 413a is also reduced, and the phase modulation amount is also reduced. As described above, according to the present embodiment, it is possible to adaptively generate an inverse characteristic of the phase according to the degree of phase modulation of the output signal of the first amplifier 401.

  In the present embodiment, the phases of the input signal and output signal of the first amplifier 401 are compared, and the phase rotation caused by the input power is sequentially detected. Here, an example using an exclusive OR circuit 1103 as a phase comparator is shown. Further, by providing the limiting amplifier 1102 before the exclusive OR circuit 1103, the signals 1112 and 1113 having edges can be generated, and the accuracy of the phase comparison can be improved.

  The first amplifier 401 and the phase compensation circuit thereof according to the first to fourth embodiments can be used for a high-frequency circuit used in a radio communication system or a radar system. The second amplifier 413 amplifies the envelope 422 of the input signal 421 at the input terminal 402, so that the phase distortion of the first amplifier 401 can be compensated with high accuracy. Further, the peak position of the phase compensation characteristic can be changed by controlling the potential of the first potential node Vr.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

401 first amplifier 402 input terminal 403 output terminal 404 first capacitor 405 second capacitor 406 first field effect transistor 407 third capacitor 411 detector 412 low-pass filter 413 second amplifier 414 resistance

Claims (6)

A first capacitor connected between the input terminal and the first node;
A second capacitor connected between the first node and an input terminal of the first amplifier;
A first field effect transistor having a gate connected to the first node and a source and drain connected to a first potential node;
An envelope detection circuit for detecting an envelope of a signal at the input terminal;
And a second amplifier for amplifying the envelope detected by the envelope detection circuit and outputting the amplified signal to the first node.   2. The amplifier phase compensation circuit according to claim 1, wherein the second amplifier is a variable gain amplifier capable of controlling a gain. A third capacitor connected between the first potential node and the reference potential node;
3. The phase compensation circuit for an amplifier according to claim 1, wherein the first potential supplied to the first potential node can be variably controlled. The second capacitor is connected between the first node and the second node;
A fourth capacitor connected between the second node and an input terminal of the first amplifier;
A second field effect transistor having a gate connected to the second node and a source and drain connected to a second potential node;
A third amplifier that amplifies the envelope detected by the envelope detection circuit and outputs the amplified signal to the second node;
4. The amplifier phase compensation circuit according to claim 1, wherein the first field effect transistor and the second field effect transistor have mutually complementary channels. 5. And a phase difference detection circuit for detecting a phase difference between an input signal and an output signal of the first amplifier,
5. The amplifier phase compensation circuit according to claim 1, wherein the second amplifier amplifies with a gain corresponding to the phase difference detected by the phase difference detection circuit. 6. A first amplifier for amplifying the signal;
A phase compensation circuit,
The phase compensation circuit is:
A first capacitor connected between the input terminal and the first node;
A second capacitor connected between the first node and an input terminal of the first amplifier;
A first field effect transistor having a gate connected to the first node and a source and drain connected to a first potential node;
An envelope detection circuit for detecting an envelope of a signal at the input terminal;
An amplifier circuit comprising: a second amplifier that amplifies an envelope detected by the envelope detection circuit and outputs the amplified signal to the first node.

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