JP5548342B2 - Semiconductor device - Google Patents

Description

  The present invention relates to cost reduction in the assembly process of a semiconductor device and shortening of the development period of the semiconductor device.

  Along with the demand for miniaturization and higher functionality of various electronic devices such as mobile phones and digital still cameras, it is possible to cope with the reduction in size of semiconductor devices, the increase in processing speed in semiconductor devices and the increase in the number of pins of semiconductor devices. Packaging technology is required. When assembling a semiconductor device by narrowing the space between pads (terminals) of a semiconductor chip due to the effects of shrinking semiconductor chips and increasing the number of pins by SOC (system on chip). It is necessary that the pads of the semiconductor chip and the pads on the substrate that are arranged at a narrow interval overlap each other.

  Currently, in packages using organic multilayer boards that are often used in system LSIs (Large Scale Integration) such as mobile phones and digital still cameras, when the spacing between pads (terminals) of semiconductor chips is narrower than before, It is difficult to form wiring in the substrate so that the pads of the substrate overlap the pads of the semiconductor chips arranged at a narrow interval. Therefore, in this case, a special substrate with higher cost is required.

  As a means for solving this problem, a method that is currently considered to be effective is a two-stage connection in which a substrate and a semiconductor chip are connected via an intermediate wiring layer such as a silicon interposer. Specifically, the pads of the semiconductor chip and the pads on the silicon interposer, which are arranged at a narrower distance than before, are placed on top of each other to increase the spacing between the pads in the silicon interposer, and then the silicon interposer is connected to the substrate. It is a method.

  As another example of using a silicon interposer, there is one used as a redistribution layer in order to increase possible combinations of sizes of semiconductor chips to be stacked, as in Patent Document 1. Thus, the package configuration has evolved from a conventional configuration in which a package is formed of a semiconductor chip and a substrate to a configuration in which an intermediate wiring layer is added between the semiconductor chip and the substrate.

  In addition, it is necessary for the semiconductor device to satisfy the following requirements.

In mobile phones, etc., software development time and costs associated with system LSIs are high, and how to manufacture multiple types of semiconductor devices using the same semiconductor chip (system LSI) Sharing) is important. As a result, it is necessary to differentiate the functions of the semiconductor device by changing only peripheral components such as a memory capacity using the same semiconductor chip. In this case, the arrangement of solder balls (signal transmission destination) in the semiconductor device changes in conjunction with peripheral components. Conventionally, there has been little demand for semiconductor devices, so when changing peripheral components, it is more efficient to reroute the wiring by redrawing the wiring on the substrate than using the intermediate wiring layer described in Patent Document 1 or the like. . However, since the demand for semiconductor devices is increasing as described above, the method of re-wiring the wiring by redrawing the wiring of the substrate every time the peripheral component is changed cannot be dealt with.
JP 2001-257307 A

  Regarding sharing of semiconductor chips, there is only one solder ball arrangement (signal transmission destination) for one semiconductor chip, and if the use or function of the semiconductor device is different, it is necessary to recreate the substrate. Therefore, there is a problem in that manufacturing the substrates with different solder ball arrangements increases the cost and the development period of the semiconductor device becomes longer.

  Also, in the future, it is possible to share a substrate by wiring a plurality of types of semiconductor chips on the same substrate, thereby reducing the cost of the semiconductor device and shortening the development period of the semiconductor device. Conceivable. However, at present, it is difficult to perform such a technique.

  The present invention has been made to solve such problems, and a plurality of types of semiconductor chips are used by rotating a wiring layer group on the upper surface of a substrate using a two-stage package through the wiring layer group. Is connected to the same substrate.

  Furthermore, when using a low-cost board that does not have the freedom of wiring, even if the wiring can be redrawn on the board, the ball arrangement cannot be changed, and the ball arrangement can be changed. Had no choice but to use high-cost substrates. However, by rotating the wiring layer group on the upper surface of the substrate, the degree of freedom in routing the wiring is increased, so that a low-cost substrate can be used.

  The semiconductor device of the present invention includes a substrate, a wiring layer group, a semiconductor chip, and a plurality of first, second and third terminals. The plurality of first terminals and the wiring layer group are provided on the substrate. The plurality of second terminals are provided in the wiring layer group, and are connected from the first terminal via the substrate. The semiconductor chip is provided in the wiring layer group, and the plurality of third terminals are provided in the semiconductor chip and connected to the second terminals. The wiring layer group is rotatable about an axis extending perpendicularly to the upper surface of the wiring layer group as a rotation axis, and a plurality of first terminals having a specific function among the plurality of first terminals and a plurality of the first terminal and the plurality of first terminals Of the third terminals are connected to a third terminal having a specific function.

  Accordingly, it is not necessary to produce a substrate each time the wiring form on a substrate (for example, a wiring substrate) for providing a semiconductor device is different.

  In a preferred embodiment to be described later, the plurality of second terminals are arranged on the upper surface or the lower surface of the wiring layer group so as to be rotationally symmetrical with respect to the intersection where the rotation axis intersects the wiring layer group. A plurality of first wirings are provided, and one end of the first wiring is disposed so as to be rotationally symmetric with respect to an intersection where the rotation axis intersects the substrate, and one end of the first wiring connected to each other The second terminal is arranged so as to overlap each other, and the third terminal is connected to the first terminal which is different before the wiring layer group rotates and after the wiring layer group rotates.

  The semiconductor device of the present invention includes a plurality of types of substrates having different arrangements of the first terminals, and the third terminal has a phase difference in each of the substrates before the wiring layer group rotates and after the wiring layer group rotates. It is preferable to connect to a different first terminal.

  In the semiconductor device of the present invention, the plurality of first terminals are provided on the lower surface of the substrate and are separated into the first power supply terminal and the first signal terminal on the lower surface of the substrate, and the plurality of second terminals are connected to the wiring. A wiring that is provided on the upper surface of the layer group and is separated into a second power supply terminal and a second signal terminal on the upper surface of the wiring layer group, and that connects the first signal terminal and the second signal terminal; The wiring connecting the terminal and the second power supply terminal is preferably separated from each other. Thereby, the power supply wiring and the signal wiring can be easily routed.

  In the semiconductor device of the present invention, the substrate has a plurality of first wirings routed from the wiring layer group to the first terminal, and the wiring layer group includes the second wirings routed from the semiconductor chip to the second terminal. Each of the plurality of second wirings intersects with the plurality of first wirings, and a second terminal is disposed at each intersection where each of the second wirings intersects with the plurality of first wirings. The second terminal is preferably connected to the first wiring at one of the intersections. Thereby, the position where the signal is output from the lower surface of the substrate can be changed. Furthermore, if the second terminal provided at the tip in the longitudinal direction of the second wiring is connected to the first wiring at this intersection, noise due to the open stub in the high-speed signal line can be eliminated.

  In the semiconductor device of the present invention, the substrate has a pair of first terminals, the pair of first terminals are electrically connected to each other, and the second terminal is a pair of first terminals electrically connected to each other. It is preferably connected to any one of the terminals. Thereby, the position where the signal is output from the lower surface of the substrate can be changed further greatly.

  In the semiconductor device of the present invention, the substrate is provided with a plurality of first wirings, one end of each of the first wirings is provided on the upper surface of the substrate and connected to the second terminal, and the substrate is provided on the upper surface. An axis extending perpendicularly to the rotation axis is rotatable, and a part of one end of the first wiring overlaps before and after the rotation of the substrate, but the remaining one of the one end of the first wiring overlaps. Are preferably non-overlapping. Thereby, the semiconductor device can be electrically connected to a wiring board having a complicated wiring configuration.

  In the semiconductor device of the present invention, a region where the second terminal is not provided exists in the peripheral portion of the upper surface of the wiring layer group, and the first terminal and the second terminal are provided on the lower surface of the wiring layer group. Conductors for connecting to each other are provided, and a reinforcing conductor for reinforcing the strength of the wiring layer group is provided on the part of the lower surface of the wiring layer group opposite to the region. Is preferred. Thereby, the strength of the wiring layer group can be maintained.

  The semiconductor device of the present invention preferably includes a normal mode, an evaluation mode, and an analysis mode. The wiring layer group further includes a pad for connecting to the first terminal, an H fixed connection pad, and an L fixed connection pad, and the first terminal and the second terminal are connected to each other. In some cases, the normal mode is executed, and when one of the pads of the mode switching terminal and the first terminal are connected to each other, either the evaluation mode or the analysis mode may be executed. preferable. In such a semiconductor device, relatively complicated analysis and evaluation can be performed.

  In the preferred embodiments described below, the substrate is a lead frame.

  In another preferred embodiment to be described later, a plurality of wiring layer groups are arranged on the upper surface of the substrate at intervals, and a semiconductor chip is provided on each of the plurality of wiring layer groups.

  In another preferred embodiment described later, a plurality of wiring layer groups and a plurality of semiconductor chips are provided, and the wiring layer groups and the semiconductor chips are alternately stacked on the upper surface of the substrate.

  According to the present invention, it is possible to share a substrate by wiring a plurality of types of semiconductor chips on the same substrate, and semiconductor devices for different applications by changing peripheral components without changing the semiconductor chip Can be supplied. Therefore, it is possible to reduce the manufacturing cost of the semiconductor device and shorten the development time of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and description may be abbreviate | omitted. In each drawing, the thickness, length, and the like are different from the actual shape in creating the drawing. Further, the connection electrodes of the semiconductor chip, the connection terminals of the substrate, the wiring patterns, the vias, and the like are omitted or easy to illustrate.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2A and 2B, FIGS. 3A to 3C, and FIG.

  FIG. 1 is an exploded plan view of the semiconductor device according to the present embodiment. FIG. 2A is a top view of the semiconductor device according to the present embodiment, and FIG. 2B is a side view of the semiconductor device according to the present embodiment. 3A to 3C are side views of a semiconductor device different from the semiconductor device shown in FIG. FIG. 4 shows a power signal and a signal other than the power signal (hereinafter referred to as “power signal”) by rotating the wiring layer group from the state of FIG. FIG. 6 is a top view of the semiconductor device in a state where the transmission destination of “signal other than“ is simply referred to as “signal” ”is changed.

  First, reference numerals in FIGS. 1, 2A and 2B, FIGS. 3A to 3C and FIG. 4 will be described.

  Reference numeral 100 denotes a semiconductor chip. Reference numeral 101 denotes a pad (third terminal) disposed on the semiconductor chip 100. The pad 101 includes a signal pad and a power supply pad.

Reference numeral 110 denotes a wiring layer group. Reference numeral 111 denotes a pad (second terminal) provided in the wiring layer group 110, which is disposed on the lower surface of the wiring layer group 110 through the wiring layer group 110, and includes a signal pad (second signal terminal) and a power source. And a pad (second power supply terminal).
A wiring 112 (second wiring) routed from the semiconductor chip 100 to the pad 111 is a wiring for transmitting a signal or a power signal from the semiconductor chip 100 to the pad 111. One end of the wiring 112 is connected to the pad 101 of the semiconductor chip 100, and one end of the wiring 112 and the pad 101 of the semiconductor chip 100 that are connected to each other are arranged to overlap each other. S 1 is a rotation center point of the wiring layer group 110, and is a point where the rotation axis of the wiring layer group 110 intersects the upper surface of the wiring layer group 110.

  120 is a substrate. A pad (first terminal) 123 is provided on the lower surface of the substrate 120 and is electrically connected to the solder ball 170. Reference numeral 121 denotes a conductive body that passes through the substrate 120 and is connected to the pad 123. Reference numeral 122 denotes a wiring (first wiring) routed from the wiring layer group 110 to the pad 123. A signal or a power signal is transmitted to the wiring layer group. Wiring for transmitting from 110 to the pad 123. 122a is one end of the wiring 122 and is connected to the pad 111 of the wiring layer group 110, and the one end 122a of the wiring 122 and the pad 111 of the wiring layer group 110 that are connected to each other are arranged to overlap each other. S2 is a point where the rotation axis of the wiring layer group 110 intersects the substrate 120, and the substrate 120 and the wiring layer group 110 are arranged so that the center point S2 and the rotation center point S1 of the wiring layer group 110 overlap. .

  150 is a conductive body for connecting the pad 101 of the semiconductor chip 100 and one end of the wiring 112 on the wiring layer group 110, and 160 is the pad 111 of the wiring layer group 110 and one end 122 a of the wiring 122 on the substrate 120. Is connected to a pad 111 that penetrates the wiring layer group 110 and is disposed on the lower surface of the wiring layer group 110. Reference numeral 170 denotes a solder ball provided on the lower surface of the substrate 120.

  In the present embodiment and the following second to eleventh embodiments, the material of each component is not particularly limited, and even if the package is not covered with the mold resin, the material is not limited to the mold resin. It can be either a covered package. In the drawings, the mold resin is not described for the sake of clarity.

  Next, the semiconductor device according to the present embodiment will be described.

  In FIG. 1, the interval between the pads 101 of the semiconductor chip 100 is narrower than before, and it is difficult to arrange the pads 101 of the semiconductor chip 100 and the one end 122 a of the wiring 122 so as to overlap each other. However, in the wiring layer group 110, the pad 101 of the semiconductor chip 100 and one end of the wiring 112 can be arranged to overlap each other. Therefore, the semiconductor chip 100 and the wiring layer group 110 are electrically connected by connecting the pad 101 of the semiconductor chip 100 and one end of the wiring 112 to each other using micro bumps. Here, in the wiring layer group 110, the wiring 112 is provided in a radial pattern so that the distance between the pads 111 is wider than one end. Therefore, the pad 111 of the wiring layer group 110 can be disposed so as to overlap the one end 122 a of the wiring 122. As a result, the semiconductor chip 100 and the substrate 120 can be electrically connected to each other via the wiring layer group 110.

  Further, in the wiring layer group 110, the pads 111 are arranged so as to be rotationally symmetric with respect to the rotation center point S 1 on the upper surface of the wiring layer group 110. In the substrate 120, the wiring 122 has one end 122 a at the center of the substrate 120. It is arranged on the upper surface of the substrate 120 so as to be rotationally symmetric with respect to the point S2.

  In the present embodiment, the pads 111 of the wiring layer group 110 are arranged on the same circumference and at equal intervals around the rotation axis, and the number of pads 111 is 32. Therefore, even if the wiring layer group 110 is rotated about the rotation axis every 11.25 ° (= 360 ° / 32), the pad 111 of the wiring layer group 110 and the one end 122a of the wiring 122 of the substrate 120 overlap each other. Therefore, the wiring layer group 110 can be electrically connected to the substrate 120. Thereby, as described below, the pads 101 of the semiconductor chip 100 are connected to the pads 123 of the different substrates 120 before and after the wiring layer group 110 is rotated.

  2A and 2B show the semiconductor device in an actually assembled state. For example, “A” of the pad 101 of the semiconductor chip 100 is connected to “A ′” of the solder ball 170 via the conductive body 150, the wiring layer group 110, the conductive body 160 and the substrate 120.

  3A to 3C, semiconductor devices in which the connection state between the semiconductor chip 100 and the wiring layer group 110 or the connection state between the wiring layer group 110 and the substrate 120 are different from those in FIG. The side view of is shown.

  In FIG. 3A, the semiconductor chip 100 is inverted from the state shown in FIG. Specifically, the semiconductor chip 100 is inverted and provided on the lower surface of the wiring layer group 110, and the wiring layer group 110 provided with the semiconductor chip 100 on the lower surface is provided on the upper surface of the substrate 120.

  In FIG. 3B, the semiconductor chip 100 and the wiring layer group 110 are inverted from the state shown in FIG. Specifically, the inverted wiring layer group 110 and the semiconductor chip 100 are provided on the lower surface of the substrate 120 in this order.

  In FIG. 3C, the wiring layer group 110 is inverted from the state shown in FIG. Specifically, the semiconductor chip 100 is provided on the upper surface of the inverted wiring layer group 110, and the inverted wiring layer group 110 is provided on the lower surface of the substrate 120.

  Here, in the present embodiment, even the configuration shown in FIGS. 3A to 3C has the same effect as the configuration shown in FIG.

  FIG. 4 shows a state in which the wiring layer group 110 is rotated by 11.25 ° from the state shown in FIG. 2A around the rotation axis. As in FIG. A ”is connected to the solder ball 170 through the conductor 150, the wiring layer group 110, the conductor 160 and the substrate 120. However, in FIG. 4, unlike FIG. 2A, the connection destination of “A” of the pad 101 of the semiconductor chip 100 is changed from “A ′” to “A” ”of the solder ball 170. The signal is transmitted not to the solder ball 170 disposed near the center of the lower surface of the substrate 120 but to the solder ball 170 disposed near the peripheral edge of the lower surface of the substrate 120.

  Here, whether it is better to arrange the solder ball 170 closer to the center of the lower surface of the substrate 120 or closer to the periphery is determined by the routing of the wiring on the wiring substrate on which the semiconductor device is provided, specifically, In a wiring board or the like, it depends on whether the wiring is provided on the surface layer of the wiring board or on the inner layer of the wiring board.

  In the present embodiment, when the specific pad 111 of the wiring layer group 110 is connected to the solder ball 170 disposed near the center of the lower surface of the substrate 120, the wiring layer group 110 is rotated around the rotation axis. The pad 111 can be connected to the solder ball 170 disposed near the periphery of the lower surface of the substrate 120. Therefore, even when a substrate in which the solder balls 170 are disposed near the center of the lower surface of the substrate is used as the substrate 120 or a substrate in which the solder balls 170 are disposed near the periphery of the lower surface of the substrate is used. The same wiring layer group 110 can be used. Therefore, it is not necessary to manufacture the substrate 120 each time the wiring form in the wiring substrate or the like is different, so that the semiconductor device can be provided at low cost and the development period of the semiconductor device can be shortened.

  Further, when the wiring layer group 110 is rotated around the rotation axis, the transmission destination of the signal or power signal to the substrate 120 can be changed, so that the same substrate can be used for the semiconductor chips 100 having different terminal arrangements. A semiconductor device can be assembled using 120. Therefore, the cost of the semiconductor device can be reduced and the development period of the semiconductor device can be shortened by using the substrate 120 in common.

  In the first embodiment, the case of using a single substrate has been described in order to simplify the description. However, a plurality of types of substrates having different pad arrangements may be used. In this way, even when a plurality of types of substrates are used, if the wiring layer group is rotated around the rotation axis, the degree of freedom in routing the wiring can be increased. Therefore, in the case of using a low-cost substrate with a small degree of freedom in wiring, it is effective because the degree of freedom in wiring can be increased.

(Second Embodiment)
In the second embodiment of the present invention, the signal terminal and the power supply terminal are separated from each other in the wiring layer group in the first embodiment. Therefore, the signal wiring and the power supply wiring can be easily routed in the wiring layer group. A semiconductor device in this embodiment will be described with reference to FIGS. 5A is a bottom view of the wiring layer group, and FIG. 5B is a top view of the substrate.

  First, reference numerals in FIGS. 5A and 5B will be described.

  In FIG. 5A, reference numeral 210 denotes a wiring layer group, 111 a denotes a signal pad (second signal terminal) provided in the wiring layer group 210, and 111 b denotes a power supply pad provided in the wiring layer group 210. (Second power supply terminal). Reference numeral 215 denotes a wiring provided in the wiring layer group 210, and is a wiring that collects the power supply pads 111b.

  In FIG. 5B, 220 is a substrate, 123a is a signal pad (first signal terminal) provided on the substrate 220, and 123b is a power pad (first power terminal) provided on the substrate 220. It is. Reference numeral 225 denotes a wiring provided on the substrate 220, and is a wiring that collects the power supply pads 123b. The wiring 225 also serves as a pad connected to a conductive body that connects the wiring layer group 210 and the substrate 220. Note that 121, 122, and 123 are as described in the first embodiment.

  Next, the semiconductor device according to the present embodiment will be described.

  As shown in FIGS. 5A and 5B, on the wiring layer group 210, the signal pad 111a and the power supply pad 111b are separated from each other. Specifically, in the semiconductor chip (not shown) in the present embodiment, all the power terminals are drawn toward the center and all the signal terminals are drawn near the periphery. Therefore, in the wiring layer group 210 in the present embodiment, the signal pad 111 a is provided near the periphery of the upper surface of the wiring layer group 210, and the power supply pad 111 b is located near the center of the upper surface of the wiring layer group 210. Is provided.

  At this time, it is preferable to reduce the impedance of the power supply wiring by using a thick wiring. As shown in FIG. 5A, the power supply pad 111a has a wiring 215 having a circular shape in plan view at the center of the upper surface of the wiring layer group 210. It has been enhanced using.

  Also on the substrate 220 connected to the wiring layer group 210, the signal pad 123a and the power supply pad 123b are separated from each other. Specifically, the signal pad 123 a is provided near the periphery of the lower surface of the substrate 220, and the power pad 123 b is provided near the center of the lower surface of the substrate 220. Further, a wiring 225 having a circular shape in plan view is provided in order to lower the impedance in the power supply wiring, and the substrate 220 is configured so that the impedance of the semiconductor device does not deteriorate even if the wiring layer group 210 is rotated about the rotation axis. Has been. Thus, in this embodiment, by separating the signal pad 111a and the power supply pad 111b in the wiring layer group 210, the impedance in the power supply wiring can be lowered and the signal wiring can be easily routed.

(Third embodiment)
In the third embodiment of the present invention, by changing the arrangement of the conductors that connect the wiring layer group and the substrate, the signal and the power signal can be transmitted from the lower surface of the substrate as compared with the first embodiment. The output position can be changed.

  A semiconductor device according to the present embodiment will be described with reference to FIGS. 6A to 6C and FIG. FIGS. 6A to 6C and FIG. 7 are enlarged plan views of the region B shown in FIG. In FIG. 7, the wiring layer group and the substrate are connected by wire bonding. However, in the present invention, the connection method between the wiring layer group and the substrate may be a flip chip method or a wire bonding method.

  First, reference numerals in FIGS. 6A to 6C and FIG. 7 will be described.

  6A to 6C and FIG. 7, reference numeral 311 denotes a pad (second terminal) provided in the wiring layer group, and reference numeral 312 denotes a wiring routed from the semiconductor chip to the pad 311 (second wiring). This is a wiring for transmitting a signal or a power supply signal from the semiconductor chip to the pad 311. Reference numeral 322 denotes a wiring (first wiring) routed from the wiring layer group to the substrate, and is a wiring for transmitting a signal or a power signal from the wiring layer group to the substrate. 6A to 6C, 360 is a conductive body for connecting the pad 311 and the wiring 322, and 340 in FIG. 7 is a wire for connecting the pad 311 and the wiring 322.

  In this embodiment mode, the wiring 312 provided in the wiring layer group is refracted in the middle. Specifically, in FIGS. 6A to 6C, X 3 is a region where the wiring 312 and the wiring 322 intersect. Refracted toward the positive side in the axial direction (right side in FIGS. 6A to 6C), and in FIG. 7, refracted toward the positive direction side in the X axis direction (right side in FIG. 7) in the region near the wiring 322. ing. A pad 311 of the wiring layer group is disposed at a location where the wiring 312 and the wiring 322 intersect.

  In FIG. 6A, the conductor 360 is connected to the pad 311 of the wiring layer group arranged second from the bottom. Specifically, the connection between the wiring 312 and the wiring 322 is 1-I. 2-II, 3-III, 4-IV, 5-V, 6- *. Here, “1-I” means that “1” of the wiring 312 and “I” of the wiring 322 are connected to each other, and “6- *” indicates that “6” of the wiring 312 is illustrated. This means that it is not connected to any of the wirings 322 shown in FIG.

  In FIG. 6A and FIG. 6B, three conductors 360 of the six conductors 360 are provided at different positions. Specifically, the connection between the wiring 312 and the wiring 322 is as follows. 1-I, 2-IV, 3-II, 4-III, 5-V, 6- *. As described above, the connection destinations of “2”, “3”, and “4” of the wiring 312 are different between FIG. 6A and FIG.

  In FIG. 6C, the wiring layer group is rotated around the rotation axis as described in the first embodiment, and as a result, the wiring 312 is shifted to the left in FIG. Specifically, the connection between the wiring 312 and the wiring 322 is 1- *, 2-III, 3-I, 4-II, 5-IV, and 6-V. As described above, by multiplying the first embodiment by changing the position of the conductive body 360 and changing the connection destination of the wiring 312 (this embodiment), the signal and the power signal are transferred to the bottom surface of the substrate. The position output from can be changed. Therefore, it is possible to meet the demand for a mounting board or the like without changing the wiring form on the board.

  In FIG. 7, if the connection destination of the wire 340 is changed, the same effects as in FIGS. 6A to 6C can be obtained.

(Fourth embodiment)
In the fourth embodiment of the present invention, the noise due to the open stub in the high-speed signal line in the third embodiment is eliminated, and the electrical characteristics of the semiconductor device are improved.

  A semiconductor device in this embodiment will be described with reference to FIGS. Here, FIG. 8 is an enlarged plan view of the region B shown in FIG. 2A, and 311, 312, 322 and 360 in FIG. 8 are as shown in the third embodiment.

  In FIG. 8, “2” of the wiring 312 shown in FIGS. 6A to 6C is shortened to connect “2” of the wiring 312 and “I” of the wiring 322. By separating the tip of “2” of the wiring 322 from “2” rather than the portion connected to the wiring 312, it is possible to remove the wiring that becomes an open stub noise source. Therefore, although the positions of the conductive bodies 360 are the same between “2” and “4” of the wiring 312, “2” of the wiring 312 is less susceptible to noise than “4” of the wiring 312.

  Further, since “2” of the wiring 312 is connected to “I” of the wiring 322 and “I” of the wiring 322 is an open stub, it is affected by noise from the tip of the “I” of the wiring 322. However, for example, in the connection between “1” of the wiring 312 and “II” of the wiring 322, both the wirings are open stubs, so that they are affected by noise from the tips of the both wirings. Therefore, when one of the wirings is an open stub, the influence of noise can be reduced compared to the case where both the wirings are open stubs.

  Further, in the connection between “1” of the wiring 312 and “II” of the wiring 322, the conductive body 360 is provided near the midpoint in the longitudinal direction of “II” of the wiring 322. It will be affected by the noise from both the lower and upper ends. However, in the connection between “2” of the wiring 312 and “I” of the wiring 322, the conductive body 360 is provided at the end (“lower” in FIG. 8) of the wiring 322. The influence of noise from the lower end of "is considered to be small.

  As described above, “2” of the wiring 312 can reduce noise due to an open stub compared to the other wirings 312. Therefore, the magnitude of the rotation angle of the wiring layer group can be determined in accordance with the high-speed signal line, and the remaining wirings can be connected as described in the third embodiment. As described above, in this embodiment, since the high-speed signal lines are preferentially connected, the meaning of the high-speed signal lines themselves having options becomes low, and the electrical characteristics can be improved accordingly.

(Fifth embodiment)
In the fifth embodiment of the present invention, the substrate side has two receivers for one signal of the wiring layer group, and the position of the conductor that connects the wiring layer group and the wiring is determined. By changing, the signal transmission destination can be greatly changed as compared with the case of the first embodiment.

  The semiconductor device according to this embodiment will be described with reference to FIGS. FIG. 9 is a bottom view of the wiring layer group. FIG. 10 is a top view of a substrate to which the wiring layer group shown in FIG. 9 is connected. 11 and 12 are a bottom view of the wiring layer group and a bottom view of the substrate, respectively, in one modification of the present embodiment. 13 and 14 are a bottom view of a wiring layer group and a bottom view of a substrate, respectively, in another modification of the present embodiment.

  First, reference numerals in FIGS. 9 to 14 will be described.

  9, 11, and 13, 510 is a wiring layer group, 512 is a signal line, and 514 is a power supply line. A pair of signal pads 111a and 111a are connected to one signal line 512, and a pair of power supply pads 111b and 111b are connected to one power line 514.

  In FIG. 10, 520 is a substrate, 522 is a wiring provided on the upper surface of the substrate 520, 523 is a pad (first terminal) provided on the lower surface of the substrate 520, and 524 is on the lower surface of the substrate 520. Wiring provided. The pad 523 includes a signal pad and a power supply pad. Reference numerals 525 and 528 denote wirings for bringing together power supply pads on the substrate 520, and also serve as pads connected to a conductive body that connects the wiring layer group 510 and the substrate 520. Reference numerals 526 and 527 denote signal pads provided on the substrate 520, respectively. A conductive body 580 penetrates the substrate 520 in the thickness direction.

  In FIGS. 12 and 14, 520 is a substrate, 571 is a solder ball to which a signal line is connected, 572 is a ball to which a power supply line is connected, and 573 is an OPEN state solder to which nothing is connected. It is a ball.

  Next, the semiconductor device according to the present embodiment will be described.

  In the wiring layer group 510, as shown in FIG. 9, a pair of signal pads 111a, 111a is connected to one signal line 512, and a pair of power supply pads is connected to one power line 514. 111b and 111b are connected. The numbers of signal pads 111a and power supply pads 111b are not limited to the numbers shown in FIG.

  Near the center of the upper surface of the substrate 520 connected to the wiring layer group 510, as shown in FIG. 10, the power supply pads are doubled, and the power supply pads arranged on the inner side are collected by the wiring 525. The signal pads arranged on the outside are grouped by wiring 528. In addition, signal pads 526 and 527 are arranged in a double manner near the periphery of the upper surface of the substrate 520.

  The conductive body 580 penetrates in the thickness direction of the substrate 520, the wiring 522 is connected to the conductive body 580 on the upper surface of the substrate 520, and the wiring 524 is connected to the conductive body 580 on the lower surface thereof. The wirings 525 and 528 and the signal pads 526 and 527 are connected to the wiring 522, and the pad 523 is connected to the wiring 524.

  As shown in FIG. 10, the substrate 520 includes wiring when the signal from the wiring layer group 510 is received by the signal pad 527 and wiring when the signal from the wiring layer group 510 is received by the signal pad 526. Is provided. When a signal is received at the signal pads 526 and 527 of the substrate 520, the signal is transmitted to the pad 523 via the wiring 522, the conductor 580 and the wiring 524 in either case.

  In addition, as shown in FIG. 10, the substrate 520 is provided with two types of wiring, that is, a wiring when the power signal from the wiring layer group 510 is received by the wiring 525 and a wiring when the power signal is received by the wiring 528. It has been. When a power supply signal is received by the wirings 525 and 528, the signal is transmitted to the pad 523 through the wiring 522, the conductive body 580 and the wiring 524 in either case.

  In order to arrange all the signal lines 512 near the periphery of the upper surface of the wiring layer group 510 and arrange all the power supply lines 514 near the center of the upper surface of the wiring layer group 510, the wiring layer group 510 is shown in FIG. As described above, the conductor 160 is disposed on the outer signal pad 111a of the pair of signal pads 111a and 111a, and the conductor 160 is disposed on the inner power pad 111b of the pair of power pads 111b and 111b. That's fine. At this time, the arrangement of the solder balls on the lower surface of the substrate 520 is as shown in FIG.

  Further, in order to arrange a part of the signal line 512 near the center of the upper surface of the wiring layer group 510 and arrange all the power supply lines 514 near the periphery of the upper surface of the wiring layer group 510, as shown in FIG. The body 160 may be disposed. At this time, the arrangement of the solder balls on the lower surface of the substrate 520 is as shown in FIG.

  Here, attention is paid to “C” and “D” of the signal pads 111 a of the wiring layer group 510.

  In the wiring layer group 510 shown in FIG. 11, the conductor 160 is arranged at “C” of the signal pad 111a, and this signal pad 111a is “C ′” of the signal pad 527 of the substrate 520 in FIG. And connected to “C” ”of the solder ball in FIG. On the other hand, in the wiring layer group 510 shown in FIG. 13, a conductor is arranged at “D” of the signal pad 111a, and this signal pad 111a is “D ′” of the signal pad 527 of the substrate 520 in FIG. ”Is connected to“ D ″ ”of the solder ball in FIG. Thus, if the position of the conductor 160 in the wiring layer group 510 is changed, a plurality of wiring patterns can be provided.

  Also, pay attention to “E” and “F” of the power supply pad 111b of the wiring layer group 510.

  In the wiring layer group 510 shown in FIG. 11, the conductive body 160 is disposed at “E” of the power supply pad 111 b, and this power supply pad 111 b is connected to “E ′” of the wiring 525 in FIG. Are connected to solder balls provided in the region “E ″” shown in FIG. On the other hand, in the wiring layer group 510 shown in FIG. 13, the conductor 160 is arranged at “F” of the power supply pad 111b, and this power supply pad 111b is connected to “F ′” of the wiring 528 in FIG. It is connected to a solder ball provided in a region “F ″” shown in FIG.

  As described above, in this embodiment, the wiring on the substrate 520 is more complicated than in the first embodiment, but unlike the first embodiment, the position of the signal output from the substrate 520 is increased. Since it can be changed, it is possible to cope with a complicated wiring form on the wiring board or the like.

(Sixth embodiment)
In the sixth embodiment of the present invention, unlike the first embodiment, only specific signal wiring is changed. The semiconductor device according to this embodiment will be described with reference to FIGS. FIG. 15 is a bottom view of the wiring layer group, and FIGS. 16A and 16B are top views of the substrate. The substrate described in FIG. When rotated, the substrate shown in FIG.

  First, reference numerals in FIGS. 15 and 16A and 16B will be described.

  In FIG. 15, 610 is a wiring layer group, 612 is a signal line, and 111, 111a, 111b, and 160 are as described in the first embodiment. Here, the signal pads 111a are provided in the upper half of the upper surface of the wiring layer group 610 in FIG. 15, but may be provided in any manner on the upper surface of the wiring layer group 610, and the first terminal on the substrate. It is only necessary to be provided so as to be connectable.

  In FIGS. 16A and 16B, reference numeral 620 denotes a substrate. 621 is a signal pad, 622 is a signal wiring, 623 is a conductor, and 624 is a signal pad (first signal terminal) provided on the lower surface of the substrate 620. The signal pad 621 is connected to the signal pad 624 through the signal wiring 622 and the conductive body 623. 626 is a conductive body, 627 is a power supply wiring, and 629 is a power supply pad (first power supply terminal) provided on the lower surface of the substrate 620. Reference numerals 631 and 632 denote power supply wirings provided on the substrate 620, respectively, which also serve as pads connected to a conductor that connects the wiring layer group 610 and the substrate 620. The power supply wirings 631 and 632 are connected to the power supply pad 629 through the conductive body 626 and the power supply wiring 627, but the power supply wiring 631 and the power supply wiring 632 have different potentials. Are separated from each other.

  In the wiring layer group 610 in the present embodiment, as shown in FIG. 15, the signal pad 111a is provided on one side when the upper surface of the wiring layer group 610 is divided into two, and is arranged near the periphery of the upper surface. Has been. The power supply pads 111b are arranged near the center of the upper surface of the wiring layer group 610, and are arranged in two places according to different potentials. The power supply pad group 614 disposed on the upper side in FIG. 15 is connected to VDD, and the power supply pad group 616 disposed on the lower side in FIG. 15 is connected to VSS.

  In substrate 620 in this embodiment, as shown in FIGS. 16A and 16B, power supply wirings 631 and 632 are arranged near the center of the top surface of substrate 620, and near the periphery of the top surface of substrate 620. A signal pad 621 is disposed in the area. The power supply wiring 631 arranged on the upper side shown in FIG. 16A is connected to the power supply pad arranged on the center side of the substrate 620, and the power supply wiring 632 arranged on the lower side shown in FIG. It is connected to a power supply pad arranged on the peripheral side of 620. Then, on the substrate 620, except for the wiring route connected from the power supply wirings 631 and 632 to the power supply pad, the G region shown in FIG.

  In the case of manufacturing a semiconductor device using the wiring layer group 610 and the substrate 620 in this embodiment, first, the wiring layer group 610 is arranged on the substrate 620 shown in FIG. The wiring layer group 610 is rotated around the rotation axis so as to form a pattern. The rotation angle when rotating the wiring layer group 610 around the rotation axis needs to be 0 ° or more and less than 90 °. If the rotation angle is 90 ° or more, the power supply pad group 614 of the wiring layer group 610 is connected to both the power supply wiring 631 and the power supply wiring 632 of the substrate 620 and the power supply pad group 615 of the wiring layer group 610 becomes the substrate 620. Are connected to both the power supply wiring 631 and the power supply wiring 632, so that a short circuit occurs between the power supply pad 614 and the power supply pad 615. On the other hand, when the rotation angle is less than 90 °, the power supply pad group 614 of the wiring layer group 610 is connected to either the power supply wiring 631 or the power supply wiring 632 of the substrate 620 and the power supply pad group 615 of the wiring layer group 610 is Since it is connected to the other of the power supply wiring 631 and the power supply wiring 632 of the substrate 620, it is possible to suppress occurrence of a short circuit between the power supply pad group 614 and the power supply pad group 615 via the power supply wirings 631 and 632.

  Next, when the substrate 620 shown in FIG. 16A is rotated by 180 ° about the rotation axis, the power supply pad group 631 and the power supply pad group 632 are interchanged as shown in FIG. The positions of the power supply pads (first power supply terminals) of the substrate 620 to which the power supply pad groups 614 and 615 of the wiring layer group 610 are connected can be switched. Naturally, the signal pads of the wiring layer group 610 are arranged point-symmetrically, and are not changed even if rotated by 180 °, and only the arrangement of VDD and VSS can be exchanged.

  In the present embodiment, as described above, after the wiring layer group 610 is rotated around the rotation axis to obtain an optimal wiring pattern, only the arrangement of the power supply lines is changed without changing the arrangement of the signal lines on the substrate 620. can do. Therefore, in this embodiment, it is possible to sufficiently cope with a complicated wiring form on the wiring board or the like as compared with the first embodiment.

  In this embodiment, the signal line and the power line are distinguished for the sake of explanation, but the same effect can be obtained even when only a specific signal is asymmetrical.

  Further, the rotation angle of the substrate is not limited to 180 °.

(Seventh embodiment)
In the seventh embodiment of the present invention, the shape of the wiring layer group in the first embodiment is changed. The semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 17 is a bottom view of the wiring layer group in this embodiment.

  Reference numerals in FIG. 17 will be described. In FIG. 17, reference numeral 710 denotes a wiring layer group, 711 denotes a dummy pad, and 760 denotes a reinforcing conductor for reinforcing the wiring layer group. 111, 111a, 111b, 160, and 215 are all as described in the first embodiment.

  In FIG. 17, the planar shape of the wiring layer group 710 is a quadrangle. Considering that the wiring layer group 710 is manufactured by dicing, it is considered that the planar shape of the wiring layer group 710 is preferably a square rather than a circle.

  Generally, when the planar shape of the wiring layer group is a quadrangle, the pads are arranged when the pads are arranged rotationally symmetrically with respect to the center point on the upper surface of the wiring layer group as described in the first embodiment. No area (hereinafter referred to as “unpadded area”) is formed at the four corners of the rectangle. Since no pad is arranged in the unpadded region, a conductive body connected to the pad is not provided. For this reason, when such unpadded areas are formed at the four corners of the quadrangle, when the underfill material is injected between the wiring layer group and the substrate, the balance between the unpadded areas and the areas other than the unpadded areas is balanced. May deteriorate and voids may occur. In addition, if such unpadded regions are formed at the four corners of a quadrangle, the strength of the wiring layer group may not be maintained, and the reliability of the semiconductor device may fall below the standard.

  Therefore, in the wiring layer group 710 in the present embodiment, dummy pads 711 are provided at four corners on the upper surface of the wiring layer group 710, and reinforcing conductors 760 for reinforcing the wiring layer group are provided on the dummy pads 711, respectively. Yes. As a result, the reliability of the semiconductor device can be maintained even when a wiring layer group having a rectangular plane shape is used as the wiring layer group 710.

(Eighth embodiment)
In the eighth embodiment of the present invention, functions for fixing H and L to specific terminals in the wiring layer group described in the first embodiment are added. The semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 18 is a bottom view of the wiring layer group in the present embodiment.

  Reference numerals in FIG. 18 will be described. In FIG. 18, reference numeral 810 denotes a wiring layer group, 811 denotes a mode switching terminal, and 812 denotes a signal line. 111, 111a, 111b, 160, 215, 711, and 760 are as described in the first and seventh embodiments.

  In this embodiment, the three signal lines are set to be H-fixed and L-fixed using the gap on the lower surface of the wiring layer group 810 (the lower right gap in FIG. 18). It is. In FIG. 18, a wiring layer group having a quadrangular planar shape is used as the wiring layer group 810, but the planar shape of the wiring layer group 810 is not particularly limited.

  In the present embodiment, the semiconductor chip is provided with a terminal (mode switching terminal) for inputting the analysis mode and the evaluation mode (not shown). This mode switching terminal has three terminals, and the mode is switched in combination when each terminal is fixed to H or L.

  This mode switching terminal is also provided in the wiring layer group 810. The wiring layer group 810 is provided with three types of pads 811, 811 and 811, which are a ball connection pad, an H fixed connection pad, and an L fixed connection pad, and connect the wiring layer group 810 and the substrate. The mode can be determined depending on which of the ball connection pad, the H fixed connection pad, and the L fixed connection pad the conductor 160 is disposed on. There is no problem even if the ball connection pad is open if it is not necessary. The ball connection pad, the H fixed connection pad, and the L fixed connection pad are fixed to H or L through a high resistance, and all the pads are set to shift to the normal mode when they are open. .

  When the semiconductor device is used in the normal mode, the connection destination is changed by rotating the wiring layer group 810 around the rotation axis as described in the first embodiment and the like. When using the semiconductor device in the evaluation mode and the analysis mode, the wiring layer group 810 is fixed at an angle shown in FIG. 18 without rotating around the rotation axis, and the conductive body connecting the wiring layer group 810 and the substrate. By changing the arrangement of 160, it is possible to switch to a plurality of modes such as an evaluation 1 mode, an evaluation 2 mode, an analysis 1 mode, and an analysis 2 mode. Thereby, more complicated analysis and evaluation are possible, and the man-hours for analysis and evaluation can be reduced.

(Ninth embodiment)
In the ninth embodiment of the present invention, the substrate described in the first embodiment is replaced with a lead frame. The semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 19 is a top view of the semiconductor device according to the present embodiment.

  Reference numerals in FIG. 19 will be described. The lead 923 and the die pad 924 are connected by a frame (not shown) before the lead frame is assembled. However, after assembling the lead frame, the frame is cut after being fixed with resin. Thereby, the lead 923 and the die pad 924 are insulated. Reference numeral 921 denotes a pad provided on the upper surface of the lead 923, and reference numeral 922 denotes a wiring routed from the wiring layer group 110 to the pad 921. 923a is an internal lead, and 923b is an external lead. 925 is a sealing resin. Note that reference numerals 100, 101, 110, 111, and 112 are the same as those described in the first embodiment.

  In the semiconductor device according to the present embodiment, the wiring layer group 110 is provided on the die pad 924, the semiconductor chip 100 is provided on the wiring layer group 110, and the external lead 923b of the lead 923 is exposed. It is sealed with a sealing resin 925.

  Since the configuration of the wiring layer group 110 in the present embodiment is substantially the same as the configuration of the wiring layer group 110 in the first embodiment, when the wiring layer group 110 is rotated around the rotation axis, the connection of the pads 111 is performed. For example, the lead can be largely changed from “I” to “J” of the lead 923.

(Tenth embodiment)
In the tenth embodiment of the present invention, the semiconductor device includes a plurality of wiring layer groups. The semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 20 is a top view of the semiconductor device according to the present embodiment.

  In the semiconductor device according to the present embodiment, a plurality of wiring layer groups 110 and 110 are arranged side by side on the upper surface of the substrate 120 at intervals. As a result, even when semiconductor chips having different specifications are mounted on the same substrate, it is possible to absorb inconsistencies in signal arrangement by routing the wiring in the wiring layer group 110 and rotating the wiring layer group 110. .

  In FIG. 20, two wiring layer groups are provided on the substrate, but the number of wiring layer groups is not particularly limited.

  In addition, there is no problem even if the semiconductor chip is mounted on the lower surface of the wiring layer group.

(Eleventh embodiment)
In the eleventh embodiment of the present invention, the semiconductor device includes a plurality of wiring layer groups and a plurality of semiconductor chips. The semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 21 is a side view of the semiconductor device according to the present embodiment.

  In the semiconductor device according to the present embodiment, the wiring layer groups 110 and the semiconductor chips 100 are alternately stacked on the upper surface of the substrate 120. Thereby, the wiring layer groups having different specifications around the rotation axis can be rotated separately. Therefore, as in the tenth embodiment, it is possible to absorb mismatches in signal arrangement by wiring routing in the wiring layer group and rotation of the wiring layer group.

  In FIG. 21, two wiring layer groups are provided on the substrate, but the number of wiring layer groups is not particularly limited.

  In addition, there is no problem even if the semiconductor chip is mounted on the lower surface of the wiring layer group.

  As described above, the semiconductor device of the present invention can be manufactured using a common substrate even when the arrangement of solder balls (signal transmission destination) on the lower surface of the substrate differs depending on the use of the semiconductor device. can do. In addition, it is possible to improve the degree of freedom in routing the wiring with respect to a low-cost substrate with a low degree of freedom in routing the wiring. Therefore, the cost of the semiconductor device can be reduced and the development period of the semiconductor device can be shortened, which is useful in the field of electronic equipment such as a mobile phone or a digital still camera having problems such as high cost and a long development period. .

1 is an exploded plan view of a semiconductor device according to a first embodiment. (A) is a top view of one form of the semiconductor device concerning 1st Embodiment, (b) is a side view of the semiconductor device. (A)-(c) is a side view of the semiconductor device different from the semiconductor device shown in FIG.2 (b), respectively. It is a top view of another form of the semiconductor device concerning a 1st embodiment. (A) is a bottom view of the wiring layer group in 2nd Embodiment, (b) is a top view of the board | substrate in the same embodiment. (A)-(c) is a top view which shows the connection form of the wiring of a board | substrate and the wiring of a wiring layer group in 3rd Embodiment. It is a top view which shows another connection form of the wiring of a board | substrate and the wiring of a wiring layer group in 3rd Embodiment. It is a top view which shows the connection form of the wiring of a board | substrate and the wiring of a wiring layer group in 4th Embodiment. It is the bottom view which showed the structure of the wiring layer group 1 in 5th Embodiment. It is a top view of the board | substrate in 5th Embodiment. It is the bottom view which showed the structure according to wiring layer group in 5th Embodiment. It is the bottom view which showed one structure of the board | substrate in 5th Embodiment. It is the bottom view which showed another structure of the wiring layer group in 5th Embodiment. It is the bottom view which showed another structure of the board | substrate in 5th Embodiment. It is a bottom view of a wiring layer group in a sixth embodiment. (A) is a top view of the substrate in the sixth embodiment, and (b) is a top view of the substrate when the substrate shown in (a) is rotated by 180 ° about the rotation axis. It is a bottom view of a wiring layer group in a seventh embodiment. It is a bottom view of a wiring layer group in an eighth embodiment. It is a top view of the semiconductor device concerning 9th Embodiment. It is a top view of the semiconductor device concerning 10th Embodiment. It is a side view of the semiconductor device concerning 11th Embodiment.

Explanation of symbols

100 semiconductor chip
101 Pad (3rd terminal)
110 Wiring layer group 111 Pad (second terminal)
111a signal pad (second signal terminal)
111b Power supply pad (second power supply terminal)
112 wiring (second wiring)
120 substrates
122 wiring (first wiring)
123 Pad (1st terminal)
123a Signal pad (first signal terminal)
123b Power supply pad (First power supply terminal)
160 Conductor
311 Pad (second terminal)
312 wiring (second wiring)
322 wiring (first wiring)
510 Wiring layer group 512 Signal line
514 Power line
520 substrate
523 pad (first terminal)
610 Wiring layer group 620 Substrate
624 signal pad (first signal terminal)
629 Power supply pad (First power supply terminal)
710 Wiring layer group 711 Dummy pad
760 Conductor for reinforcement
810 Wiring layer group

Claims (12)

A substrate,
A plurality of first terminals provided on the substrate ;
A wiring layer group placed before Symbol substrate,
A plurality of first wirings provided on the substrate and routed from the wiring layer group to the first terminals;
A plurality of second terminals provided on an upper surface or a lower surface of the wiring layer group and connected from the first terminal via the substrate;
A semiconductor chip mounted on the wiring layer group;
A plurality of third terminals provided on the semiconductor chip and connected to the second terminals;
The wiring layer group is rotatable about an axis extending perpendicular to the upper surface of the wiring layer group as a rotation axis,
The semiconductor chip is arranged so that the rotation axis overlaps a first intersection that intersects the wiring layer group,
One end of the first wiring is arranged so as to be rotationally symmetric with respect to a second intersection where the rotation axis intersects the substrate,
The one end of the first wiring connected to each other and the second terminal are arranged to overlap each other,
The plurality of second terminals are rotationally symmetric with respect to the first intersection, and are arranged at equal intervals on the same circumference around the rotation axis,
The wiring layer group includes a plurality of second wirings routed from the semiconductor chip to the second terminal, and the plurality of second wirings are arranged radially around the rotation axis,
Due to the rotation of the wiring layer group, the first terminal having a specific function among the plurality of first terminals is different from the one before the rotation of the wiring layer group. A semiconductor device connected to a third terminal having a function. The semiconductor device according to claim 1 ,
Each of the previous SL second wiring intersect the plurality of first wiring,
The second terminals are arranged at intersections where each of the second wirings and the plurality of first wirings intersect, and the second terminal is the first terminal at one of the intersections. A semiconductor device connected to wiring. The semiconductor device according to claim 2,
The semiconductor device in which the second terminal provided at the tip in the longitudinal direction of the second wiring is connected to the first wiring at the intersection. The semiconductor device according to claim 1,
The semiconductor device, wherein the substrate is a lead frame. The semiconductor device according to claim 4.
The lead frame has a die pad and a plurality of internal leads arranged to surround the die pad,
The wiring layer group is placed on the die pad,
The plurality of first terminals are semiconductor devices disposed on the plurality of internal leads. The semiconductor device according to any one of claims 1 to 3,
The plurality of first terminals are provided on a lower surface of the substrate, and are separated into a first power supply terminal and a first signal terminal on the lower surface of the substrate,
The plurality of second terminals are provided on an upper surface of the wiring layer group, and are separated into a second power supply terminal and a second signal terminal on the upper surface of the wiring layer group,
A wiring for connecting the first signal terminal and the second signal terminal and a wiring for connecting the first power terminal and the second power terminal are separated from each other. The semiconductor device according to any one of claims 1 to 3,
The substrate has a pair of first terminals, and the pair of first terminals are electrically connected to each other;
The second terminal is a semiconductor device connected to one of the pair of first terminals electrically connected to each other. The semiconductor device according to any one of claims 1 to 3,
A plurality of first wirings are provided on the substrate,
One end of each of the first wirings is provided on the upper surface of the substrate and connected to the second terminal,
The substrate is rotatable about an axis extending perpendicular to the upper surface as a rotation axis,
A semiconductor device in which a part of the one end of the first wiring overlaps before and a rest of the one end of the first wiring does not overlap before and after the rotation of the substrate. The semiconductor device according to any one of claims 1 to 3,
In the peripheral portion of the upper surface of the wiring layer group, there is a region where the second terminal is not provided,
Conductors for connecting the first terminal and the second terminal are provided on the lower surface of the wiring layer group,
A semiconductor device in which a reinforcing conductor for reinforcing the strength of the wiring layer group is provided on a portion of the lower surface of the wiring layer group opposite to the region. The semiconductor device according to any one of claims 1 to 3,
It has a normal mode, an evaluation mode, and an analysis mode.
The wiring layer group further includes a pad for connecting to the first terminal, an H fixed connection pad, and an L fixed connection pad,
When the first terminal and the second terminal are connected to each other, the normal mode is executed,
A semiconductor device in which one of the evaluation mode and the analysis mode is executed when any pad of a mode switching terminal and the first terminal are connected to each other. The semiconductor device according to any one of claims 1 to 3,
On the upper surface of the substrate, a plurality of the wiring layer groups are arranged at intervals from each other,
A semiconductor device in which the semiconductor chip is provided on each of the plurality of wiring layer groups. The semiconductor device according to any one of claims 1 to 3,
A plurality of the wiring layer groups and a plurality of the semiconductor chips,
A semiconductor device in which the wiring layer group and the semiconductor chip are alternately stacked on the upper surface of the substrate.