JP5552249B2 - 3-terminal thyristor - Google Patents

Description

  The present invention relates to a three-terminal thyristor.

  Conventionally, a three-terminal thyristor that controls a main current flowing between an anode electrode and a cathode electrode by controlling a gate trigger current is known (see, for example, Patent Documents 1 and 2).

  FIGS. 10 and 11 are diagrams for explaining a conventional three-terminal thyristor 900. FIG. 10A is a plan view of the three-terminal thyristor 900, and FIG. 10B is a cross-sectional view taken along line A1-A1 in FIG. FIG. 11 is a cross-sectional view taken along line A2-A2 of FIG. In FIG. 10A, the cathode electrode 928, the gate electrode 930, and the oxide film 926 are not shown. In FIG. 11, an arrow indicates a path through which the gate trigger current flows.

The conventional three-terminal thyristor 900 is a reverse blocking three-terminal thyristor having a short gate structure. Then, as shown in FIGS. 10 and 11, a p-type anode layer 910, n is located on the first main surface side of the p-type anode layer 910 ^- -type base layer 912, n ^- first in the mold base layer 912 A p-type base layer 914 located on the main surface side, and an n ⁺ -type cathode region 916, a p ⁺ -type first ohmic region 918 and a p ⁺ -type second ohmic region 920 formed on the surface of the p-type base layer 914. In addition, an anode electrode 932 is formed on the second main surface side of the p-type anode region 910 via a p ⁺ -type ohmic layer 924, and the first main in the n ⁺ -type cathode region 916 and the p ⁺ -type first ohmic region 918 is formed. A cathode electrode 928 is formed on the surface side, and a gate electrode 930 is formed on the first main surface side in the p ⁺ -type second ohmic region 920.

  For this reason, according to the conventional three-terminal thyristor 900, the main current flowing between the anode electrode 932 and the cathode electrode 928 can be controlled by controlling the gate trigger current.

Japanese Patent Laid-Open No. 5-82776 JP-A-6-97426

  However, in the conventional three-terminal thyristor 900, since the gate trigger current flows through a narrow path, the main current is initially ignited in the narrow range due to this. As a result, the main current flows in a concentrated manner at a high current density at the time of turn-on, and there is a problem that the three-terminal thyristor may be destroyed.

  Such a problem is not limited to a reverse blocking three-terminal thyristor, but is a problem that can be applied to a reverse conducting three-terminal thyristor and other three-terminal thyristors in general.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a three-terminal thyristor having a structure that is difficult to be destroyed at turn-on by reducing the current density of the main current that flows at turn-on. To do.

[1] A three-terminal thyristor according to the present invention includes a first conductor type anode layer, a second conductivity type first base layer located on the first main surface side of the anode layer, and a first base layer of the first base layer. A first conductivity type second base layer located on the first main surface side; a second conductivity type cathode region formed on the surface of the second base layer; a first conductivity type first ohmic region; A second ohmic region of the mold, an anode electrode is formed on the second main surface side of the anode layer, a cathode electrode is formed on the first main surface side of the cathode region and the first ohmic region, In the three-terminal thyristor having a gate electrode formed on the first main surface side in the second ohmic region, the cathode region, the first ohmic region, and the second ohmic region in the second base layer. A first conductivity type containing a first conductivity type impurity at a higher concentration than the second base layer so as to extend from the second ohmic region to the cathode region in plan view in a deeper region. A buried diffusion layer is formed.

  According to the three-terminal thyristor of the present invention, the second base layer extends from the second ohmic region to the cathode region in a region deeper than the cathode region, the first ohmic region, and the second ohmic region in the second base layer. Since the buried diffusion layer of the first conductivity type containing the first conductivity type impurity having a higher concentration than the layer is formed, the gate trigger current flows through the buried diffusion layer. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, the current density of the main current that flows at turn-on is reduced, and the three-terminal thyristor has a structure that is not easily destroyed at turn-on.

  In this specification, the first main surface refers to the surface on the side where the cathode electrode is formed. In addition, the second main surface refers to a surface opposite to the first main surface.

[2] In the three-terminal thyristor of the present invention, it is preferable that the buried diffusion layer is formed at a boundary portion between the first base layer and the second base layer.

  With such a configuration, the buried diffusion layer can be formed relatively easily in a region deeper than the cathode region, the first ohmic region, and the second ohmic region in the second base layer.

[3] In the three-terminal thyristor of the present invention, it is preferable that the buried diffusion layer is formed at a position shallower than a boundary portion between the first base layer and the second base layer.

  Even with such a configuration, the buried diffusion layer can be formed relatively easily in a region deeper than the cathode region, the first ohmic region, and the second ohmic region in the second base layer.

[4] In the three-terminal thyristor of the present invention, the impurity concentration of the buried diffusion layer is preferably set in the range of 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  With this configuration, the gate trigger current can easily flow through the buried diffusion layer.

[5] In the three-terminal thyristor of the present invention, it is preferable that an interval between the second ohmic region and the buried diffusion layer is set in a range of 20 μm to 40 m.

  As described above, the reason why the distance between the second ohmic region and the buried diffusion layer is preferably set in the range of 20 μm to 40 μm is that the distance between the second ohmic region and the buried diffusion layer is longer than 40 μm. This is because it becomes difficult for the gate trigger current to flow from the second ohmic region through the buried diffusion layer. When the distance between the second ohmic region and the buried diffusion layer is shorter than 20 μm, the breakdown voltage as a three-terminal thyristor is obtained. This is because the performance cannot be maintained.

[6] In the three-terminal thyristor of the present invention, it is preferable that the buried diffusion layer is formed on the entire surface of the second base layer as viewed in plan.

  With such a configuration, the gate trigger current flows through a wider path.

[7] In the three-terminal thyristor of the present invention, it is preferable that the buried diffusion layer is partially formed in the second base layer as viewed in a plan view.

  Even with this configuration, the gate trigger current can flow through a wider path.

[8] In the three-terminal thyristor of the present invention, the second ohmic region and the buried diffusion layer are connected by a first conductivity type connection layer containing a high concentration first conductivity type impurity. Is preferred.

  With such a configuration, the gate trigger current is more likely to flow from the second ohmic region toward the buried diffusion layer.

[9] In the three-terminal thyristor of the present invention, the three-terminal thyristor preferably has a short gate structure.

  With such a configuration, the sensitivity to the gate trigger current is lower than that without the short gate structure, so that the gate trigger current flows more reliably toward the buried diffusion layer.

FIG. 3 is a diagram for explaining a three-terminal thyristor 100 according to the first embodiment. FIG. 3 is a diagram for explaining a three-terminal thyristor 100 according to the first embodiment. FIG. 3 is a view for explaining the method for manufacturing the three-terminal thyristor according to the first embodiment. FIG. 3 is a view for explaining the method for manufacturing the three-terminal thyristor according to the first embodiment. 6 is a cross-sectional view of a three-terminal thyristor 200 according to Embodiment 2. FIG. 6 is a cross-sectional view of a three-terminal thyristor 300 according to Embodiment 3. FIG. 6 is a cross-sectional view of a three-terminal thyristor 400 according to Embodiment 4. FIG. 7 is a cross-sectional view of a three-terminal thyristor 500 according to Embodiment 5. FIG. It is a figure shown in order to demonstrate the 3 terminal thyristor 600 which concerns on Embodiment 6. FIG. It is a figure shown in order to demonstrate the conventional 3 terminal thyristor 900. It is a figure shown in order to demonstrate the conventional 3 terminal thyristor 900.

  Hereinafter, the three-terminal thyristor of the present invention will be described in more detail based on the embodiments shown in the drawings.

[Embodiment 1]
1. Structure of 3-terminal thyristor according to Embodiment 1 FIGS. 1 and 2 are views for explaining a 3-terminal thyristor 100 according to Embodiment 1. FIG. FIG. 1A is a plan view of a three-terminal thyristor 100, and FIG. 1B is a cross-sectional view taken along line A1-A1 of FIG. FIG. 2 is a cross-sectional view taken along line A2-A2 of FIG. In FIG. 1A, the cathode electrode 128, the gate electrode 130, and the oxide film 126 are not shown. Further, in FIG. 2, an arrow indicates a path through which the gate trigger current flows.

The three-terminal thyristor 100 according to the first embodiment is a mesa-type reverse blocking three-terminal thyristor having a short gate structure. 1 and 2, a p-type anode layer (first conductor type anode layer) 110 and an n ⁻ -type first base layer (on the first main surface side in the p-type anode layer 100) ( A first conductivity type first base layer) 112; a p-type second base layer (first conductivity type second base layer) 114 located on the first main surface side of the n ⁻ -type first base layer 112; An n ⁺ type cathode region (second conductivity type cathode region) 116, a p ⁺ type first ohmic region (first conductivity type first ohmic region) 118 and p formed on the surface of the p type second base layer 114. ⁺ Type second ohmic region (second ohmic region of first conductivity type) 120, an anode electrode 132 is formed on the second main surface side of the p type anode layer 110, and n ⁺ type cathode region 116 and p ⁺ Type first ohmic region 118 A cathode electrode 128 is formed on the first main surface side of the gate electrode 130, and a gate electrode 130 is formed on the first main surface side of the p ⁺ -type second ohmic region 120.

In the three-terminal thyristor 100 according to the first embodiment, as shown in FIGS. 1 and 2, the n ⁺ -type cathode region 116, the p ⁺ -type first ohmic region 118, and the p ⁺ -type second base layer 114 in the p-type second base layer 114. N having a higher concentration than the p-type second base layer 114 so as to extend from the p ⁺ -type second ohmic region 120 to the n ⁺ -type cathode region 116 in a plan view in a region deeper than the two-ohmic region 120. A p ⁺ type buried diffusion layer 122 containing a type impurity is formed.

In the three-terminal thyristor 100 according to the first embodiment, the p ⁺ type buried diffusion layer 122 is formed at the boundary between the n ⁻ type first base layer 112 and the p type second base layer 114.

In the three-terminal thyristor 100 according to the first embodiment, the impurity concentration of the p-type anode layer 110 is set to, for example, 1 × 10 ¹⁶ cm ⁻³ , and the impurity concentration of the n ⁻ -type first base layer 112 is, for example, is set to 1 × ¹⁰ 14 ^{cm -3,} the impurity concentration of the p-type second base layer 114, for example, is set to 1 × ¹⁰ 18 ^{cm -3,} the impurity concentration of the ^{n +} -type cathode region 116, for example, it is set to 1 × ¹⁰ 20 ^{cm -3,} the impurity concentration of the ^{p +} -type first ohmic region 118 may, for example 1 × ¹⁰ 20 ^m is set to ^{-3, p +} -type second ohmic region 120 impurity concentration, for example, 1 × ¹⁰ 20 ^{cm -3} is set in, the impurity concentration of the ^{p +} -type ohmic layer 124, for example, is set to ^{1 × 10 20 m -3, p} + -type Umakomi拡Impurity concentration of the layer 122 is set in a range of ^{5 × 10 18 cm -3 ~1 ×} 10 20 cm -3.

In the three-terminal thyristor 100 according to the first embodiment, the thickness of the p-type anode layer 110 is 40 μm, for example, and the thickness of the n ⁻ -type first base layer 112 is set to 120 μm, for example. The thickness of the second base layer 114 is set to 40 μm, for example, the depth of the n ⁺ -type cathode region 116 is set to 15 μm, for example, and the p ⁺ -type first ohmic region 118 and the p ⁺ -type first The depth of the 2 ohmic region 120 is set to 3 μm, for example, the depth of the p ⁺ type ohmic layer 124 is set to 5 μm, for example, and the thickness of the p + type buried diffusion layer 122 is 5 μm to The range is set to 10 μm.

In the three-terminal thyristor 100 according to the first embodiment, the interval between the p ⁺ type second ohmic region 120 and the p ⁺ type buried diffusion layer 122 is set in a range of 20 μm to 40 m.

In the three-terminal thyristor 100 according to the first embodiment, as shown in FIG. 1A, the p ⁺ type buried diffusion layer 122 is partially formed in the n ⁻ type second base layer 114 in plan view. Has been.

2. Effects of the three-terminal thyristor according to the first embodiment According to the three-terminal thyristor 100 according to the first embodiment, the n ⁺ -type cathode region 116, the p ⁺ -type first ohmic region 118, and the p ⁺ -type in the p-type second base layer 114. A p-type impurity having a concentration higher than that of the p-type second base layer 114 is included in a region deeper than the second ohmic region 120 so as to extend from the p ⁺ -type second ohmic region 120 to the n ⁺ -type cathode region 116. Since the p ⁺ type buried diffusion layer 122 is formed, the gate trigger current flows through the p ⁺ type buried diffusion layer 122 described above. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, the current density of the main current that flows at turn-on is reduced, and the three-terminal thyristor has a structure that is not easily destroyed at turn-on.

Further, according to the three-terminal thyristor 100 according to the first embodiment, the p ⁺ type buried diffusion layer 122 is formed at the boundary between the n ⁻ type first base layer 112 and the p type second base layer 114. The p ⁺ type buried diffusion layer 122 is relatively easy to be deeper than the n ⁺ type cathode region 116, the p ⁺ type first ohmic region 118, and the p ⁺ type second ohmic region 120 in the p type second base layer 114. Can be formed.

Further, according to the three-terminal thyristor 100 according to the first embodiment, the impurity concentration of the p ⁺ -type buried diffusion layer 122 is set in the range of 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . Therefore, the gate trigger current easily flows through the p ⁺ type buried diffusion layer 122.

Further, according to the three-terminal thyristor 100 according to the first embodiment, the interval between the p ⁺ -type second ohmic region 120 and the p ⁺ -type buried diffusion layer 122 is set in the range of 20 μm to 40 m. ^The gate trigger current does not easily flow from the ⁺ type second ohmic region 120 through the p ⁺ type buried diffusion layer 122, and the withstand voltage performance as a three-terminal thyristor cannot be maintained.

  In addition, since the three-terminal thyristor 100 according to the first embodiment has the short gate structure, the sensitivity to the gate trigger current is lower than that without the short gate structure, and the gate trigger current is embedded in the buried diffusion layer. It will flow more reliably toward.

3. Manufacturing Method of Three-Terminal Thyristor According to Embodiment 1 FIGS. 3 and 4 are views for explaining a manufacturing method of a reverse blocking three-terminal thyristor according to Embodiment 1. FIG. 3A to FIG. 3E and FIG. 4A to FIG. 4D are process diagrams.

  The three-terminal thyristor according to Embodiment 1 can be manufactured by the following process. Hereinafter, each process is demonstrated one by one.

(1) Semiconductor substrate preparation step First, an n ⁻ type semiconductor substrate (n ⁻ type first base layer) 112 made of n ⁻ type silicon, for example, having a thickness of 120 μm and an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ is prepared ( (See FIG. 3 (a)).

(2) ^{p +} -type buried diffusion layer formation step Next, the epitaxial growth technique, for example, a thickness of 5 m to 10 m, ^{p +} -type buried diffusion of an impurity concentration of ^{5 × 10 18 cm -3 ~1 ×} 10 20 cm -3 The layer 122 is formed on the n ⁻ -type first base layer 112 (see FIG. 3B).

(3) Step of forming p-type second base layer Next, by epitaxial growth technology, for example, the p-type second base layer 114 having a thickness of 40 μm and an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is formed on the p ⁺ -type buried diffusion layer 122. (See FIG. 3C).

(4) p-type anode layer forming step Next, the p-type anode layer 110 having a thickness of, for example, 40 μm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is formed into a second main layer of the n ⁻ -type first base layer 112 by an impurity diffusion technique. It is formed on the surface side surface (see FIG. 3D).

(5) p ⁺ type ohmic layer forming step Next, the p ⁺ type ohmic layer 124 having a depth of 5 μm and an impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed on the second main surface of the p type anode layer 110 by an impurity diffusion technique. It forms on the surface of the side (refer FIG.3 (e)).

(6) ^{p +} -type first ohmic region and ^{the p +} -type second ohmic region formation step Next, the impurity diffusion technique, for example, depth 3 [mu] m, ^{p +} -type first ohmic region of an impurity concentration of 1 × ¹⁰ 20 ^{cm -3} 118 and the p ⁺ -type second ohmic region 120 are formed on the surface of the p-type second base layer 114 on the first main surface side (see FIG. 4A).

(7) Step of forming n ⁺ -type cathode region Next, the n ⁺ -type cathode region 116 having a depth of 15 μm and an impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed on the first p-type second base layer 114 by an impurity diffusion technique. It is formed on the surface on the main surface side (see FIG. 4B).

(8) Groove Formation Step Next, a groove 140 having a depth reaching the n ⁻ -type first base layer 112 from the first main surface side of the semiconductor substrate is formed using a mask (not shown) (see FIG. 4C). .) The groove is formed by etching, for example. As an etchant, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (for example, HF: HNO ₃ : CH ₃ COOH = 1: 4: 1) is used.

(9) Passivation Layer Formation Step Next, a passivation layer 142 is formed inside the groove 140 (see FIG. 4D). This step is performed by electrodepositing and baking a glass material using electrophoresis.

(10) Electrode Formation Step Next, the oxide film 126 formed on the surface of the first main surface side of the p-type second base layer 114 is removed by etching, and then the n ⁺ -type cathode region 116 and the p ⁺ -type first layer are removed. the first surface and ^{the p +} -type surface of the second ohmic region 120 of the ohmic region 118, respectively to form a cathode electrode 128 and the gate electrode 130 composed of a laminated film such as aluminum film and the nickel film, the ^{p +} -type 2 ohmic region 124 An anode electrode 132 made of a laminated film of a titanium film, a nickel film, and a silver film is formed on the surface (see FIG. 4D).

  Through the steps as described above, the three-terminal thyristor 100 according to the first embodiment can be manufactured.

[Embodiment 2]
FIG. 5 is a cross-sectional view of a three-terminal thyristor 200 according to the second embodiment.

The three-terminal thyristor 200 according to the second embodiment basically has the same configuration as the three-terminal thyristor 100 according to the first embodiment, but the formation position of the p ⁺ -type buried diffusion layer is the three-terminal according to the first embodiment. This is different from the case of the thyristor 100. That is, in the three-terminal thyristor 200 according to the second embodiment, as shown in FIG. 5, the p ⁺ -type buried diffusion layer 222 is a boundary between the n ⁻ -type first base layer 212 and the p-type second base layer 214. It is formed at a position shallower than the portion.

As described above, the three-terminal thyristor 200 according to the second embodiment differs from the three-terminal thyristor 100 according to the first embodiment in the formation position of the p ⁺ -type buried diffusion layer, but in the p-type second base layer 214. In a region deeper than the n ⁺ -type cathode region 216, the p ⁺ -type first ohmic region 218, and the p ⁺ -type second ohmic region 220, as viewed in plan, as in the case of the three-terminal thyristor 100 according to the first embodiment. A p ⁺ type buried diffusion layer 222 containing an n type impurity at a concentration higher than that of the p type second base layer 214 is formed so as to extend from the p ⁺ type second ohmic region 220 to the n ⁺ type cathode region 216. Therefore, a gate trigger current flows through the n ⁺ buried diffusion layer 222. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, as in the case of the three-terminal thyristor 100 according to the first embodiment, the current density of the main current that flows at the time of turn-on is reduced, and the three-terminal thyristor having a structure that is not easily destroyed at the time of turn-on.

The three-terminal thyristor 200 according to the second embodiment has the same configuration as that of the three-terminal thyristor 100 according to the first embodiment except for the position where the p ⁺ type buried diffusion layer is formed. Among the effects of the three-terminal thyristor 100 according to FIG.

[Embodiment 3]
FIG. 6 is a cross-sectional view of a three-terminal thyristor 300 according to the third embodiment.

The three-terminal thyristor 300 according to the third embodiment basically has the same configuration as that of the three-terminal thyristor 100 according to the first embodiment, but further includes a p ⁺ -type coupling layer 323 containing a high-concentration p-type impurity. This is different from the case of the three-terminal thyristor 100 according to the first embodiment. That is, in the three-terminal thyristor 300 according to the third embodiment, as shown in FIG. 6, further comprising a ^{p +} -type connecting layer 323, and a ^{p +} -type second ohmic region 320 and the ^{p +} -type buried diffusion layer 322 The p ⁺ -type coupling layers 323 are connected. The p ⁺ type coupling layer 323 can be formed by a selective epitaxial growth technique.

As described above, the three-terminal thyristor 300 according to the third embodiment is different from the three-terminal thyristor 100 according to the first embodiment in that it further includes the p ⁺ -type coupling layer 323 containing a high-concentration p-type impurity. In the case of the three-terminal thyristor 100 according to the first embodiment, a region deeper than the n ⁺ -type cathode region 316, the p ⁺ -type first ohmic region 318, and the p ⁺ -type second ohmic region 320 in the p-type second base layer 314 is used. Similarly to p, the p-type impurity containing p-type impurities at a higher concentration than the p-type second base layer 314 so as to extend from the p ⁺ -type second ohmic region 320 to the n ⁺ -type cathode region 316 in plan view. ^{Since the +} type buried diffusion layer 322 is formed, a gate trigger current flows through the p ⁺ buried diffusion layer 322. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, as in the case of the three-terminal thyristor 100 according to the first embodiment, the current density of the main current that flows at the time of turn-on is reduced, and the three-terminal thyristor having a structure that is not easily destroyed at the time of turn-on.

In addition, since the three-terminal thyristor 300 according to the third embodiment further includes the p ⁺ type coupling layer 323, the gate trigger current efficiently flows into the p ⁺ type buried diffusion layer 322.

The three-terminal thyristor 300 according to the third embodiment, as in the case at a point other than that it further includes a p ⁺ -type connecting layer 323 containing a high concentration p-type impurity of the three-terminal thyristor 100 according to Embodiment 1 Therefore, the three-terminal thyristor 100 according to the first embodiment has a corresponding effect.

[Embodiment 4]
FIG. 7 is a cross-sectional view of a three-terminal thyristor 400 according to the fourth embodiment.

The three-terminal thyristor 400 according to the fourth embodiment basically has the same configuration as the three-terminal thyristor 100 according to the first embodiment, but the formation position of the p ⁺ -type buried diffusion layer is the three-terminal according to the first embodiment. This is different from the case of the thyristor 100. That is, in the three-terminal thyristor 400 according to the fourth embodiment, as shown in FIG. 7, p ⁺ -type buried diffusion layer 422 on the outer peripheral side of the p ⁺ -type second ohmic region 420 is not formed.

As described above, the three-terminal thyristor 400 according to the fourth embodiment differs from the three-terminal thyristor 100 according to the first embodiment in the formation position of the p ⁺ -type buried diffusion layer, but in the p-type second base layer 414. In a region deeper than the n ⁺ -type cathode region 416, the p ⁺ -type first ohmic region 418, and the p ⁺ -type second ohmic region 420, as in the case of the three-terminal thyristor 100 according to the first embodiment, A p ⁺ type buried diffusion layer 422 containing a p type impurity at a higher concentration than the p type second base layer 414 is formed to extend from the p ⁺ type second ohmic region 420 to the n ⁺ type cathode region 416. Therefore, a gate trigger current flows through the p ⁺ buried diffusion layer 422. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, as in the case of the three-terminal thyristor 100 according to the first embodiment, the current density of the main current that flows at the time of turn-on is reduced, and the three-terminal thyristor having a structure that is not easily destroyed at the time of turn-on.

The three-terminal thyristor 400 according to the fourth embodiment has the same configuration as that of the three-terminal thyristor 100 according to the first embodiment except for the position where the p ⁺ -type buried diffusion layer is formed. Among the effects of the three-terminal thyristor 100 according to FIG.

[Embodiment 5]
FIG. 8 is a cross-sectional view of a three-terminal thyristor 500 according to the fifth embodiment.

  The three-terminal thyristor 500 according to the fifth embodiment has basically the same configuration as the three-terminal thyristor 100 according to the first embodiment, but as shown in FIG. 8, is a planar type according to the first embodiment. This is different from the case of the three-terminal thyristor 100.

As described above, the three-terminal thyristor 500 according to the fifth embodiment is different from the three-terminal thyristor 100 according to the first embodiment in that it is a planar type, but the n ⁺ -type cathode region in the p-type second base layer 514. 516, ^{p +} -type region deeper than the first ohmic region 518 and the ^{p +} -type second ohmic region 520, as in the case of the three-terminal thyristor 100 according to the embodiment 1, ^{the p +} -type second in plan view Since the p ⁺ type buried diffusion layer 522 containing a p type impurity at a higher concentration than the p type second base layer 514 is formed so as to extend from the ohmic region 520 to the n ⁺ type cathode region 516, A gate trigger current flows through the p ⁺ buried diffusion layer 522. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, as in the case of the three-terminal thyristor 100 according to the first embodiment, the current density of the main current that flows at the time of turn-on is reduced, and the three-terminal thyristor having a structure that is not easily destroyed at the time of turn-on.

  Since the three-terminal thyristor 500 according to the fifth embodiment has the same configuration as that of the three-terminal thyristor 100 according to the first embodiment except for the planar type, the three-terminal thyristor according to the first embodiment. 100 has a corresponding effect among the effects of 100.

[Embodiment 6]
FIG. 9 is a diagram for explaining a three-terminal thyristor 600 according to the sixth embodiment. 9A is a plan view of the three-terminal thyristor 600, and FIG. 9B is a cross-sectional view taken along line A1-A1 of FIG. 9A. In FIG. 9A, the cathode electrode 628, the gate electrode 630, and the oxide film 626 are not shown.

The three-terminal thyristor 600 according to the sixth embodiment basically has the same configuration as the three-terminal thyristor 100 according to the first embodiment, but the formation position of the p ⁺ -type buried diffusion layer is the three-terminal according to the first embodiment. This is different from the case of the thyristor 100. That is, in the three-terminal thyristor 600 according to the sixth embodiment, as shown in FIG. 9, the p ⁺ -type buried diffusion layer 622 is formed on the entire surface of the p-type second base layer 614 in plan view. .

As described above, the three-terminal thyristor 600 according to the sixth embodiment is different from the three-terminal thyristor 100 according to the first embodiment in the formation position of the p ⁺ -type buried diffusion layer, but in the p-type second base layer 614. n ⁺ -type cathode region 616, ^{p +} -type first ohmic region 618 and the ^{p +} -type second region deeper than the ohmic region 620, planarly viewed ^{p +} -type second ohmic region 620 of ^{n +} -type cathode region 616 Since the p ⁺ type buried diffusion layer 622 containing a p type impurity at a concentration higher than that of the p type second base layer 614 is formed so as to extend through the p ⁺ type second base layer 614, the p ⁺ type buried diffusion layer 622 passes through the p ⁺ buried diffusion layer 622. As a result, a gate trigger current flows. For this reason, as a result of the gate trigger current flowing through a wider path, the main current is initially fired in a wider range. As a result, as in the case of the three-terminal thyristor 100 according to the first embodiment, the current density of the main current that flows at the time of turn-on is reduced, and the three-terminal thyristor having a structure that is not easily destroyed at the time of turn-on.

  In addition, according to the three-terminal thyristor 600 according to the fifth embodiment, there is an effect that the gate trigger current flows through a wider path.

The three-terminal thyristor 600 according to the sixth embodiment has the same configuration as that of the three-terminal thyristor 100 according to the first embodiment except for the position where the p ⁺ type buried diffusion layer is formed. Among the effects of the three-terminal thyristor 100 according to FIG.

  Although the three-terminal thyristor of the present invention has been described based on the above embodiments, the present invention is not limited to the above embodiments, and can be implemented in various modes without departing from the scope of the invention. For example, the following modifications are possible.

(1) In each of the above-described embodiments, the present invention has been described taking the reverse blocking three-terminal thyristor as an example, but the present invention is not limited to this. The present invention can also be applied to reverse conducting three-terminal thyristors and other three-terminal thyristors.

(2) In each of the above-described embodiments, the first conductivity type is p-type and the second conductivity type is n-type. However, the invention of the present invention is not limited to this. The first conductivity type may be n-type and the second conductivity type may be p-type.

100, 200, 300, 400, 500, 600, 900 ... 3-terminal thyristor, 110, 210, 310, 410, 510, 610, 910 ... p-type anode layer, 112, 212, 312, 412, 512, 612, 912 ... n ^- type base layer, 114, 214, 314, 414, 514, 614, 914 ... p-type base layer, 116, 216, 316, 416, 516, 616, 916 ... n ⁺ -type cathode region, 118, 218, 318,418,518,618,918 ... ^{p +} -type first ohmic region, 120,220,320,420,520,620,920 ... ^{p +} -type second ohmic region, 122,222,322,422,522, 622 ... ^{n +} -type buried diffusion layer, 124,224,324,424,524,624,924 ... ^{p +} type O Mic layer, 126, 226, 326, 426, 526, 626, 926 ... oxide film, 128, 228, 328, 428, 528, 628, 928 ... cathode electrode, 130, 230, 330, 430, 530, 630, 930 ... Gate electrode, 132,232,332,432,532,632,932 ... Anode electrode, 323 ... p ⁺ type coupling layer

Claims (9)

A first conductor type anode layer;
A first base layer of a second conductivity type located on the first main surface side in the anode layer;
A second base layer of a first conductivity type located on the first main surface side in the first base layer;
A second conductive type cathode region, a first conductive type first ohmic region, and a first conductive type second ohmic region formed on a surface of the second base layer;
An anode electrode is formed on the second main surface side of the anode layer,
A cathode electrode is formed on the first main surface side in the cathode region and the first ohmic region,
In the three-terminal thyristor in which a gate electrode is formed on the first main surface side in the second ohmic region,
In the second base layer, the cathode region, the first ohmic region, and a region deeper than the second ohmic region extend from the second ohmic region to the cathode region in plan view. 2. A three-terminal thyristor, wherein a buried diffusion layer of the first conductivity type containing a first conductivity type impurity having a higher concentration than the two base layers is formed by an epitaxial growth technique . The three-terminal thyristor according to claim 1,
The three-terminal thyristor, wherein the buried diffusion layer is formed at a boundary portion between the first base layer and the second base layer. The three-terminal thyristor according to claim 1,
The three-terminal thyristor, wherein the buried diffusion layer is formed at a position shallower than a boundary portion between the first base layer and the second base layer. The three-terminal thyristor according to any one of claims 1 to 3,
The three-terminal thyristor is characterized in that the impurity concentration of the buried diffusion layer is set in a range of 5 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ . The three-terminal thyristor according to any one of claims 1 to 4,
The three-terminal thyristor is characterized in that an interval between the second ohmic region and the buried diffusion layer is set in a range of 20 μm to 40 μm . The three-terminal thyristor according to any one of claims 1 to 5,
The three-terminal thyristor, wherein the buried diffusion layer is formed on the entire surface of the second base layer in plan view. In the 3 terminal thyristor in any one of Claims 1-6,
The three-terminal thyristor, wherein the buried diffusion layer is partially formed in the second base layer as viewed in plan. In the 3 terminal thyristor in any one of Claims 1-7,
The three-terminal thyristor, wherein the second ohmic region and the buried diffusion layer are coupled by a first conductivity type coupling layer containing a high concentration of first conductivity type impurities. The three-terminal thyristor according to any one of claims 1 to 8,
The three-terminal thyristor has a short gate structure.

Images