JP5553797B2 - Data recording method for semiconductor memory device - Google Patents

Description

  The present invention relates to a data recording method for a semiconductor memory device, and more particularly to a rewritable nonvolatile solid-state memory element (phase change memory) that stores information by using a substance whose electrical resistance reversibly changes when a current is passed. The present invention relates to a technique that is effective when applied to a data recording method of a semiconductor memory device.

  In recent years, resistance random access memory (ReRAM) has been studied as a semiconductor memory to replace flash memory, which is approaching the limit of miniaturization. As an example, a chalcogenide material is used as a recording material. Phase change memory is actively researched.

The phase change memory is a non-volatile solid-state memory that stores information using the property that a phase change material such as Ge ₂ Sb ₂ Te _{5 that} is a recording material has a high resistance in an amorphous state and a low resistance in a crystalline state. The basic element structure is such that a phase change film is sandwiched between a pair of metal electrodes.

  Data is read by applying a potential difference across the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element. Data is rewritten by changing the state of the phase change film between an amorphous state and a crystalline state by Joule heat generated by current.

  The reset operation, that is, the operation of changing the phase change film to the high resistance amorphous state is performed by flowing a relatively large current to dissolve the phase change film, and then rapidly decreasing the current by rapidly decreasing the current. On the other hand, the set operation, that is, the operation of changing the phase change film to a low-resistance crystalline state is performed by passing a relatively small current and maintaining the phase change film at the crystallization temperature or higher.

  The phase change memory described above is suitable for miniaturization because the volume of the phase change film decreases as the miniaturization proceeds and the current required to change the resistance decreases.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2010-165982) discloses a technique for improving the degree of integration of a phase change memory, in which a plurality of layers that penetrate all layers in a stacked structure in which a plurality of gate electrodes and insulating films are alternately stacked. A phase change memory structure is disclosed in which through holes are formed by batch processing, and a gate insulating film, a channel layer of a current path switching transistor, and a phase change film are formed inside each through hole.

  In Patent Document 2 (Japanese Patent Laid-Open No. 2009-117854), when a phase change film is reset (high resistance), a short voltage pulse having a pulse width of about 10 ns is continuously applied a plurality of times. A data recording method for a phase change memory is disclosed which prevents overheating of the change film.

JP 2010-165982 A JP 2009-117854 A

  In the phase change memory described in Patent Document 1, in order to increase the capacity, a phase change film and a current switching switch (MOS transistor) formed in parallel electrically are set as one set to correspond to a memory bit. Yes. For a structure in which a plurality of memory bits are electrically connected in series (hereinafter referred to as a memory array), a pulse current source is connected by a selection operation using a word line and a bit line, and a current pulse from the pulse current source is connected. To record data.

  In addition, the polycrystalline silicon constituting the current channel of the current switching switch and the phase change material are both formed as a continuous thin film, thereby simplifying the device manufacturing process and increasing the capacity. In such an element structure, it is possible to achieve both large capacity and low cost by microfabrication and an increase in the number of memory bits included in the memory array.

  In the phase change memory having the above-described structure, when the number of memory bits in the memory array is increased to increase the capacity, the load resistance and load capacitance of the pulse current source are increased, and the applied pulse current It is obvious that it is difficult to generate a short current pulse because of the deterioration of the frequency characteristics.

  On the other hand, the recording method in which a short current pulse is continuously energized as described in Patent Document 2 to perform a reset operation surely suppresses overheating of the phase change material and improves the reliability of the phase change memory. Have. However, this recording method has an important limitation condition regarding the pulse interval which is not described in Patent Document 2. Here, this limitation condition is clarified through the experimental results of the phase change memory sample, and the technical problems derived therefrom are described.

FIG. 6 is a schematic diagram showing a configuration of a phase change memory sample. Here, a 100 nm thick silicon oxide film 31 is formed on the semiconductor substrate 10 made of a 0.5 mm thick silicon single crystal, and a lower electrode 32 made of a 100 nm thick tungsten film is formed thereon. Further, a silicon oxide film 33 having a thickness of 150 nm was formed on the lower electrode 32, and a tungsten plug 34 was formed inside a hole formed in a part of the silicon oxide film 33. The diameter of the tungsten plug 14 is 50 nm to 1000 nm. Thereafter, a phase change film 35 made of a 50 nm thick Ge ₂ Sb ₂ Te ₅ film, an upper electrode 36 made of a 50 nm thick tungsten film, and a 10 μm thick silicon oxide film 37 were sequentially formed on the silicon oxide film 33.

  FIG. 7 shows the experimental results showing the resistance change of the phase change memory sample by the continuous pulse application. Here, the results when the diameter of the tungsten plug 34 is 200 nm, the interval (pulse period) of each pulse is 100 μs, and the number of pulses to be continuously applied are 1, 2, 4, 8, 16, 32 are shown.

  FIG. 7A shows the experimental results when the pulse width is 5 ns. It can be seen that as the number of continuously applied current pulses increases to 1, 2, 4, and 8, a higher resistance (reset operation) can be realized with a smaller current. When the number of pulses is 8, 16, or 32, the pulse current value necessary for increasing the resistance is substantially constant. When the number of pulses is 1, the threshold current for increasing resistance is about 35 mA, whereas when the number of pulses is 8 or more, the threshold current is about 12 mA, which is about 1/3. Reduced to

  FIG. 7B shows the experimental results when the pulse width is 20 ns. Similar to the case where the pulse width is 5 ns, the effect of reducing the threshold current with higher resistance is seen as the number of pulse currents applied continuously increases. However, the reduction effect is smaller than that when the pulse width is 5 ns. Become.

  FIG. 7C shows the experimental results when the pulse width is 100 ns. Regardless of the number of pulses, the threshold current for increasing the resistance is almost constant, and the effect of increasing the sensitivity, that is, the effect of suppressing overheating is hardly seen.

  The mechanism of the sensitivity enhancement effect obtained in FIG. 7A will be schematically described with reference to FIG. As a result of the thermal simulation of this sample, the temperature distribution in the phase change film 35 by the first current pulse has a maximum value in the region slightly above the tungsten plug 14, and the first amorphous region is formed in this portion. Subsequently, when the first formed amorphous region has a low temperature due to the application of the second current pulse, the current flows avoiding this region. Therefore, the additional formed amorphous region is the same as the first formed amorphous region. It becomes the periphery. Then, by repeating the application of the current pulse, when the amorphous region is expanded until the tungsten plug 14 is finally covered, the element resistance is greatly observed, and the reset operation is completed.

FIG. 9 is an experimental result showing the temperature dependence of the electrical resistivity of the phase change film made of Ge ₂ Sb ₂ Te ₅ measured with another sample.

  In this experiment, the electrical resistivity was measured while raising the temperature of the phase change film in the initial amorphous state from room temperature at a constant rate of 10 ° C. per minute. As seen in the figure, from room temperature to about 150 ° C., after a reversible temperature-dependent region in which the electrical resistivity decreases to about 1/30 with respect to the temperature rise, the resistance is further reduced by crystallization, and further A decrease in electrical resistance was observed. That is, it can be seen that the electrical resistance of the phase change film in the amorphous state has a large temperature dependence even at a temperature lower than the crystallization temperature.

  In order to efficiently implement the high-sensitivity recording mechanism by the additional process of the amorphous region described in FIG. 8, the temperature of the amorphous region is sufficiently low so that the pulse current selectively flows so as to avoid it. There is a need. Even if the pulse width of the pulse current is long and the current flows avoiding the first amorphous region, if the temperature rise due to Joule heat generation in the adjacent crystal region is transmitted to the first amorphous region by heat conduction, the resistance decreases, and high sensitivity The effect is lost. This defines the pulse width dependency shown in FIG. In addition, even if the pulse width is sufficiently short and the heat diffusion time that the heat generation of the adjacent crystal region is transmitted is less than or equal to the current, if the temperature of the amorphous region is high before the pulse current is applied, the current Since it also flows in the amorphous region, the effect of increasing sensitivity is lost.

  In order to quantify the influence of the latter, an experiment was performed in which the pulse period was continuously changed in the case where the pulse width was 5 ns. The result is shown in FIG.

  As can be seen from the figure, the above-described operation principle is reflected, and it can be seen that the sensitivity enhancement effect is hardly obtained when the pulse interval is 20 ns, compared with the case where the pulse interval is 10 ns. This is because the formed amorphous region is not sufficiently cooled. The remarkable sensitivity enhancement effect appears when the pulse period is 100 ns or more. From the result of the thermal simulation, it is predicted that the temperature of the amorphous region at this time is cooled to 70 ° C. or less, and from the result of FIG. 9, the resistance in the amorphous state may be sufficiently higher than the crystalline state. I understand.

  From the above results, when the diameter of the tungsten plug 14 is 200 nm, the pulse width is 5 ns, the pulse interval is 100 ns, the number of pulses is 8, and the effect of suppressing overheating and increasing the sensitivity of the phase change material by continuous pulse application is obtained. As a result, the time required for one reset operation is 800 ns, which takes eight times as long as the reset operation by the 100 ns pulse shown in FIG. 7, for example. This indicates that the data recording transfer rate of the phase change memory is reduced to 1/8.

  Based on the above examination results, problems to be solved by the present invention are summarized. In order to efficiently add an amorphous region in the phase change film by the continuous pulse method, it is necessary to keep the temperature of the amorphous region low. However, since it is necessary to generate a continuous current pulse under the condition that the tungsten plug diameter is 200 nm and the pulse width is about 5 ns and the pulse interval is about 100 ns, a decrease in data transfer rate is inevitable. .

  When the size of the memory bit is reduced by miniaturization, it is needless to say that a shorter pulse width is required because the time for thermal diffusion from the crystalline region to the amorphous region due to thermal conduction is shortened as described above. On the other hand, it has a memory array structure in which a plurality of memory bits in which a current switching switch and a phase change film are formed in parallel are electrically arranged in series, and one memory array is formed by one pulse current source. In the phase change memory of the driving method, when the number of memory bits in the memory array is increased to increase the capacity, the frequency characteristic of the pulse current source is deteriorated and a short current pulse of less than 5 ns may be generated. It becomes difficult.

  As described above, combining the phase change memory structure suitable for increasing the capacity as described in Patent Document 1 and the recording method described in Patent Document 2 and preventing a decrease in data transfer speed are not possible. Difficulty has been found by the inventors.

  An object of the present invention is to provide a phase change memory having a memory array structure in which a plurality of memory bits in which a current switching switch and a phase change film are electrically parallel are arranged in series. It is an object of the present invention to provide a data recording method for a phase change memory that realizes a high transfer speed and high reliability by reducing a write current or suppressing cross erase.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In order to solve the above-described problems, the present invention focuses on the frequency characteristics of the control voltage of the MOS transistor constituting the memory bit current switching switch. Generally, this is realized by controlling the gate voltage or the like. However, since this may be voltage control, it can be formed with a small mounting size, that is, a small capacitance compared to the pulse current source.

  In addition, since the magnitude of the gate voltage is a design matter, it is possible to improve the frequency characteristics of the gate voltage control system 10 times or more as compared with the pulse current source in combination with reducing the magnitude. In this case, the pulse current source having low frequency characteristics is held in an ON state. Next, by turning off one of the gate electrodes of the plurality of memory bits for a period of about 5 ns, a short pulse current is caused to flow through the corresponding phase change film. Next, the gate electrode of another memory bit is similarly turned off for a period of about 5 ns, thereby passing a short current through the corresponding phase change film.

  By repeating the above process and passing a short current through the required phase change film, another memory bit is transferred during the aforementioned pulse interval corresponding to the standby period for sufficiently increasing the temperature of the amorphous region. The parallel data recording to the memory array is effectively performed by applying the pulse current.

  As described above, since the current pulse interval can be effectively concealed by parallel processing, it is possible to avoid a decrease in data transfer rate. According to the above result, if a pulse width = 5 ns and a pulse interval = 100 ns are required, the pulse interval can be completely hidden in principle if the memory array has 20 or more memory bits. Writing to 20 memory bits can be completed in 5 ns × 8 × 20 = 800 ns. Further, when a pulse of 100 ns is used, the data transfer rate can be improved as compared with 100 ns × 20 = 2000 ns.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In a phase change memory with a memory array structure in which a switch for current switching and a phase change film are electrically formed in parallel and arranged in series, overheating is suppressed and sensitivity is increased by applying a continuous pulse current. Therefore, it is possible to improve both the transfer rate performance and the reliability.

It is a schematic sectional drawing which shows the memory part of the semiconductor memory device which is one embodiment of this invention. It is sectional drawing which expands and shows a part of FIG. It is an equivalent circuit diagram which shows the operation | movement principle of a memory bit. It is an equivalent circuit diagram explaining a data writing method of a memory bit. 6 is a timing chart illustrating a method for writing data in memory bits. It is a schematic diagram which shows the structure of the phase change memory sample used for experiment. (A), (b), (c) is a graph of the experimental result which shows the resistance change of a phase change memory sample. It is a schematic diagram explaining the mechanism of the high sensitivity effect obtained by Fig.7 (a). Ge is a graph of experimental results showing the ₂ Sb ₂ Temperature dependence of the electrical resistivity of the phase change film made of Te _5. It is a graph of the experimental result which changed the pulse period continuously.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the drawings describing the embodiments, hatching may be omitted even in a cross-sectional view for easy understanding of the configuration.

  FIG. 1 is a schematic cross-sectional view showing a memory portion of the semiconductor memory device of the present embodiment, and FIG. 2 is an enlarged cross-sectional view showing a part of FIG. 1 (a rectangular region surrounded by a two-dot chain line). .

  For example, an n-type semiconductor region 11 serving as a contact layer on the substrate side of the memory bit is formed on the main surface of the semiconductor substrate 10 made of p-type single crystal silicon. Further, on the upper portion of the n-type semiconductor region 11, for example, a five-layer interlayer insulating film made of silicon oxide (first interlayer insulating film 12, second interlayer insulating film 13, third interlayer insulating film 14, fourth interlayer insulating film) 15 and a fifth interlayer insulating film 16) are laminated.

  Between the first interlayer insulating film 12 and the second interlayer insulating film 13, between the second interlayer insulating film 13 and the third interlayer insulating film 14, and between the third interlayer insulating film 14 and the fourth interlayer insulating film 15. Is formed with a gate electrode 20 of a MOS transistor constituting a current switching switch. Further, between the fourth interlayer insulating film 15 and the fifth interlayer insulating film 16, a gate electrode 21 of a MOS transistor constituting a memory array selection switch is formed. The gate electrodes 20 and 21 are made of, for example, n-type polycrystalline silicon and function as the word line WL.

  The fifth interlayer insulating film (first interlayer insulating film 12, second interlayer insulating film 13, third interlayer insulating film 14, fourth interlayer insulating film 15, and fifth interlayer insulating film 16) includes a fifth interlayer insulating film. A plurality of holes 22 reaching the upper surface of the n-type semiconductor region 11 from the upper surface of the film 16 are formed. The side walls of each hole 22 have a structure in which the respective cross sections of the gate electrodes 20 and 21 are exposed.

  A gate insulating film 23 of a MOS transistor (current switching switch and memory array selection switch) is formed on the side wall of each hole 22. The gate insulating film 23 is made of, for example, silicon oxide.

Inside each hole 22 described above, an n-type polycrystalline silicon film 24 constituting a current channel of a MOS transistor (current switching switch and memory array selection switch) is formed inside the gate insulating film 23. . In each hole 22, a phase change film 25 made of, for example, Ge ₂ Sb ₂ Te ₅ is formed further inside the n-type polycrystalline silicon film 24. Since the MOS transistors constituting the memory array selection switch only need to turn on / off the current by controlling the voltage of the gate electrode 21, the phase change film 25 is not formed in the vicinity thereof.

  Bit lines BL and metal wirings 26 and 27 are formed on the fifth interlayer insulating film 16. The bit line BL is disposed at the upper end of the hole 22 and is electrically connected to the n-type polycrystalline silicon film 24 inside the hole 22. The metal wiring 26 is electrically connected to the gate electrode 21 of the memory array selection switch through a plug 28 formed in a part of the interlayer insulating film. Further, the metal wiring 27 is electrically connected to the gate electrode 20 of the current switching switch through a plug 29 formed in a part of the interlayer insulating film. The bit line BL, the metal wirings 26 and 27, and the plug 28 are made of a metal material such as tungsten or titanium nitride. Each of the bit line BL, the metal wirings 26 and 27, and the n-type semiconductor region 11 is electrically connected to a peripheral circuit portion formed in a region (not shown) of the semiconductor substrate 10.

  As shown in FIG. 2 (enlarged view showing an area corresponding to two memory bits), the phase change memory includes a current changeover switch (MOS) having a phase change film 25 formed in parallel electrically and a gate electrode 20. Transistor) as a set to correspond to one memory bit. As shown in FIG. 1, a plurality of memory bits arranged along the vertical direction of the hole 22 are electrically connected in series (memory array).

  FIG. 1 shows an example in which three memory bits are connected in series to one memory array, but more memory bits are connected in series in an actual memory array. . In the memory portion of the semiconductor substrate 10, a plurality of memory arrays configured as described above are arranged in the X direction (first direction) horizontal to the main surface of the semiconductor substrate 10 and the Y direction (second direction) orthogonal thereto. ) In a matrix. Such a structure of the memory portion can be manufactured using a known manufacturing technique, for example, a manufacturing technique described in Patent Document 1.

  FIG. 3 shows the operation principle of the memory bit. First, a predetermined memory bit is selected by a selection operation using the word line WL and the bit line BL. Then, a control voltage is applied to the gate electrode 20 of the selected memory bit to turn off the MOS transistor and increase the resistance of the current channel (n-type polycrystalline silicon film 24) so that no current flows to the MOS transistor side. As a result, a current is passed through the phase change film 25 connected in parallel to the MOS transistor to operate the memory bit.

  Next, a method for recording data in the phase change memory according to the present embodiment will be described. FIG. 4 shows a memory bit in which one memory array shown in FIG. 1, that is, a current switching switch SW composed of MOS transistors, and a phase change film 25 as an information holding unit are electrically formed in parallel. An equivalent circuit of a memory array in which a plurality (bit0, bit1, bit2,...) Are arranged in series is shown. Here, the current amount of the current pulse flowing from the pulse current source 40 in the peripheral circuit section is I, and the gate control voltage to be applied to the gate electrodes (word lines WL0, WL1, WL2,...) Of the current switching switches SW. V0, V1, V2,...

  FIG. 5 is a timing chart for explaining a data writing method at the time of resetting. As shown in the figure, when a current pulse of the amount of current (I) generated from the pulse current source is supplied to the memory array, the frequency characteristics are lowered, so that the rise time and the rise time become longer. Therefore, the effect of the continuous current pulse method described above cannot be sufficiently exhibited.

  Therefore, in this embodiment, the gate control voltages (V0, V1, V2,...) Having high frequency characteristics are sequentially set to the LOW state within the period in which the current pulse is turned on, and the MOS transistor (current switching switch) ) Are sequentially turned OFF to switch the path, and data is written by sequentially passing current through the phase change film (25) constituting the data bits (bit0, bit1, bit2,...). The period during which current flows through the phase change film (25) of each data bit (bit0, bit1, bit2,...) Is limited to the period during which the gate control voltage (V0, V1, V2,...) Of the corresponding MOS transistor is LOW. Therefore, the effect of the continuous current pulse method can be sufficiently exhibited.

  Further, for example, each gate control voltage (V1, V2,...) Is supplied so that the current flows in the data bits (bit1, bit2,...) Until the second current flows in the phase change film (25) of the data bit (bit0). ...) is controlled. As a result, the current flowing through the phase change film (25) constituting each data bit (bit0, bit1, bit2,...) Is a continuous current whose pulse width is necessary and sufficiently narrow and the pulse period is necessary and sufficiently wide. The pulse method can satisfy the conditions for preventing overheating and achieving high sensitivity. At this time, each pulse cycle can be effectively used as a period for supplying a current to other data bits, so that a decrease in transfer rate can be prevented at the same time.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor memory device having a phase change memory.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 N type semiconductor region 12 1st interlayer insulation film 13 2nd interlayer insulation film 14 3rd interlayer insulation film 15 4th interlayer insulation film 16 5th interlayer insulation film 20, 21 Gate electrode 22 Hole 23 Gate insulation film 24 n-type polycrystalline silicon film 25 phase change films 26 and 27 metal wiring 31 silicon oxide film 32 lower electrode 33 silicon oxide film 34 tungsten plug 35 phase change film 36 upper electrode 37 silicon oxide film 40 pulse current source BL bit line SW current switching Switch WL Word line

Claims (5)

A memory unit is disposed in a first region of a main surface of the semiconductor substrate, and a peripheral circuit unit is disposed in a second region of the main surface;
The memory unit includes a plurality of information holding units configured of a phase change material, and a current switching switch that is electrically connected in parallel to the information holding unit and switches a current path that flows through the phase change material. A memory array in which memory bits are electrically connected in series is formed,
In the peripheral circuit portion, a data recording method for a semiconductor memory device in which a pulse current source for supplying a pulse current to the memory array is formed,
During the generation period of the pulse current generated by the pulse current source, the current switching switch of each of the plurality of memory bits is sequentially turned on / off, and at least one memory of the plurality of memory bits A data recording method for a semiconductor memory device, wherein data is sequentially written into the plurality of memory bits by passing a current having a period shorter than a generation period of the pulse current through the information holding unit of the bit.   The memory array is provided in a direction perpendicular to a main surface of the semiconductor substrate, and the plurality of memory bits are operated by causing the pulse current to flow through the memory array along the vertical direction. 2. A data recording method for a semiconductor memory device according to claim 1, wherein:   2. The semiconductor memory device according to claim 1, wherein a plurality of said memory arrays are arranged in a matrix along a first direction horizontal to said main surface of said semiconductor substrate and a second direction orthogonal thereto. Data recording method.   2. The data recording method for a semiconductor memory device according to claim 1, wherein the current switching switch is formed of a MOS transistor having a gate electrode formed of a polycrystalline silicon film.   2. The data recording method for a semiconductor memory device according to claim 1, wherein the phase change material is made of a chalcogenide material containing Ge, Sb, and Te.