JP5555871B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor element from a semiconductor substrate having at least a p-type semiconductor region and an n-type semiconductor region, and a semiconductor element.

A vertical structure having a structure in which a p-type semiconductor layer (hereinafter also referred to as “p-type layer”) and an n-type semiconductor layer (hereinafter also referred to as “n-type layer”) are stacked on a substrate. In the type semiconductor element, a current flows in a direction perpendicular to the pn junction surface in the on state, and a depletion layer spreads on both sides of the pn junction surface in the off state. In power semiconductor devices such as power transistors and power MOSFETs to which a high voltage of several hundred volts or more is applied, the breakdown voltage of the pn junction is important. In particular, in a vertical power semiconductor device, a dielectric breakdown voltage is generated at the element end face. Therefore, various attempts have been made to increase the dielectric breakdown strength of the element end face of the pn junction.
One of them is a method of inclining the element end face of the pn junction (see Non-Patent Document 1, Fig. 7b). When the pn junction is inclined, both ends of the depletion layer are separated from each other, so that the leakage current generated in the depletion layer can be reduced and the dielectric breakdown strength is improved.
When the element end face of the pn junction is inclined, the depletion layer is separated from the both ends as the inclination angle increases. However, in order to ensure a large inclination angle at the pn junction, it is necessary to sharpen the element end face, which has been an obstacle to downsizing the power semiconductor element.
In addition, there is a method in which a peripheral side surface of a diode in which a pn junction is formed between a p-type layer and an n-type layer is formed in a concave curve (see Patent Document 1 and FIG. 2). By forming the curved apex of the peripheral side surface on the low impurity concentration layer side of the p-type layer and the n-type layer, surface discharge can be prevented. However, it has been difficult to perform bending at a desired position and size.
Further, it is disclosed that a substrate wafer is divided into a plurality of substrate chips by a plasma etching method in which a film forming process and an etching process are repeated (Patent Document 2).

Japanese Utility Model Publication No. 48-40370 JP 2002-93749 A

B. Jayant Baliga, B. Tech., M.S., Ph.D., "High-voltage device termination techniques", IEE Proc., Vol.129, pt I, No.5, October 1982

  SUMMARY OF THE INVENTION The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device comprising a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region, and to improve the withstand voltage at the pn junction boundary, and such a semiconductor. It is to provide an element.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes:
A method of manufacturing a semiconductor element from a semiconductor substrate having at least a p-type semiconductor region and an n-type semiconductor region,
A surface where a pn junction boundary is exposed is formed on the semiconductor substrate by plasma etching, and the exposed surface extends to the pn junction boundary in a direction parallel to the interface between the p-type semiconductor region and the n-type semiconductor region. A creeping extension groove is formed.

  The plasma etching is characterized in that a film forming process and an etching process are alternately repeated.

  Further, the first plasma etching performed from the surface of the semiconductor substrate to immediately before the region including the pn junction boundary and the second plasma etching for forming the creeping extension groove in the region including the pn junction boundary include a gas flow rate. The conditions determined by one or a combination of high frequency output, discharge frequency, and processing time are different.

The semiconductor device manufactured by the present invention has a large number of continuous arc-shaped grooves parallel to the pn junction boundary portion on the surface where the pn junction boundary portion is exposed, and the pn junction boundary portion of the arc-shaped grooves is formed at the pn junction boundary portion. The arcuate groove located has a creeping distance longer than other arcuate grooves.

  According to the present invention, the surface where the pn junction boundary is exposed by plasma etching is formed, and the creeping extension groove is formed in a region including the pn junction boundary of the exposed surface, thereby increasing the creepage distance of the depletion layer. Therefore, the withstand voltage of the semiconductor element is improved. According to the present invention, the surface where the pn junction boundary portion is exposed has a large number of continuous arc-shaped grooves parallel to the pn junction boundary portion, and the region including the pn junction boundary portion in the arc-shaped groove. Since the positioned arc-shaped groove has a creeping distance longer than the other arc-shaped grooves, it is not necessary to incline the region including the pn junction. For this reason, the withstand voltage of the semiconductor element can be improved and the element can be miniaturized.

1 is an overall schematic configuration diagram of an inductively coupled plasma processing apparatus according to an embodiment of the present invention. The figure which shows the gas introduction path | route and gas discharge path | route of a process chamber. The figure which shows an example of the structure (a) of a semiconductor substrate of this invention, and a semiconductor element (b). The figure which shows an example of the plasma conditions in the formation process of an arc-shaped groove. The figure which shows an example of the plasma conditions in the formation process of a creeping extension groove | channel. 4 is an electron microscopic image of an arc-shaped groove of Example 1. FIG. The electron microscope image of the arc-shaped groove | channel of Example 2. FIG.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 and 2 show a plasma processing apparatus 1 according to this embodiment. The plasma processing apparatus 1 includes a processing chamber 2 and an inductive coupling coil 4 provided in the upper portion of the processing chamber 2 for generating plasma in the processing chamber 2. A lower electrode 6 is provided in the processing chamber 2.

An electrostatic chuck 8 is provided on the lower electrode 6, and the semiconductor substrate S placed on the lower electrode 6 is attracted and held by the electrostatic chuck 8.
A heat transfer gas supply pipe 12 for supplying a heat transfer gas to the refrigerant circulation pipe 10 and the electrostatic chuck 8 is disposed in the lower electrode 6. The processing substrate disposed on the lower electrode 6 is maintained at a predetermined temperature (for example, 20 ° C.) by the refrigerant circulating in the refrigerant circulation pipe 10 and the heat transfer gas (for example, helium gas) supplied through the heat transfer gas supply pipe 12. The

  An etching gas (for example, SF6), a film forming gas (C4F8), and an oxygen gas are respectively introduced into the processing chamber 2 through gas introduction pipes 14, 16, and 18. Mass flow controllers 141 and 161 and three-way valves 142 and 162 are provided in the introduction pipes 14 and 16 for the etching gas and the film forming gas. The oxygen gas introduction pipe 18 is provided with a mass flow controller 181 and a three-way valve 182. The processing chamber 2 is provided with a load lock chamber 20. Bypass pipes 24, 26, 27 connected to the exhaust pipe 22 of the load lock chamber 20 are connected to the three-way valves 142, 162, 182 of the gas introduction pipes 14, 16, 18.

  Further, a vacuum pump 30 and a vacuum pump 31 are provided in the exhaust pipe 28 of the processing chamber 2 and the exhaust pipe 22 of the load lock chamber 20, respectively. The inside of the processing chamber 2 is maintained in a predetermined reduced pressure atmosphere by the vacuum pump 30. The inside of the load lock chamber 20 is maintained in a predetermined reduced pressure atmosphere by the vacuum pump 31, and gas that has not been introduced into the processing chamber 2 is discharged by the three-way valve 142 or 162.

  A cylindrical dielectric 32, a Faraday shield 34 integrally formed on the outer peripheral surface of the dielectric 32, and an inductive coupling coil 4 wound around the outer periphery of the Faraday shield 34 are disposed at the upper portion of the processing chamber 2. Yes. A high frequency power supply 38 is connected to the inductive coupling coil 4 via a matching unit (matching box) 37. The Faraday shield 34 is provided with a cut so that the Faraday shield 34 does not go around the outer periphery of the dielectric 32. As a result, a current opposite to the current flowing through the inductive coupling coil 4 does not flow through the Faraday shield 34.

  High frequency power is applied to the lower electrode 6 from a high frequency power source 13. The driving of the mass flow controllers 141, 161, 181, valves 142, 162, 182, high frequency power supplies 13, 38, vacuum pump 30 and the like is controlled by a control device (not shown).

Here, the semiconductor element S1 formed by dividing the semiconductor substrate S to be processed and the semiconductor substrate S will be described. As shown in FIG. 3, the semiconductor substrate S has a structure in which at least an n-type semiconductor region 103 and a p-type semiconductor region 105 are stacked on a conductive substrate 101. In order to adjust the spread of the depletion layer and increase the withstand voltage of the semiconductor element, the n-type semiconductor region 103 includes an n ⁺ semiconductor layer having a high n-type impurity concentration and an n ⁻ semiconductor having a lower n-type impurity concentration. It may be composed of layers. In this case, the n ⁻ semiconductor layer is provided on the p-type semiconductor region side.

In the semiconductor substrate S, a surface where the pn junction boundary is exposed is formed by plasma etching, and a creeping extension groove is formed in a region including the pn junction boundary in the exposed surface. Here, the region including the pn junction boundary means a region including the pn junction boundary and extending to both sides of the p-type semiconductor layer and the n-type semiconductor layer.
The number of creeping extension grooves formed in the region including the pn junction boundary may be one or more, and a plurality of creeping extension grooves are formed in that the creepage distance of the element end face is increased and the withstand voltage is improved. It is preferable to do. When forming a plurality of creeping extension grooves, it is preferable to form a plurality of creeping extension grooves on the n-type semiconductor region side (particularly the n ⁻ semiconductor region) in the region including the pn junction boundary.

  The exposed surface can be formed by performing plasma etching from the surface of the semiconductor substrate S to at least the pn junction boundary. The creeping extension groove can be formed by performing plasma etching on a region including the pn junction boundary portion in the exposed surface.

  In addition, the creeping extension groove can be formed while forming an exposed surface in the semiconductor substrate S as follows. That is, first, plasma etching is performed from the surface of the semiconductor substrate S to immediately before the region including the pn junction boundary, thereby continuously forming a large number of arc-shaped grooves parallel to the pn junction boundary. Thereafter, the plasma etching conditions are adjusted to perform plasma etching on the region including the pn junction boundary, and the creepage distance is longer than that of the arc-shaped groove formed immediately before the region including the pn junction boundary from the surface of the semiconductor substrate. An arcuate groove is formed. An arcuate groove located in a region including the pn junction boundary and having a creeping distance longer than other arcuate grooves is a “creeping extension groove”, and is a region including the pn junction boundary from the surface of the semiconductor substrate S. An “exposed surface” is formed from a large number of arc-shaped grooves formed just before and a creeping extension groove located in a region including the pn junction boundary.

In the semiconductor element S1, first plasma etching is performed from the surface of the semiconductor substrate S to immediately before the region including the pn junction boundary to form an exposed surface, and a creeping extension groove is formed in the region including the pn junction boundary. For this purpose, the second plasma etching is performed. The first plasma etching and the second plasma etching are processes in which conditions determined by one or a combination of a gas flow rate, a high frequency output, a discharge frequency, and a processing time are different.
In this case, plasma etching is preferably performed by alternately repeating the film forming process and the etching process. According to this method, the semiconductor element S1 having a high withstand voltage at the element end face can be manufactured.

  The gas used in the etching process is preferably a gas in which the reaction with the semiconductor substrate S isotropically proceeds in that an arc-shaped groove can be formed. Examples of such gas include SF6 and Cl2. The gas used in the film forming process is preferably C4F8, ClF3, or the like in that an insulating polymer film is formed on the surface where the pn junction boundary is exposed to further improve the voltage endurance of the element end face.

  Etching by the first plasma etching is performed from the surface of the semiconductor substrate S to immediately before the region including the pn junction boundary to form a large number of continuous arc-shaped grooves. Subsequently, a creeping extension groove is formed by performing etching by second plasma etching in a region including the pn junction boundary. Thereafter, plasma etching is performed again to the other surface (back surface) of the semiconductor substrate S under the same conditions as the first plasma etching to form a large number of continuous arc-shaped grooves. By doing so, it is possible to divide the semiconductor substrate S and manufacture individual chip-like semiconductor elements S1. In other words, in this case, the semiconductor substrate S can be divided into a plurality of semiconductor elements S1 surrounded by the separation groove 111 by the separation groove 111 constituted by the exposed surface. The semiconductor element S1 has a structure in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. When the vertical direction is a direction perpendicular to the interface between the layers, the p-type semiconductor layer and the n-type semiconductor layer are vertically Current flows in the direction. The present invention is characterized by the shape of the separation groove 111 formed in the semiconductor substrate S and the end surface shape of the semiconductor element S1 (surface where the pn junction boundary is exposed).

  Hereinafter, a method of forming the separation groove 111 performed using the inductively coupled plasma processing apparatus 1 and a method of forming a creeping extension groove in a region including the pn junction boundary will be described. In the method of forming the separation groove 111, high-density plasma is generated while alternately repeating the film forming process and the etching process to perform an etching process with a high aspect ratio on the semiconductor substrate. As a result, the thickness direction ( A separation groove 111 extending in the vertical direction) is formed. Since the separation groove 111 is formed by alternately repeating a film forming process and an isotropic etching process, a large number of continuous arc-shaped grooves (also referred to as scallops) are formed on the side wall of the separation groove 111. The The plasma etching is performed until the separation groove 111 reaches the pn junction boundary, thereby forming a surface where the pn junction boundary is exposed.

  The first plasma etching performed from the surface of the semiconductor substrate S to immediately before the region including the pn junction boundary and the second plasma etching for forming the creeping extension groove in the region including the pn junction boundary include a gas flow rate and a high frequency. Conditions determined by a combination of one or more of output, discharge frequency, and processing time are different.

  That is, plasma etching is performed until the separation groove 111 reaches just before the region including the pn junction boundary depending on the conditions of the first plasma etching. Thereafter, the surface is changed to the second plasma etching condition in which the etching action appears stronger than the first plasma etching condition, and the creeping surface located in the region including the pn junction boundary portion of the side wall surface (the exposed surface) of the separation groove 111. An extension groove is formed. The arcuate groove, which is a creeping extension groove located in a region including the pn junction boundary, has a creepage distance longer and a greater depth than the other continuous arcuate grooves. The creepage distance can be increased, and the withstand voltage of the semiconductor element can be improved. The creeping extension groove is formed in a region including the pn junction boundary, and improves the pressure resistance of the semiconductor element even if the distance between both ends of the creeping extension groove is larger or smaller than the distance between both ends of the depletion layer. In addition, it is possible to obtain the effect of reducing the size of the semiconductor element.

In the case where the semiconductor element S1 is manufactured by dividing the semiconductor substrate S after forming the creeping extension groove located in the region including the pn junction boundary under the second plasma etching condition, the plasma etching condition is set to the original first condition. Returning to the plasma etching conditions, plasma etching is performed up to the other surface (back surface) of the semiconductor substrate S, and a separation groove 111 is further formed. By carrying out like this, it has many arc-shaped groove | channels which are parallel to the pn junction boundary part in the surface which the pn junction boundary part exposed, and is located in the area | region which contains the said pn junction boundary part among the said arc-shaped grooves The arc-shaped groove, which is an extension groove, has a longer creepage distance and a greater depth than the other arc-shaped grooves.
In the present embodiment, the semiconductor substrate S is selected by appropriately selecting parameters such as the processing time and frequency of the film forming process and the etching process, the gas composition and gas flow rate, the substrate bias power, and the ICP power in the film forming process and the etching process. While forming a separation groove 111 (vertical hole) extending in a direction (longitudinal direction) perpendicular to the interface between the layers, a direction parallel to the interface between the layers (hereinafter referred to as “lateral direction”) is formed in the middle. An extending creeping extension groove (lateral hole) is formed. That is, the separation groove 111 includes a horizontal hole structure formed in the middle portion thereof, and an upper vertical hole structure and a lower vertical hole structure higher than the horizontal hole structure.

In both the plasma etching film forming step and the etching step for forming the separation groove 111, the inside of the processing chamber 2 is maintained at a predetermined reduced pressure atmosphere, for example, 20 mTorr by the vacuum pump 30.
In the film forming process, a film forming gas, for example, C4F8 is introduced into the processing chamber 2 from the film forming gas supply source through the film forming gas introduction pipe 16. Further, oxygen gas is introduced into the processing chamber 2 from the oxygen gas supply source through the gas introduction pipe 18.
In the film forming process, the SF 6 supplied from the etching gas supply source to the etching gas introduction pipe 14 bypasses the processing chamber 2 and is discharged to the exhaust pipe 22 of the load lock chamber 20. Can be switched. In addition, the residual gas from the etching process is discharged from the processing chamber 2 in synchronization with the introduction of the film forming gas.
As a result, the film forming gas is turned into plasma by the inductive coupling coil 4, and a CF-based polymer that functions as a protective film is polymerized on the side walls and bottom surface of the separation groove.

In the etching process, an etching gas such as SF 6 is introduced into the processing chamber 2 from the etching gas supply source through the gas introduction pipe 14. Further, oxygen gas is introduced into the processing chamber 2 from the oxygen gas supply source through the gas introduction pipe 18.
In the etching process, the film forming gas supplied from the film forming gas supply source to the gas introduction pipe 16 bypasses the processing chamber 2 and is discharged to the exhaust pipe 22 of the load lock chamber 20. The exit position is adjusted. Further, in synchronism with the introduction of the etching gas, the remaining gas in the film forming process is discharged from the processing chamber 2.
For example, high frequency power of 13.56 MHz is applied to the inductive coupling coil 4. As a result, the SF 6 in the processing chamber 2 enters a plasma state, and etching of a semiconductor layer such as Si is performed.

The oxygen gas continuously introduced into the processing chamber 2 during the film forming process and the etching process has a function of removing the protective film formed on the bottom surface of the separation groove in the film forming process. Oxygen gas also contributes to the removal of sulfur and carbon. Therefore, by introducing oxygen gas, the protective film on the bottom surface of the separation groove 111 can be quickly removed and etched in the vertical direction in the etching process performed after the film forming process.
The semiconductor substrate is not limited as long as it is a semiconductor substrate used for a power semiconductor element. For example, a compound semiconductor such as gallium nitride or silicon carbide may be used.

An isolation groove is actually formed in a semiconductor substrate (8-inch silicon wafer) having a p-type semiconductor region and an n-type semiconductor region using an inductively coupled plasma processing apparatus (RIE-800iPB) manufactured by Samco Co., Ltd. Manufactured.
In this inductively coupled plasma processing apparatus, the processing chamber is made of aluminum, and a plasma generation chamber made of a cylindrical dielectric is provided above the lower electrode. A single winding inductive coupling coil is provided around the dielectric, and a high frequency power source (13.56 MHz) is connected to the inductive coupling coil.
The semiconductor substrate has a p-type semiconductor layer stacked on an n-type semiconductor layer, and a photoresist mask is provided on the surface of the p-type semiconductor layer. The photoresist mask is provided with an opening (a portion to be etched), and a separation groove 111 is formed in the semiconductor substrate S from the opening during plasma etching.

FIG. 4 shows the first plasma etching conditions used when forming the separation groove 111 (upper / lower vertical hole structure). FIG. 5 shows the second plasma etching conditions used when forming the creeping extension groove (lateral hole structure) located in the region including the pn junction boundary.
The creeping extension grooves (vertical hole structure and horizontal hole structure) located in the region including the separation groove 111 and the pn junction boundary are each formed by executing a processing cycle including three steps one to several times. The first step includes a film forming process, and the second and third steps include an etching process. The second step is a process for removing ions of the protective film on the bottom by strongly drawing ions into the separation groove, and the third step is a process for etching the semiconductor layer.

In the process of forming the upper vertical hole structure (the structure from the wafer surface to immediately before the region including the pn junction boundary), the cycle of the first plasma etching condition shown in FIG. 4 is repeated 24 times to form the lower vertical hole structure. The process is repeated 35 times. Further, a creeping extension groove (horizontal hole structure) is formed in the process of forming the upper vertical hole structure and the lower vertical hole structure. In the process of forming the creeping extension groove (horizontal hole structure), the cycle of the second plasma etching condition shown in FIG. 5 is performed once.
As can be seen from FIGS. 4 and 5, the film formation process and the etching process time under the second plasma etching condition are set to be 4 times and 8 times as long as those of the first plasma etching condition.

  An electron microscopic image of the separation groove formed by the process of forming the separation groove is shown in FIG. In the electron microscope image of FIG. 6, it is not possible to clearly recognize how many arc-shaped grooves parallel to the pn junction boundary are continuously formed on the surface where the pn junction boundary is exposed. This is because the arc-shaped groove is reduced because the film forming process and the etching process under the first plasma etching conditions are switched in a short processing time. When the upper vertical hole structure is formed, the plasma etching is performed by repeating the cycle of the first plasma etching condition 24 times. In practice, therefore, 24 continuous arc-shaped grooves parallel to the pn junction are formed. ing. Similarly, when the lower vertical hole structure is formed, since the plasma etching is performed by repeating the cycle of the first plasma etching conditions 35 times, in practice, 35 continuous circles parallel to the pn junction are formed. An arcuate groove is formed.

In addition, it can be seen from the electron microscope image of FIG. 6 that one creeping extension groove (horizontal hole structure) is formed in a region including the pn junction boundary portion in the middle of the upper vertical hole structure and the lower vertical hole structure. The creeping extension groove is formed by performing the treatment under the second plasma etching condition once. Thus, it can be seen that the arcuate groove (creeping extension groove) located in the region including the pn junction boundary has a creepage distance longer than other arcuate grooves (scallops).
The electron microscope image of FIG. 6 shows a state in which the processing under the second plasma etching conditions is performed 35 times when the lower vertical hole structure is formed. However, if the processing under the second plasma etching conditions is further continued to the back surface of the wafer. A semiconductor element in which the semiconductor substrate is completely divided is obtained.

  Next, a semiconductor element was manufactured in the same manner as in Example 1 except that the film forming step (first step) under the second plasma etching condition shown in FIG. 5 was changed to 2 seconds. That is, the time of the etching process (third step) in the process of forming the creeping extension groove (lateral hole structure) located in the region including the pn junction boundary is made eight times as long as the process of forming the separation groove (upper / lower vertical hole structure), The process for forming the separation groove was performed at the same film formation step (first step). FIG. 7 shows an electron micrograph of the separation groove obtained in Example 2.

Also in Example 2, since both the film forming process and the etching process under the first plasma etching conditions are switched in a short processing time, a large number of small arc-shaped grooves are formed. Further, in the region including the pn junction boundary part in the middle of the upper vertical hole structure and the lower vertical hole structure, the process of the second plasma etching condition is performed once, so that one creeping extension groove (horizontal hole structure) is formed. It can be seen that the arcuate groove (creeping extension groove) located in the region including the pn junction boundary has a creepage distance longer than other arcuate grooves (scallops).
In the second plasma etching, although the film forming process is 2 seconds, the etching process time is as long as 40 seconds. Therefore, the wall surface of the upper vertical hole structure is slightly etched but rough. 7 can be understood.
Similarly to Example 1, the electron microscope image in FIG. 7 is obtained by repeating the cycle of the first plasma etching conditions 35 times when the lower vertical hole structure is formed, but the processing by the second plasma etching conditions is further continued. When the process is performed up to the back surface of the wafer, a semiconductor element obtained by dividing the semiconductor substrate is obtained.

  As described above, by appropriately setting the plasma conditions in the film forming process and the etching process of the separation groove forming process, it is possible to form a groove (arc-shaped groove) located at the pn junction boundary part in the middle of the separation groove. Therefore, the creepage distance of the depletion layer can be increased, and the pressure resistance of the semiconductor element is improved.

The present invention is not limited to the above-described embodiments and examples, and appropriate modifications can be made. For example, changing the plasma conditions in the pn junction boundary (horizontal hole structure) forming process to change the size of the groove (arc-shaped groove) structure, or changing the timing and number of times for incorporating the groove (horizontal hole) forming process Thus, the position and number of the groove (lateral hole) structure can be changed.
In addition, it is preferable to gradually change the conditions of the film forming process and the etching process as the processing cycle of the first plasma etching progresses in that the width of the separation groove 111 can be formed constant.
In addition, since the curvature of the arc of the creeping extension groove (arc-shaped groove) can be optimized, one of the gas flow rate, the high frequency output, and the discharge frequency during the film forming process and the etching process of the second plasma etching. It is preferable to change the conditions determined by one or a plurality of combinations.

DESCRIPTION OF SYMBOLS 1 ... Inductively coupled plasma processing apparatus 2 ... Processing chamber 4 ... Inductive coupling coil 6 ... Lower electrode 8 ... Electrostatic chucks 14, 16, 18 ... Gas introducing pipe 101 ... Conductive substrate 103 ... N-type semiconductor layer 105 ... P-type semiconductor Layer S ... Semiconductor substrate S1 ... Semiconductor element

Claims (4)

A method of manufacturing a semiconductor element from a semiconductor substrate having at least a p-type semiconductor region and an n-type semiconductor region,
A surface where a pn junction boundary is exposed on the semiconductor substrate is formed by plasma etching, and the exposed surface extends in a direction parallel to the interface between the p-type semiconductor region and the n-type semiconductor region at the pn junction boundary. A method of manufacturing a semiconductor device, comprising forming a creeping extension groove.   The method of manufacturing a semiconductor device according to claim 1, wherein the plasma etching alternately repeats a film forming process and an etching process. A first plasma etching performed from the surface of the semiconductor substrate to immediately before a region including the pn junction boundary, and a second plasma etching for forming the creeping extension groove in the pn junction boundary include a gas flow rate, a high frequency output, 3. The method of manufacturing a semiconductor device according to claim 1, wherein conditions determined by one or a combination of a discharge frequency and a processing time are different. The surface where the pn junction boundary portion is exposed has a large number of continuous arc-shaped grooves parallel to the pn junction boundary portion, and the arc-shaped grooves located at the pn junction boundary portion of the arc-shaped grooves are other arc shapes. A semiconductor element characterized in that a creepage distance is longer than a groove.