JP5557313B2 - Cache memory control system, control method thereof, and control program - Google Patents

Description

  The present invention relates to a cache memory control system that performs control to store predetermined information output from a plurality of processors in a cache memory, a control method thereof, and a control program.

  In recent years, software has become more complex as hardware advances, and it has become necessary to process a plurality of processes simultaneously. In this way, when processing multiple processes at the same time, there may be cases where another process starts after the completion of all processes, and one process handles the other process during this simultaneous processing. For example, a cache memory swap process is performed. As a result, processing time is delayed, and there is a concern that the performance of the entire system is degraded. Various multiprocessor systems have been developed to solve such problems.

  In the above swap processing, the multiprocessor system, for example, registers new predetermined information at the cache memory level with a cache, directory type directory, or snoop type tag, and when each entry level is full, either The new level information is registered and new information is registered in the empty level.

  Here, level selection methods in conventional swap processing include round robin, LRU (selected from old information), random selection, a method of leaving a level used by a high priority processor, or a combination of the above. (For example, refer to Patent Document 1).

JP 2004-145780 A

  However, when the conventional level selection method is used for a multiprocessor system, the information registered in each level of the cache memory is managed as a whole from which source (eg, processor). Absent. For this reason, information registered by the process being processed may be swapped, or only information registered by a specific process may be always swapped.

  Here, when a process is waiting for the completion of another process, if the swap process of the process to be waited frequently occurs and the time until completion is delayed, the next process cannot be started and a waiting time occurs. Therefore, there is a problem that the processing performance of the entire system is deteriorated.

  The present invention has been made to solve such problems, and a main object of the present invention is to provide a cache memory control system, a control method thereof, and a control program capable of improving the processing performance.

  To achieve the above object, according to one aspect of the present invention, control is performed to store predetermined information output from a plurality of processors in each level of a cache memory, and the predetermined information is stored in the output destination processor. A cache memory control system including source information indicating, for each source information, counting means for counting the number of the source information stored in each level of the cache memory and calculating as a count value; Priority level determining means for determining a priority level of a level to be swapped among the levels of the cache memory based on the count value for each source information calculated by the means; and determined by the priority level determining means Of the cache memory levels, swap processing is performed based on the prioritized priority. And a level determining means for determining the level of performing a cache memory control system, characterized in that.

  In addition, according to one aspect of the present invention for achieving the above object, control is performed to store predetermined information output from a plurality of processors in each level of a cache memory, and the predetermined information is stored in the output destination. A control method of a cache memory control system including source information indicating a processor, wherein for each source information, the number of the source information stored in each level of the cache memory is counted and calculated as a count value, Based on the calculated count value for each source information, a priority order of levels to be swapped among the respective levels of the cache memory is determined, and based on the determined priority order, the cache memory The cache memory control system is characterized in that, among the levels, the level for performing the swap processing is determined. It may be a method of controlling the beam.

Furthermore, according to one aspect of the present invention for achieving the above object, control is performed such that predetermined information output from a plurality of processors is stored in each level of a cache memory, and the predetermined information is stored in the output destination. A control program for a cache memory control system, including source information indicating a processor, wherein for each source information, the number of the source information stored in each level of the cache memory is counted and calculated as a count value When,
Based on the calculated count value for each source information, processing for determining a priority level of a level to be swapped among the levels of the cache memory, and based on the determined priority level, the cache A control program for a cache memory control system that causes a computer to execute a process for determining the level for performing a swap process among the levels of the memory may be used.

  ADVANTAGE OF THE INVENTION According to this invention, the cache memory control system which can improve processing performance, its control method, and a control program can be provided.

It is a functional block diagram of a cache memory control system according to an embodiment of the present invention. 1 is a block diagram showing a schematic configuration of a cache memory control system according to an embodiment of the present invention. It is a flowchart which shows an example of the control processing flow of the cache memory control system which concerns on one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram of a cache memory control system according to an embodiment of the present invention. The cache memory control system 1 according to the present embodiment performs control to store predetermined information output from a plurality of processors 11 at each level of the cache memory 12. Here, the predetermined information includes source information indicating the output destination processor 11.

  The cache memory control system 1 also counts the number of source information stored in each level of the cache memory 12 for each source information as a count value, and the source information calculated by the count means 2 Based on the count value for each level, priority level determining means 3 for determining the priority level of the level to be swapped among the levels of the cache memory 12, and based on the priority level determined by the priority level determining means 3 The level determining means 4 for determining the level for performing the swap processing among the levels of the cache memory 12 is provided.

  As a result, the usage rate of the cache memory 12 can be equalized for each source information, and the processing performance of the entire system 1 can be improved by eliminating sources whose performance is extremely reduced.

  FIG. 2 is a block diagram showing a schematic configuration of a cache memory control system according to an embodiment of the present invention. The cache memory control system 1 according to this embodiment performs control to store predetermined information output from the plurality of processors 11 in the cache memory 12.

  Here, the predetermined information indicates, for example, processing contents of each processor 11, is information such as transaction information 100 registered in the cache memory 12, and includes source information indicating the output destination processor 11. Each source information may indicate a single processor 11 or may indicate a plurality of processors 11 arbitrarily combined.

  The cache memory control system 1 according to the present embodiment includes a cache memory 12, an index circuit 13, a first register circuit 14, a count circuit 15, a priority determination circuit 16, a ratio calculation circuit 17, and a level determination circuit. 18, a level selection circuit 19, a second register circuit 20, and a merge circuit 21.

  The cache memory 12 stores, for example, transaction information 100 output from each of a plurality of processors (multiprocessors) 11 and source information included in the transaction information 100 using a set associative method for each level.

  The index circuit 13 is a specific example of index means. When the transaction information 100 registered in the cache memory 12 is received, the index circuit 13 indexes information of each level stored in the cache memory 12. Then, the index circuit 13 outputs information on each level of the cache memory 12 that is the index result to the first register circuit 14 via the cache memory 12. Further, the first register circuit 14 stores information on each level of the cache memory 12 output from the index circuit 13.

  The count circuit 15 is a specific example of the counting means 2 and is configured as an up / down counter, for example. The count circuit 15 counts the source information of the transaction information 100, counts the number of source information stored in each level of the cache memory 12 for each source information, and calculates the count value.

  Specifically, the count circuit 15 includes individual counters (individual counter Y1, individual counter Y2, individual counter corresponding to each source information (source information X1, source information X2, source information X3,..., Source information Xn). Y3..., Individual counter Yn).

  Each individual counter Yn counts up (+1) when the transaction information of the corresponding source information Xn is newly stored in the cache memory 12, while the transaction information 100 of the corresponding source information Xn is swapped ( When the replacement process is performed, a countdown (-1) is performed. In this way, the individual counters Y1 to Yn of the count circuit 15 output the count values Z1 to Zn counted up / down and totaled for each source information to the priority determination circuit 16 and the ratio calculation circuit 17, respectively.

  The priority order determination circuit 16 is a specific example of the priority order determination means 3 and is subject to swap processing among the levels of the cache memory 12 based on the count value Zn for each source information calculated by the count circuit 15. Determine the priority of the level to be.

  For example, as the count value Zn for each source information calculated by the count circuit 15 increases, the priority determination circuit 16 sets the priority of swap processing for the transaction information 100 of the source information Xn, and conversely, As the count value Zn for each source information decreases, the priority of swap processing for the transaction information 100 of the source information Xn is set lower. The priority determination circuit 16 outputs the determined priority of swap processing to the level determination circuit 18.

  The ratio calculation circuit 17 is a specific example of the ratio calculation means, calculates the total value (ΣZn) of the count values Z1 to Zn for each source information calculated by the count circuit 15, and calculates the total capacity number of the cache memory 12. The ratio of the grand total value to is calculated.

  Specifically, the ratio calculation circuit 17 calculates the total value of the count values Z1 to Zn output from the individual counters Y1 to Yn of the counter circuit 15, and uses the calculated total value in the cache memory 12 as a whole. By dividing by the number of capacities (the number of transaction information 100 that can be stored in the cache memory 12), the ratio of the total value is calculated. The ratio calculation circuit 17 outputs the calculated ratio of the total value to the level determination circuit 18.

  The level determination circuit 18 is a specific example of level determination means. The level determination circuit 18 compares the information of each level of the cache memory 12 stored in the first register circuit 14 with the key address 101 of the transaction information 100, and the priority determination circuit. The level for performing the swap process is determined based on the priority order determined by 16 and the ratio of the total value calculated by the ratio calculation circuit 17. The level determination circuit 18 includes a hit level determination unit 181, a miss level determination unit 182, a swap level determination unit 183, and a level determination unit 184.

  The hit level determination unit 181 extracts the level (hit level) that matches the key address 101 from the information of each level of the cache memory 12 stored in the first register circuit 14 and outputs it to the level determination unit 184. To do. Further, the miss level determination unit 182 has a level that is free in the cache memory 12 when there is no level that matches the key address 101 among the information of each level of the cache memory 12 stored in the first register circuit 14 ( Miss level) is extracted and output to the level determination unit 184.

  Further, the swap level determination unit 183 determines the priority level when there is no level that matches the key address 101 and there is no level that is free in the cache memory 12, that is, regardless of the hit and miss of the cache memory 12. Based on the priority order determined by the determination circuit 16 and the ratio of the total value calculated by the ratio calculation circuit 17, a level (swap level) for performing the swap processing is determined, and the level determination unit 184 is determined. Output.

  For example, the swap level determination unit 183 may determine the level with the highest priority determined by the priority determination circuit 16 as the level for performing the swap process. In addition, when the ratio of the total value calculated by the ratio calculation circuit 17 is low, the swap level determination unit 183 determines the level for performing the swap process by a known method such as round robin or LRU, and the ratio of the total value When the value becomes equal to or greater than the predetermined ratio, it is preferable to determine the level for performing the swap processing according to the priority order determined by the priority order determination circuit 16 as described above.

  Further, the level determination unit 184 determines the level output from the swap level determination unit 183 as the level for performing the swap process.

  Further, the level determination unit 184 outputs the hit level from the hit level determination unit 181 to the level selection circuit 19 when it matches the key address 101, and determines the miss level when there is an empty level that does not match the key address 101. The miss level from the unit 182 is output to the level selection circuit 19, and if it does not match the key address 101 and there is no empty level, the swap level from the swap level determination unit 183 is output to the level selection circuit 19.

  The level selection circuit 19 is a specific example of level selection means, and selects the level information output from the level determination unit 184 from the information of each level of the cache memory 12 stored in the first register circuit 14. The information of the selected level is stored in the second register circuit 20.

  The level information stored in the second register circuit 20 is output from the second register circuit 20 to be used for subsequent processing, and is input to the merge circuit 21 for updating the cache memory 12. Then, the merge circuit 21 outputs the merged merge information to the cache memory 12 and the individual counters Yn of the count circuit 15.

  Here, the merge information is input as new transaction information 100 to the cache memory 12. Further, since all levels of the cache memory 12 have been stored as described above, when the swap process is executed, the corresponding individual counter Yn has a count value corresponding to the source information Xn of the transaction information 100 to be swapped. Count down Zn.

  As a result, the number of source information Xn stored in the cache memory 12 can be managed for each source information, and the total sum of the count values Zn of the individual counters Yn is stored in the transaction stored in the cache memory 12. This is consistent with the grand total of information (source information).

  When the total sum of the transaction information 100 is small (the ratio of the total sum value is low), the capacity of the cache memory 12 is still sufficient as described above, so there is no need to manage each process and the conventional information The swap level may be determined by a method. Switching between the method of the present invention for determining the swap level so that the number of each source information Xn is equal to the conventional method is determined by the ratio of the total value, but the switching point is set at the initial setting. Since it can be set, the optimum performance can be derived by checking the performance of the entire system and changing the setting value.

  Next, the control method of the cache memory control system 1 according to the present embodiment will be described in detail. FIG. 3 is a flowchart showing an example of a control processing flow of the cache memory control system according to the present embodiment.

  Transaction information 100 registered in the cache memory 12 is output from each processor 11 (step S101) and input to the count circuit 15 and the index circuit 13, respectively.

  The corresponding individual counter Yn of the count circuit 15 counts up the count value Zn based on the source information Xn of the transaction information 100 (step S102), and the priority order determination circuit 16 uses each individual counter Yn of the count circuit 15 to count up. Based on the counted value Zn for each source information, the priority level of the level to be swapped among the levels of the cache memory 12 is determined (step S103).

  In addition, the ratio calculation circuit 17 calculates the total value of the count values Z1 to Zn for each source information calculated by the count circuit 15, and calculates the ratio of the calculated total value to the total capacity number of the cache memory 12. (Step S104).

  On the other hand, the index circuit 13 performs indexing of information at each level stored in the cache memory 12 (step S105).

  Next, when the hit level determination unit 181 of the level determination circuit 18 extracts the hit level that matches the key address from the information of each level of the cache memory 12 stored in the first register circuit 14 (in step S106). (YES), the extracted hit level is output to the level determining unit 184, the hit level is updated as necessary (step S107), and this process ends.

  Further, the miss level determination unit 182 has no level that matches the key address among the information of each level of the cache memory 12 stored in the first register circuit 14 (NO in step S106), and is empty in the cache memory 12. When the current miss level is extracted (YES in step S108), the extracted miss level is output to the level determining unit 184, transaction information is registered in the miss level (step S109), and this process is terminated. To do.

  Furthermore, when the swap level determination unit 184 has no level that matches the key address and there is no level free in the cache memory 12 (NO in step S108), the swap level determination unit 183 causes the ratio calculation circuit 17 to It is determined whether or not the ratio of the calculated total value is equal to or greater than a predetermined ratio (step S110).

  When the swap level determination unit 183 determines that the ratio of the total value calculated by the ratio calculation circuit 17 is equal to or greater than a predetermined ratio (YES in step S110), the swap level determination unit 183 swaps according to the priority determined by the priority determination circuit 16 A level to be processed is determined (step S111), swap processing is performed for the determined level, and new transaction information is registered.

  On the other hand, if the swap level determination unit 183 determines that the ratio of the total value calculated by the ratio calculation circuit 17 is not equal to or greater than the predetermined ratio (NO in step S110), the swap level determination unit 183 determines a level for performing the swap process by the conventional method ( Step 112), swap processing is performed for the determined level, and new transaction information is registered.

  As described above, according to the cache memory control system 1 according to the present embodiment, the usage rate of the cache memory 12 can be equalized for each source information, and by eliminating the source (processor 11) whose performance is extremely reduced, The processing performance of the entire system 1 can be improved. Note that the processing performance can be improved with a simple configuration and a slight change in the level selection control at the time of swap processing, leading to cost reduction. In addition, since the optimum performance of the system 1 can be extracted only by changing the initial setting, the flexibility of the system can be ensured.

  In addition, this invention is not limited to the said embodiment, It is possible to change suitably in the range which does not deviate from the meaning.

  For example, in the above-described embodiment, a snoop method or a directory method for managing cache coherency for maintaining the consistency of the cache memory 12 can be applied. In this case, the cache memory control system 1 has a tag in the snoop method and a directory in the directory method, and manages information registered in the cache memory 12 using a predetermined algorithm. In the tag and the directory, the basic structure of the cache memory 12 is the same, and swap processing is required. Therefore, the same effect as in the above embodiment can be expected.

  The present invention can also realize arbitrary processing by causing a CPU (Central Processing Unit) to execute a computer program. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another communication medium. The storage medium includes, for example, a flexible disk, hard disk, magnetic disk, magneto-optical disk, CD-ROM, DVD, ROM cartridge, RAM memory cartridge with battery backup, flash memory cartridge, and nonvolatile RAM cartridge. The communication medium includes a wired communication medium such as a telephone line, a wireless communication medium such as a microwave line, and the like.

DESCRIPTION OF SYMBOLS 1 Cache memory control system 2 Count means 3 Priority order determination means 4 Level determination means 11 Processor 12 Cache memory 13 Index circuit 14 First register circuit 15 Count circuit 16 Priority order determination circuit 17 Ratio calculation circuit 18 Level determination circuit 19 Level selection circuit 19 Level selection circuit 20 Second register circuit 21 Merge circuit 181 Hit level determination unit 182 Miss level determination unit 183 Swap level determination unit 184 Level determination unit

Claims (7)

Control is performed to store predetermined information output from a plurality of processors in each level of the cache memory, and
The predetermined information is a cache memory control system including source information indicating the output destination processor,
Counting means for counting the number of the source information stored in each level of the cache memory for each source information and calculating as a count value;
Slave is I the count value of each of the source information calculated by said counting means increases, among the level of the cache memory, priority determining means for increasing determining the level of priority to be swap process When,
Level determining means for determining the level to be swapped out of the levels of the cache memory based on the priority determined by the priority determining means;
A cache memory control system comprising: The cache memory control system according to claim 1 ,
Calculating a total sum of count values for each of the source information calculated by the counting means, further comprising a ratio calculating means for calculating a ratio of the calculated total total value to the total capacity number of the cache memory;
The level determining means determines a level for performing the swap process according to the priority determined by the priority determining means when the ratio calculated by the ratio calculating means is equal to or greater than a predetermined ratio; A featured cache memory control system. The cache memory control system according to claim 1 or 2 ,
Index means for indexing each level of information stored in the cache memory;
First register means for storing information of each level of the cache memory that is an index result indexed by the index means;
The level determining means includes a result of comparing the information of each level of the cache memory stored in the first register means and the key address of the predetermined information, and the priority determined by the priority determining means. A cache memory control system, wherein a level for performing the swap process is determined based on the level. The cache memory control system according to claim 3 ,
The level determining means includes
A hit level determination unit that extracts and outputs the level that matches the key address from the information of each level;
When there is no level that matches the key address among the information of each level, a miss level determination unit that extracts and outputs a level that is free in the cache memory;
When there is no level that matches the key address and there is no free level in the cache memory, the level for performing the swap processing is determined based on the priority determined by the priority determination means. A swap level determination unit;
A level determination unit that determines the level output from the hit level determination unit, the miss level determination unit, or the swap level determination unit;
A cache memory control system. The cache memory control system according to claim 3 or 4 ,
Level selection means for selecting the level information determined by the level determination means among the information on each level of the cache memory stored in the first register means;
And a second register means for storing information of the level selected by the level selection means. Control of storing predetermined information output from a plurality of processors at each level of the cache memory, and the predetermined information includes source information indicating the output destination processor. There,
For each source information, the number of the source information stored in each level of the cache memory is counted and calculated as a count value,
As the calculated count value for each source information increases , among the levels of the cache memory, the priority level of the level to be swapped is determined high ,
Based on the determined priority order, the level for performing the swap process is determined among the levels of the cache memory.
And a control method of a cache memory control system. Control for storing predetermined information output from a plurality of processors at each level of the cache memory, and the predetermined information is a control program for a cache memory control system including source information indicating the output destination processor. There,
For each source information, a process of counting the number of the source information stored in each level of the cache memory and calculating as a count value;
Follow the I count value for each source information the calculated increases, among the level of the cache memory, a process of increasing determining the level of priority to be swap process,
Based on the determined priority order, a process for determining the level to be swapped out of each level of the cache memory;
A control program for a cache memory control system, which causes a computer to execute

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