JP5561311B2 - Semiconductor device - Google Patents

Description

The present technology relates to a semiconductor device, and more particularly, to a semiconductor device including a MOS (Metal Oxide Semiconductor) transistor.

  Conventionally, the transistor performance has been improved by reducing the size, such as on-current, but after 65nm (nanometer), the size is simply reduced due to the extreme degradation of the threshold voltage in the short channel region. It is becoming difficult to achieve an improvement rate according to the conventional scaling law. Therefore, in recent years, a technique for improving the performance of a transistor by increasing the mobility of carriers (electrons and holes) by applying stress to the MOS transistor has been studied.

  Stress applied to the transistor is divided into compressive stress and tensile stress. On the other hand, in an n-channel type (hereinafter simply referred to as “n-type”) MOS transistor and a p-channel type (hereinafter simply referred to as “p-type”) MOS transistor, in order to increase carrier mobility. The direction of the stress acting on the semiconductor layer is different. Specifically, in the MOS transistor in which the gate electrode G, the source region S, and the drain region D are formed, the n-type MOS transistor has a gate length direction X and a gate width direction Y as shown in FIG. In both cases, it is preferable to apply tensile stress respectively. On the other hand, in the p-type MOS transistor, as shown in FIG. 15B, it is preferable to apply a compressive stress in the gate length direction X and to apply a tensile stress in the gate width direction Y.

  As one of the prior arts, for example, in a p-type MOS transistor, a semiconductor germanium (SiGe) layer having a lattice constant larger than that of silicon (Si) is formed by epitaxial growth as a source / drain provided in a transistor region. A technique for applying stress to the channel region of the layer has been proposed (see, for example, Non-Patent Document 1 below). As another conventional technique, a technique has been proposed in which a silicon nitride film used as a contact etching stopper on a gate electrode is used as a stress film.

T. Ghai et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IED M Tech Dig., Pp.978-980, (2003)

  However, in the above prior art, when the distance between adjacent gate electrodes (hereinafter referred to as “inter-gate distance”) is shortened due to the layout of the transistor region, the stress caused by the SiGe layer or the silicon nitride film The stress due to the above does not act effectively on the channel region of the semiconductor layer, and the performance of the transistor cannot be sufficiently improved.

Engaging Ru semi conductor arrangement to the present technology, a semiconductor layer having a transistor region, a gate electrode formed through a gate insulating film on the first surface of the semiconductor layer in the transistor region, a semiconductor layer in the transistor region A stress film formed on a second surface opposite to the first surface, and the stress film is formed using a silicide film.

In engaging Ru semi conductor arrangement in this technology, the surface on which the gate electrode is formed by forming a stress film on the second surface of the semiconductor layer on the opposite side, applying stress to the semiconductor layer by the stress film Since it is configured, stress can be effectively applied to the channel region of the semiconductor layer without depending on the layout such as the inter-gate distance in the transistor region. Further, since the silicide film generates a strong tensile stress, a strong tensile stress can be applied to the channel region of the semiconductor layer by forming the stress film using the silicide layer on the second surface of the semiconductor layer. It becomes possible.

According to the semiconductor device of the present technology , the transistor performance can be improved by effectively applying stress to the channel region of the semiconductor layer without depending on the layout such as the inter-gate distance in the transistor region.

FIG. 10 is a cross-sectional view (part 1) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present technology ; FIG. 9 is a cross-sectional view (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present technology ; FIG. 9 is a cross-sectional view (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present technology ; FIG. 14 is a cross-sectional view (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present technology ; It is a figure showing an example of composition of a semiconductor device concerning a 1st embodiment of this art . In the semiconductor device concerning a 1st embodiment of this art , it is a figure explaining the direction of the stress applied to a semiconductor layer. It is a figure showing an example of composition of a CMOS transistor in a 1st embodiment of this art . It is a figure which shows the 1st example of application to a CMOS inverter circuit. It is a figure which shows the 2nd example of application to a CMOS inverter circuit. It is a figure which shows the example of application to a SRAM cell. It is sectional drawing which shows the other manufacturing process of the semiconductor device which concerns on 1st Embodiment of this technique . It is sectional drawing which shows the further another manufacturing process of the semiconductor device which concerns on 1st Embodiment of this technique . It is a figure showing an example of composition of a semiconductor device concerning a 2nd embodiment of this art . It is a figure showing a manufacturing process of a semiconductor device concerning a 2nd embodiment of this art . It is a figure which shows the relationship between the conductivity type of a MOS transistor, and a preferable stress direction.

Hereinafter, specific embodiments of the present technology will be described in detail with reference to the drawings.

First, a method for manufacturing a semiconductor device according to an embodiment of the present technology will be described.

[First Embodiment]
1 to 4 are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment of the present technology . First, as shown in FIG. 1A, a CMOS transistor (complementary MOS transistor) is formed using a silicon substrate 1 having an SOI (silicon on insulator) structure.

  A semiconductor layer 3 made of silicon is formed on one surface of the silicon substrate 1 via a BOX (Buried Oxide) layer 2 made of silicon oxide. The SOI substrate includes a silicon substrate 1, a BOX layer 2 and a semiconductor layer 3. The BOX layer 2 is used as an etching stopper layer when the SOI substrate is thinned in a subsequent process.

  The semiconductor layer 3 is divided (element isolation) by the element isolation layer 4. More specifically, the semiconductor layer 3 is divided into an n-type MOS transistor region and a p-type MOS transistor region having different conductivity types in plan view. However, only one MOS transistor region of one conductivity type is shown here. The element isolation layer 4 is a trench type isolation layer by STI (shallow trench isolation) method. In the MOS transistor region of the semiconductor layer 3, a gate insulating film 5, a gate electrode 6, an extension region 7, sidewalls 8, source / drain regions 9, and a silicide layer 10 are formed. A cap layer 11 is formed on the first surface. In the semiconductor layer 3, a channel region is formed between the pair of source / drain regions 9 and below the gate electrode 6.

  Here, an example of a method for manufacturing a MOS transistor will be described. First, the BOX layer 2 and the semiconductor layer 3 are sequentially formed on one surface of the silicon substrate 1. Next, after forming the element isolation layer 4 in the semiconductor layer 3 by the STI method, a conductive impurity is introduced into the transistor formation region of the semiconductor layer 3 partitioned by the element isolation layer 4, thereby forming a well region in the semiconductor layer 3. Form. The element isolation layer 4 may be formed after the well region is formed in the semiconductor layer 3. Also. Here, an SOI substrate is employed from the viewpoint of processing accuracy, but an ordinary bulk substrate may be employed instead of the SOI substrate.

  Next, a gate insulating film 5 made of silicon oxide and a gate electrode 6 made of polysilicon are formed on the first surface of the semiconductor layer 3 by patterning. Next, an extension region 7 is formed on both sides of the gate electrode 6 by introducing conductive impurities into the semiconductor layer 3 using the gate electrode 6 as a mask.

  Next, a sidewall 8 made of an insulating film is formed on the side surface of the gate electrode 6. Subsequently, a source / drain region 9 is formed on both sides of the gate electrode 6 by introducing conductive impurities into the semiconductor layer 3 using the gate electrode 6 and the sidewalls 8 as a mask. The source / drain region 9 can also be formed of a silicon germanium layer by epitaxially growing silicon germanium having a lattice constant larger than that of silicon at a position where the source / drain is formed.

  Next, a silicide layer 10 is formed on the gate electrode 6 and the source / drain region 9, and then a cap layer 11 is formed on the first surface of the semiconductor layer 3 so as to cover the silicide layer 10. The silicide layer 10 is formed to reduce contact resistance. As the silicide material, nickel (Ni), cobalt (Co), titanium (Ti), or the like can be used. In particular, the NiSi layer is preferably formed from the viewpoint of low temperature formation. The cap layer 11 is used as an etching stopper layer when a contact hole is formed in a subsequent process. The cap layer 11 is formed of a highly elastic silicon nitride film or the like, and generates a tensile stress. As the cap layer 11, a DSL (Dual Stress Line) film having different stress directions in the n-type MOS transistor region and the p-type MOS transistor region may be employed.

  A MOS transistor region is formed in the semiconductor layer 3 by the above manufacturing method. If the MOS transistor region is an n-type MOS transistor region, the semiconductor layer 3 is p-type, and the extension region 7 and the source / drain region 9 are each n-type. If the MOS transistor region is a p-type MOS transistor region, the semiconductor layer 3 is p-type. The layer 3 is n-type, and the extension region 7 and the source / drain region 9 are each p-type.

  Thereafter, in a BEOL (Back End Of the Line) process for forming the multilayer wiring, as shown in FIG. 1B, the first interlayer insulation is formed on the first surface of the semiconductor layer 3 via the cap layer 11. After the film 12 is formed, contact holes (not shown) reaching the silicide layer 10 on the gate electrode 6 and the silicide layer 10 on the source / drain regions 9 are formed in the first interlayer insulating film 12, and each of the contact holes (not shown) is formed. The contact plug 13 is formed by filling the contact hole with a conductive material such as tungsten (W). Next, after forming a second interlayer insulating film 14 on the first interlayer insulating film 12, a wiring layer 15 is formed on the second interlayer insulating film 14 using a wiring material such as copper (Cu). Next, a third interlayer insulating film 16 is formed on the second interlayer insulating film 14.

Subsequently, as illustrated in FIG. 2A, a support substrate 18 is attached to the third interlayer insulating film 16 with an adhesive layer 17 interposed therebetween. For the adhesive layer 17, a resin such as polyimide, BCB (benzocyclobutene), or SiLK can be used. The support substrate 18 can be a Si substrate or a SiO ₂ substrate. Next, as shown in FIG. 2B, the front and back of the substrate are reversed, and the silicon substrate 1 located on the opposite side of the support substrate 18 is removed by CMP (Chemical Mechanical Polishing) or wet etching. As a result, the SOI substrate is thinned. At that time, by using the BOX layer 2 as an etching stopper layer, the SOI substrate can be thinned with high accuracy.

Next, as shown in FIG. 3A, after the BOX layer 2 is removed from the second surface of the semiconductor layer 3, the second surface of the semiconductor layer 3 is formed on the second surface as shown in FIG. For example, an insulating film 19 made of SiO ₂ is formed. The BOX layer 2 may be removed as necessary. Next, as shown in FIG. 4A, the stress transmission pattern 19 </ b> A is formed on the second surface of the semiconductor layer 3 by patterning the insulating film 19. The stress transmission pattern 19 </ b> A is an uneven pattern in the thickness direction of the semiconductor layer 3, and is formed in a streak shape along the gate width direction (depth direction in FIG. 4). Further, the stress transmission pattern 19 </ b> A is composed of a plurality of linear patterns having a streak shape, and is formed in the transistor region of the semiconductor layer 3 that is element-isolated by the element isolation layer 4 in the plane direction of the semiconductor layer 3.

4B, a stress film 20 made of an insulating film is formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 19A. For the stress film 20, for example, a CVD (Chemical Vapor Deposition) film such as SiN, SiO ₂ , or SiON, or a coating film such as polyimide, BCB, SiLK, or polysilazane can be applied.

  The stress film 20 is a film that applies stress to the semiconductor layer 3. The stress film 20 is divided into a film that generates tensile stress (hereinafter also referred to as “tensile stress film”) and a film that generates compressive stress (hereinafter also referred to as “compressive stress film”). Among these, the tensile stress film is formed in the n-type MOS transistor region, and the compressive stress film is formed in the p-type MOS transistor region.

  In the semiconductor device obtained by the manufacturing method as described above, as shown in FIGS. 5A and 5B, the second side of the semiconductor layer 3 opposite to the first surface where the gate electrode 6 is formed is provided. The stress film 20 is formed on the surface, and stress is applied to the semiconductor layer 3 by the stress film 20. Therefore, stress can be effectively applied to the channel region of the semiconductor layer 3 without depending on the layout such as the inter-gate distance in the MOS transistor region. Further, the stress transmission pattern 19A is formed on the second surface of the semiconductor layer 3, and the stress film 20 is formed so as to cover the stress transmission pattern 19A. In such a configuration, since the stress generated by the stress film 20 acts strongly on the stress transmission pattern 19A in the surface direction of the semiconductor layer 3, the stress is efficiently transmitted to the semiconductor layer 3 through the stress transmission pattern 19A. . For this reason, compared with the case where the stress transmission pattern 19A is not formed, the stress applied to the semiconductor layer 3 by the stress film 20 is amplified. That is, the stress applied to the semiconductor layer 3 by the stress film 20 is strengthened by the presence of the stress transmission pattern 19A. Therefore, stronger stress can be applied to the channel region of the semiconductor layer 3 than when the stress transfer pattern 19A is not formed.

In the semiconductor device according to the first embodiment of the present technology , the direction of the stress applied to the semiconductor layer 3 by the stress film 20 is regulated by the direction of the stress transmission pattern 19A. Specifically, a stress is applied to the semiconductor film 3 in a direction orthogonal to the direction of the stress transmission pattern 19A having a streak shape. For this reason, by using the stress film 20 formed in the n-type MOS transistor region as a tensile stress film, as shown in FIG. A tensile stress can be applied to X in the channel length direction). Further, by making the stress film 20 formed in the p-type MOS transistor region a compressive stress film, as shown in FIG. 6B, the channel region under the gate electrode 6 is arranged in the gate length direction X. Compressive stress can be applied. Accordingly, in both the n-type MOS transistor region and the p-type MOS transistor region, the carrier mobility can be increased to improve the transistor performance.

  Further, as shown in FIGS. 7A and 7B, the CMOS transistor has an n-type MOS transistor region nTR and a p-type MOS transistor region pTR that are element-isolated by the element isolation layer 4 as shown in FIGS. In the MOS transistor region nTR, a tensile stress film 20t is formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 19A, and a cap serving as a tensile stress film is formed on the first surface of the semiconductor layer 3. A layer 11t is formed, and in the p-type MOS transistor region pTR, a compressive stress film 20c is formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 19A, and the first surface of the semiconductor layer 3 is formed. It is also possible to form a cap layer 11c serving as a compressive stress film thereon.

  7A and 7B, the cap layer 11t formed on the first surface of the semiconductor layer 3 in the n-type MOS transistor region nTR and the first layer of the semiconductor layer 3 are used. Due to the synergistic effect of the tensile stress film 20t formed on the second surface, tensile stress is applied to the semiconductor layer 3 from both the first surface and the second surface of the semiconductor layer 3. Therefore, a tensile stress can be applied more strongly to the channel region under the gate electrode 6 in the n-type MOS transistor region nTR. Similarly, in the p-type MOS transistor region pTR, a synergistic effect of the cap layer 11 c formed on the first surface of the semiconductor layer 3 and the compressive stress film 20 c formed on the second surface of the semiconductor layer 3. Thus, compressive stress is applied to the semiconductor layer 3 from both the first surface and the second surface of the semiconductor layer 3. Therefore, compressive stress can be applied more strongly to the channel region under the gate electrode 6 in the p-type MOS transistor region pTR.

  8A and 8B are diagrams showing an application example to a CMOS inverter circuit. In the figure, an n-type MOS transistor region nTR and a p-type MOS transistor region pTR are isolated from each other by an element isolation layer 4. An n-type source / drain region 9n is formed in the n-type MOS transistor region nTR, and a p-type source / drain region 9p is formed in the p-type MOS transistor region pTR. The gate electrode 6 is a common electrode in the n-type MOS transistor region nTR and the p-type MOS transistor region pTR.

In contrast, the stress transfer pattern 19A is a n-type MOS transistor region nTR and p-type MOS transistor region pTR, both formed in the streak along the gate rectangular direction X. The stress transmission pattern 19A is formed so as to intersect the gate electrode 6 in plan view. The stress transmission pattern 19 </ b> A is covered on the second surface of the semiconductor layer 3 by a stress film 20 that generates a tensile stress. For this reason, in both the n-type MOS transistor region nTR and the p-type MOS transistor region pTR, the tensile stress of the stress film 20 covering the stress transmission pattern 19A acts in the gate width direction Y. When tensile stress is applied in the gate width direction Y in this way, carrier mobility increases in both the n-type MOS transistor region nTR and the p-type MOS transistor region pTR. Therefore, the performance of each transistor can be improved without forming the stress film 20 separately in the n-type MOS transistor region nTR and the p-type MOS transistor region pTR.

  Further, when applied to the CMOS inverter circuit, as shown in FIGS. 9A and 9B, the gate electrode 6 is covered on the first surface of the semiconductor layer 3 in the n-type MOS transistor region nTR. While forming the tensile stress film 21t, it is also possible to form the compressive stress film 21c on the first surface of the semiconductor layer 3 so as to cover the gate electrode 6 in the p-type MOS transistor region pTR.

  When such a configuration is adopted, tensile stress is applied from the first surface side of the semiconductor layer 3 by the tensile stress film 21t formed on the first surface of the semiconductor layer 3 in the n-type MOS transistor region nTR. At the same time, the stress film (tensile stress film) 20 formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 19A is pulled in the gate width direction Y from the second surface side of the semiconductor layer 3. Stress is applied. For this reason, the tensile stress in the gate length direction X and the tensile stress in the gate width direction Y act simultaneously on the channel region of the n-type MOS transistor region nTR. For this reason, stress effective for improving the performance of the transistor can be efficiently applied to the channel region of the n-type MOS transistor region nTR.

  On the other hand, in the p-type MOS transistor region pTR, a compressive stress is applied from the first surface side of the semiconductor layer 3 by the compressive stress film 21c formed on the first surface of the semiconductor layer 3, and the semiconductor layer The tensile stress in the gate width direction Y is applied from the second surface side of the semiconductor layer 3 by the stress film (tensile stress film) 20 formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 19A. . For this reason, the compressive stress in the gate length direction X and the tensile stress in the gate width direction Y act simultaneously on the channel region of the p-type MOS transistor region pTR. For this reason, stress effective for improving the performance of the transistor can be efficiently applied to the channel region of the p-type MOS transistor region pTR.

  As shown in FIG. 10, when applied to an SRAM cell including a drive transistor Tr1, an access transistor Tr2, a load transistor Tr3, etc., each composed of a MOS transistor, the gate length on the second surface of the semiconductor layer is similar to the above. A streak-like stress transmission pattern Pt is formed along the direction X, and the stress transmission pattern Pt is covered with a stress film (not shown) that generates a tensile stress, whereby each transistor region is pulled in the gate width direction Y. Stress can be applied to improve the performance of the transistor.

  In the first embodiment, the insulating film 19 is formed on the second surface of the semiconductor layer 3, and the insulating film 19 is patterned, whereby the stress transmission pattern is formed on the second surface of the semiconductor layer 3. However, the present invention is not limited to this. For example, the BOX layer 2 that covers the second surface of the semiconductor layer 3 after thinning the SOI substrate as shown in FIG. 11A, the stress transmission pattern 2A is formed on the second surface of the semiconductor 3 as shown in FIG. 11A, and then the stress transmission pattern 2A is covered as shown in FIG. 11B. In a state, the stress film 20 may be formed on the second surface of the semiconductor layer 3.

  As another example, the BOX layer 2 covering the second surface of the semiconductor layer 3 after the SOI substrate is thinned as shown in FIG. As shown in FIG. 12 (B), after the groove processing is performed on the second surface of the semiconductor layer 3 to form the stress transmission pattern 3A having irregularities in the thickness direction of the semiconductor layer 3, The stress film 20 may be formed on the second surface of the semiconductor layer 3 so as to cover the stress transmission pattern 3A. Further, the BOX film 2 may be removed before the groove processing.

[Second Embodiment]
13A and 13B are diagrams illustrating a configuration example of a semiconductor device according to the second embodiment of the present technology . In the second embodiment of the present technology , the same reference numerals are given to the same parts as those of the semiconductor device described in the first embodiment. In FIG. 13, the n-type MOS transistor region nTR and the p-type MOS transistor region pTR are element-isolated by the element isolation layer 4.

In the n-type MOS transistor region nTR, a gate electrode 6 is formed on the first surface of the semiconductor layer 3, and a first tensile layer made of a silicide layer is formed on the second surface of the semiconductor layer 3 on the opposite side. A stress film 31 and a second tensile stress film 32 made of an insulating film are formed. These tensile stress films 31 and 32 are formed in the n-type MOS transistor region nTR so as to cover the second surface of the semiconductor layer 3. The first tensile stress film 31 is formed using a silicide film such as NiSi, CoSi, TiSi, for example. On the other hand, the second tensile stress film 32 is formed using an insulating film such as SiN, SiO ₂ , or SiON.

On the other hand, in the p-type MOS transistor region pTR, the gate electrode 6 is formed on the first surface of the semiconductor layer 3, and the insulating film is formed on the second surface of the semiconductor layer 3 on the opposite side. A compressive stress film 33 is formed. The compressive stress film 33 is formed in the p-type MOS transistor region pTR so as to cover the second surface of the semiconductor layer 3. The compressive stress film 33 is formed using an insulating film such as SiN, SiO ₂ , or SiON.

  In manufacturing the semiconductor device having the above configuration, for example, after thinning the SOI substrate as shown in FIG. 2B according to the same method as in the first embodiment, in the n-type MOS transistor region nTR, As shown in FIG. 14A, a first tensile stress film 31 made of a silicide layer is formed on the second surface of the semiconductor layer 3 by a film forming process such as sputtering and an annealing process. As shown in FIG. 5B, a second tensile stress film 32 made of an insulating film is formed on the second surface of the semiconductor layer 3 so as to cover the first tensile stress film 31. In the p-type MOS transistor region pTR, although not shown, prior to the film forming process of the first tensile stress film 31, for example, the second surface of the semiconductor layer 3 is covered with a photoresist film, Thereafter, prior to the formation of the compressive stress film 33, the photoresist film is peeled off. As a result, the first tensile stress film 31 can be formed only in the n-type MOS transistor region nTR.

In the semiconductor device according to the second embodiment of the present technology , the stress films (31 to 33) are formed on the second surface of the semiconductor layer 3 opposite to the first surface on which the gate electrode 6 is formed. By applying stress to the semiconductor layer 3 by the stress films (31 to 33), the stress is effectively applied to the channel region of the semiconductor layer 3 without depending on the layout such as the inter-gate distance in the MOS transistor region. be able to. For the n-type MOS transistor region nTR, since the first tensile stress film 33 is formed using a silicide layer that generates a strong tensile stress, the first tensile stress film 31 and the second tensile stress film 31 are formed. Due to the synergistic effect of the tensile stress film 32, a tensile stress in the channel length direction X can be strongly applied to the channel region of the semiconductor layer 3. For this reason, the performance of the n-type MOS transistor can be improved reliably. On the other hand, in the p-type MOS transistor region pTR, compressive stress due to the compressive stress film 33 is applied to the semiconductor layer 3, so that compressive stress in the channel length direction X can be applied to the channel region of the semiconductor layer 3. For this reason, the performance of the p-type MOS transistor can be improved.

  Furthermore, when a stress film using a silicide film is compared with a stress film using an insulating film, a stress film using a silicide film generates a relatively stronger stress than a stress film using an insulating film. To do. For this reason, for example, when a tensile stress film made of a silicide film and a compressive stress film made of an insulating film are formed in the same region on the substrate, the stress of the tensile stress film overcomes the stress of the compressive stress film. A tensile stress is applied to the substrate. Therefore, a tensile stress film made of a silicide film is formed in the n-type MOS transistor region nTR, and both the n-type MOS transistor region nTR and the p-type MOS transistor region pTR are made of an insulating film so as to cover the tensile stress film. When a compressive stress film is formed, a tensile stress in the gate length direction X is applied to the channel region of the semiconductor layer 3 in the n-type MOS transistor region nTR, while a gate is applied to the channel region of the semiconductor layer 3 in the p-type MOS transistor region pTR. A compressive stress in the long direction X can be applied. Therefore, transistor performance can be improved in both the n-type MOS transistor region nTR and the p-type MOS transistor region pTR. In addition, since it is not necessary to separately form a stress film using an insulating film for the n-type MOS transistor region nTR and the p-type MOS transistor region pTR, the manufacturing process can be reduced.

  Incidentally, the stress film using a silicide film such as NiSi, CoSi, TiSi is the tensile stress film 20t (see FIG. 7) formed in the n-type MOS transistor region nTR or the gate length direction X in the first embodiment. It is also possible to apply to the stress film 20 (see FIGS. 8 and 9) covering the stress transmission pattern 19A along the line.

3 Semiconductor layer
4 Device isolation layer
5 Gate insulation film
6 Gate electrode
9, 9n, 9p Source / drain region
2A, 3A, 19A Stress transmission pattern
20, 20t, 20c Stress film
31 First tensile stress film (silicide film)
32 Second tensile stress film
33 Compressive stress film
X Gate length direction
Y Gate width direction

Claims (5)

A semiconductor layer having a transistor region;
A gate electrode formed on the first surface of the semiconductor layer in the transistor region via a gate insulating film;
A tensile stress film formed using a silicide film on a second surface of the semiconductor layer opposite to the first surface of the n-type transistor region of the semiconductor layer ;
A compressive stress film formed using an insulating film on a second surface of the semiconductor layer opposite to the first surface of the p-type transistor region of the semiconductor layer;
The semiconductor device characterized by Ru with a.   Prior to the film forming process of the tensile stress film, the second surface is covered with a photoresist film,
  Thereafter, prior to the formation of the compressive stress film, the photoresist film is peeled off.
The semiconductor device according to claim 1.   The silicide film is NiSi, CoSi or TiSi.
The semiconductor device according to claim 1, wherein:   Another tensile stress film made of an insulating film is formed on the tensile stress film formed on the second surface.
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   The other tensile stress film is SiN, SiO. ₂ Or SiON
The semiconductor device according to claim 4.

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