JP5565038B2 - FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE - Google Patents

Description

  The present invention relates to a field effect transistor, a manufacturing method thereof, and an image display device using the same.

In recent years, many display devices such as a liquid crystal display, an organic EL display, and an electrophoretic display, which are widely used in recent years, use an active matrix drive device using a thin film transistor (TFT) as a display switching device. For such a TFT as a display switch, a field effect transistor (FET) made of a semiconductor disposed between a gate electrode, a gate insulating layer, a source-drain electrode, and a source-drain electrode is used. The driving principle of the FET is to control the charge carrier amount consisting of electrons m or holes in the semiconductor by applying a voltage to the gate electrode, and to control the charge transfer between the source and drain, that is, the current. It plays the role of a switch by a special action.
Conventionally, the semiconductors of the TFT array as described above are those using amorphous or polycrystalline thin film silicon as a semiconductor. Generally, each layer such as an electrode, a semiconductor, and an insulating layer of a thin film silicon TFT is used. Requires a vacuum process and a high-temperature process of 300 ° C. or higher, and is formed by a relatively complicated and expensive process.

  On the other hand, in recent years, semiconductor materials that can be formed at low temperatures such as transparent oxide semiconductors and organic semiconductors have been developed, and it is possible to realize low-temperature, high-speed, and low-cost processes such as having electrical conductivity characteristics higher than amorphous silicon. It has become. In addition, by adopting a low temperature process, a flexible base material such as a plastic film or paper is adopted, and application to production by roll-to-roll or production of a flexible device is expected.

However, in general, a flexible substrate such as a plastic film or paper has micron-order irregularities on the surface due to foreign matter adhesion or scratches, or the surface shape of the material itself. When these flexible substrates are used as support substrates, the surface irregularities cause electrical shorts, leaks, or disconnections in the electronic circuits and elements formed thereon, causing malfunctions of the elements. It was.
In order to avoid this, in general, attempts have been made to smooth the surface of the flexible substrate by forming the surface of the flexible substrate by a technique such as coating or vapor deposition. (See Patent Document 1)

Japanese Patent No. 2724026

However, the technique described in Patent Document 1 for directly applying and forming a base layer on the surface of a flexible substrate was able to achieve a certain result. There has been a problem that surface irregularities are caused again by entraining foreign matters resulting from the process of forming the underlayer.
Furthermore, the above-mentioned problems such as electrical shorts, leaks, or disconnections are problems that arise only when foreign matter having a very small size of 1 micron in diameter is mixed in. It was very difficult to recognize its presence on one substrate.

  Therefore, the present invention has been made paying attention to the above-mentioned problems, and is produced with high reproducibility and high yield by almost eliminating the unevenness of the underlayer formed on the surface of the flexible substrate. It is an object of the present invention to provide a highly reliable field effect transistor and an image display device as a suitable flexible device.

The invention according to claim 1 for achieving the above object includes a first step of obtaining a first laminate by forming a base first layer on a surface of a first substrate;
A second step of forming a self-assembled monolayer on the smooth surface of the second substrate, and further forming a base second layer on the self-assembled monolayer to obtain a second laminate;
A third step of obtaining a third laminate including the first laminate and the second laminate by bonding the foundation first layer and the foundation second layer;
The fourth laminate in which the first substrate and the base layer including the base first layer and the base second layer are integrated is peeled from the second substrate and the self-assembled monolayer. A fourth step;
And a fifth step of forming a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a semiconductor layer in this order on the base layer of the fourth stacked body. Yes.

  According to the first aspect of the present invention, since the surface roughness of the base second layer serving as the surface of the base layer formed on the first substrate can be reduced as much as possible by the second step, the base Problems such as short circuit, leakage, and disconnection of each transistor element formed on the second layer can be prevented. Therefore, a field effect transistor can be manufactured with high reproducibility and high yield.

According to a second aspect of the present invention, in the method for manufacturing a field effect transistor according to the _{first aspect,} the surface roughness Rms ₁ of the second substrate is 0.15 nm or less.
The invention according to claim 3 is characterized in that, in the method of manufacturing a field effect transistor according to claim 1 or 2, the method further comprises a step of cleaning the second substrate before the second step. Yes.

According to a fourth aspect of the present invention, in the method of manufacturing a field effect transistor according to any one of the first to third aspects, the step of surface-treating the first substrate before the first step. It is characterized by including.
The invention according to claim 5 is the field effect transistor manufacturing method according to any one of claims 1 to 4, wherein the underlying second layer is made of an acrylic resin, and the second step includes: The base second layer is formed by applying a compound containing a (meth) acrylic monomer or a compound having an epoxy group and then curing it.

The invention according to claim 6 is the field effect transistor manufacturing method according to any one of claims 1 to 5, wherein the first step of the first stacked body is performed in the third step. A step of fixing one surface of the substrate to the third substrate is included.
The invention according to claim 7 is the field effect transistor manufacturing method according to any one of claims 1 to 6, wherein the fifth step is the gate electrode, The formation of at least one of the gate insulating layer, the source electrode, the drain electrode, and the semiconductor layer uses a printing method.

  According to the present invention, a field effect transistor as a flexible device can be obtained in a high yield even with the first substrate with good reproducibility, and as a result, it is excellent in impact resistance, lightweight, and can be curved. Possible image display devices can also be provided.

It is sectional drawing which shows the structure in one Embodiment of the field effect transistor which concerns on this invention. It is sectional drawing which shows the 1st thru | or 3rd process in one Embodiment of the manufacturing method of the field effect transistor which concerns on this invention. It is sectional drawing which shows the 4th process in one Embodiment of the manufacturing method of the field effect transistor which concerns on this invention. It is sectional drawing which shows the 5th process in one Embodiment of the manufacturing method of the field effect transistor which concerns on this invention. 6 is a cross-sectional view showing a configuration of a field effect transistor having a top contact structure manufactured according to Example 4. FIG. FIG. 10 is a cross-sectional view illustrating a configuration of a field effect transistor having a top gate structure manufactured according to Example 5;

Embodiments of a field effect transistor, a manufacturing method thereof, and an image display device according to the present invention will be described below with reference to the drawings. Note that, in the description of the present embodiment, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.
FIG. 1 is a cross-sectional view showing the configuration of an embodiment of a field effect transistor according to the present invention. 2A to 2D are cross-sectional views showing first to third steps in an embodiment of the method for manufacturing a field effect transistor according to the present invention. Moreover, FIG. 3 is sectional drawing which shows the 4th process in one Embodiment of the manufacturing method of the field effect transistor based on this invention. FIG. 4 is a sectional view showing a fifth step in one embodiment of the method for producing a field effect transistor according to the present invention.
As shown in FIG. 1, a field effect transistor 1 according to the present invention includes a first substrate 10, a base layer 20, a gate electrode 30, a gate insulating layer 40, a source on the first substrate 10. The electrode 50, the drain electrode 60, the source electrode 50, and the semiconductor layer 70 are formed at least in this order.

<First substrate>
The first substrate 10 is not particularly limited as long as it has a sheet shape and a flat surface, and can be appropriately selected according to the purpose. For example, soda lime glass, quartz glass, borosilicate glass, plastic film And paper.
The first substrate 10 is preferably a flexible substrate, and such materials include paper, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), cycloolefin polymer, polyimide (PI), and polyether. Examples include sulfone (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyallylate, and triacetyl cellulose (TAC).

  In addition, examples of the material of the first substrate 10 include conductive or semiconductive base materials such as a stainless sheet, an aluminum foil, a copper foil, and a silicon wafer. These conductive or semiconductive base materials are more preferably used by coating or vacuum depositing an insulating material such as a polymer material or a metal oxide on the surface. Further, the above substrate may be provided with a surface treatment layer such as an easy adhesion layer on the surface, or may be subjected to a surface treatment such as corona treatment, plasma treatment, UV / ozone treatment.

<Underlayer>
The foundation layer 20 includes a foundation first layer 21 and a foundation second layer 22. The ground first layer 21 is a layer made of an adhesive resin in contact with the first substrate 10. Underlying the second layer 22 is formed on the underlying first layer 21, the underlying surface roughness Rms ₂ of the first layer 21 and the surface in contact with the opposite surface 22a is, is a layer consisting of 0.3nm or less of the resin .
<Primary first layer>
The base first layer 21 has sufficient insulating properties and can form a sticky or adhesive state. If a thin film having a thickness of 10 μm or less can be formed, the base first layer 21 is sticky when cured or semi-cured. Resin, polymer compound, organometallic compound and degradation product thereof having the property or adhesiveness can be used.

  Examples of such materials include organic materials such as polyvinylphenol (PVP), polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyimide (PI), epoxy resin, polysiloxane, polysilsesquioxane, and butadiene rubber. High molecular compounds, or a mixture thereof, and further, alkoxides, chlorides, and their alkoxides whose main elements are metals such as silicon, titanium, tantalum, aluminum, niobium, zirconium, copper, nickel, indium, and hafnium. Also included are decomposed oxides, or mixtures of these and resins. In addition, a resin compound that is melted or fused by heating can also be used.

<Base 2nd layer>
The underlying second layer 22 is not limited to this as long as it has sufficient insulation and can form a thin film of 1 μm or more and 10 μm or less, and more preferably a thin film of 3 μm or more.
The base second layer 22 can use a resin or a polymer compound. For example, an acrylic resin, epoxy resin, polyvinyl phenol (PVP), polyvinyl alcohol (PVA), polyvinyl chloride (PVC) that is cured by UV irradiation or heating. ), Polyimide (PI), polysiloxane, polysilsesquioxane, butadiene rubber, or other organic polymer compounds, or a mixture thereof. Furthermore, silicon, titanium, tantalum, aluminum, niobium, zirconium, It is also possible to use alkoxides, chlorides, and decomposed oxides thereof having a metal as a central element such as copper, nickel, indium and hafnium, or a mixture thereof and a mixture of the above resin or polymer compound.

The thin film may have a desired film thickness by lamination, but it is necessary to appropriately select a material and a coating method that do not cause defects such as cracks in the thin film. From the above viewpoint, a resin compound or a mixed compound of a resin and a metal oxide is usually used.
Here, the acrylic resin refers to a resin cured using a compound containing a (meth) acrylic monomer as a raw material, and the (meth) acrylic monomer refers to both an acrylic monomer and a methacrylic monomer, and a polyfunctional acrylic monomer and Also includes methacrylic monomers. The undercoat second layer preferably has a certain degree of hardness so as not to cause scratches on the surface in the subsequent process, and is desirably H or higher, preferably 3H or higher, in the pencil hardness test of JIS-K5400.

<Electrode>
As materials for each of the gate electrode 30, the source electrode 50, and the drain electrode 60, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), and indium oxide are used. Oxide materials such as cadmium (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO ₄ ), zinc tin oxide (Zn ₂ SnO ₄ ), and indium zinc oxide (In—Zn—O) are preferably used.

  In addition, it is preferable that the gate electrode 30, the source electrode 50, and the drain electrode 60 be made of a material obtained by doping impurities into the oxide material in order to increase conductivity. For example, indium oxide doped with tin, molybdenum, titanium, tin oxide doped with antimony or fluorine, zinc oxide doped with indium, aluminum, gallium, and the like.

  Among these, indium tin oxide obtained by doping tin into indium oxide (commonly referred to as ITO) is particularly preferably used because of its low resistivity. In addition, low resistance metal materials such as Au, Ag, Cu, Cr, Al, Mg, and Li are also preferably used. Further, a laminate in which a plurality of conductive oxide materials and low resistance metal materials are stacked can be used. In this case, a three-layer structure in which a conductive oxide thin film / metal thin film / conductive oxide thin film is laminated in order in order to prevent oxidation or deterioration with time of the metal material is particularly preferably used.

An organic conductive material such as PEDOT (polyethylenedioxythiophene) can also be suitably used. The gate electrode, the source electrode, and the drain electrode may all be the same material, or may be all different materials. However, in order to reduce the number of steps, it is more desirable that the source electrode and the drain electrode are made of the same material.
These electrodes are formed by vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (chemical vapor deposition), photo CVD, hot wire CVD, or the like. In addition, the conductive material described above in an ink form or a paste form can be applied by screen printing, letterpress printing, an ink jet method or the like, and baked, but is not limited thereto.

<Gate insulation layer>
Examples of the gate insulating layer 40 include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride (SiN _x O _y ), aluminum oxide, tantalum oxide, yttrium oxide, hafnium oxide, hafnium aluminate, zirconia oxide, and titanium oxide. Or, polyacrylate such as PMMA (polymethyl methacrylate), PVA (polyvinyl alcohol), PS (polystyrene), polyimide, polyester, epoxy resin, polyvinylphenol (PVP), polyvinyl chloride (PVC), polyvinylidene fluoride (PVDF) , Polytetrafluoroethylene (PTFE), polydimethylsiloxane (PDMS), polysilsesquioxane, butadiene rubber and the like, but are not limited thereto.
In order to suppress the gate leakage current, the resistivity of the insulating material is preferably 1.0 × 10 ¹¹ Ωcm or more, more preferably 1.0 × 10 ¹⁴ Ωcm or more. The film thickness is preferably 50 nm or more and 2 μm or less.

  The gate insulating layer 40 is formed by vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (Chemical Vapor Deposition), photo CVD, hot wire CVD, spin coating, dip coating, It can be formed by using a screen printing method, a micro gravure printing method, a die coating method or the like. The gate insulating layer 40 may be used as a single layer, or a stacked layer of a plurality of layers may be used. In addition, a material whose composition is inclined toward the growth direction of the film is also preferably used.

The gate insulating layer 40 may be subjected to surface treatment such as corona treatment, plasma treatment, UV / ozone treatment, etc., but care must be taken so that the surface roughness due to the treatment does not become rough. The surface of the gate insulating layer is preferably relatively smooth and free from pinholes, protrusions, and undulations.
Furthermore, the gate insulating layer 40 may form a self-assembled monolayer on the surface, and the forming method includes a method of depositing a compound that forms the self-assembled monomolecule on a corresponding substrate under vacuum, A method of immersing a substrate in a compound solution, a Langmuir-Blodgett method, or the like can be used, but is not limited thereto.

<Semiconductor layer>
As the semiconductor layer 70, a metal oxide semiconductor material or an organic semiconductor material can be preferably used. The metal oxide semiconductor material used in the semiconductor 70 according to the embodiment of the present invention is an oxide containing one or more elements of zinc, indium, tin, tungsten, magnesium, and gallium, zinc oxide, indium oxide, Examples thereof include, but are not limited to, materials such as indium zinc oxide, tin oxide, tungsten oxide (WO), and indium gallium zinc oxide (In—Ga—Zn—O).

  These materials are substantially transparent and have a band gap of 2.8 eV or more, and preferably a band gap of 3.2 eV or more. The structure of these materials may be single crystal, polycrystal, microcrystal, crystal / amorphous mixed crystal, nanocrystal scattered amorphous, or amorphous. The film thickness of the semiconductor layer 60 is desirably at least 20 nm.

<Method of manufacturing field effect transistor>
The field effect transistor manufacturing method according to the present invention includes a first step shown in FIG. 2 (a), a second step shown in FIG. 2 (b), and a third step shown in FIG. 2 (c). And a fourth step shown in FIGS. 3A and 3B and a fifth step shown in FIGS. 4A to 4E.
Here, as described above, the field effect transistor according to the present invention is characterized in that the surface 22a of the underlayer 20 is extremely smooth to the extent that the irregularities disappear, and the surface roughness Rms _{2 of the} surface 22a. Is 0.3 nm or less. That is, by providing a very smooth surface, electronic circuits and elements formed on the base layer 20 can be manufactured with high yield without defects. The field effect transistor manufacturing method according to the present invention is characterized by including the first to fifth steps in order to obtain a smooth surface free from foreign matter, protrusions and irregularities on the surface.

<First step>
The first step is a step of obtaining the first stacked body 101 by forming the base first layer 21 on the surface of the first substrate 10 as shown in FIG.
As described above, the raw material that gives the resin or polymer compound for forming the base first layer 21 is the same as that for the base second layer 22, or lamination, thermal fusion, thermocompression bonding, spray deposition, or the like is used. To form on the substrate 10. The base first layer 21 is preferably made of a material having adhesiveness or adhesiveness when cured or dried, or the next step is preferably performed in a semi-cured or semi-dried state where the material is not completely cured.

<Second step>
In the second step, as shown in FIG. 2B, a self-assembled monomolecular film 90 is formed on the smooth surface of the second substrate 80, and a second substrate is formed on the self-assembled monomolecular film 90. In this step, the second stacked body 102 is obtained by forming the layer 22.
As the second substrate 80, a substrate having a smooth surface 80a having a surface roughness Rms ₁ of 0.15 nm or less can be used. Specifically, soda lime glass, borosilicate glass, quartz, sapphire, alumina, MgO, SiC, ZnO, titania, silicon, or the like can be used. Usually, soda lime glass, surface-polished silicon wafers, silicon wafers with thermal oxide films, and the like can be preferably used.

These second substrates 80 need to be sufficiently cleaned and flattened so that there are no foreign matter, protrusions or depressions on the surface, and are usually UV / ozone cleaning, brush cleaning, ultrasonic cleaning, plasma cleaning. A smooth surface can be obtained by using a method such as corona cleaning or a method such as chemical mechanical polishing (CMP) or self-planarization by CVD thin film formation.
A surface layer capable of reducing the surface energy and maintaining smoothness is formed on the surface of the second substrate 80. As this surface layer, a self-assembled monolayer 90 is formed in the present invention. As the self-assembled monomolecular film 90, an organic compound having a reactive functional group at one end of the molecule and a substituent having a function of lowering the surface energy at the other end is used. As the reactive functional group, it is necessary to select a functional group capable of reacting with the surface of the previously selected second substrate 80. For example, when glass, silicon wafer, titanium oxide, or the like is selected as the second substrate, When a trichlorosilane group or trimethoxysilane group is selected and alumina or sapphire is selected, a phosphonic acid group is preferably selected. In addition, a carboxylic acid group, a phosphoric acid group, an alcohol group, a catechol group, an amino group, a thiol group, and the like can be selected.

  As the substituent having a function of reducing the surface energy, an alkyl group, a perfluoroalkyl group, a phenylalkyl group having a benzene ring or a toluene ring at the end of the alkyl group, a tolylalkyl group, or a phenoxyalkyl group may be selected. The above alkyl group may have a straight chain structure, may have a branched structure, or may have an ether structure, an ethylene structure, or an acetylene structure in the middle or at the end of the alkyl chain. good. Moreover, a phenyl group, a tolyl group, etc. which do not have an alkyl structure in a molecule | numerator can also be selected suitably. More specifically, examples of the self-assembled monolayer 90 having the above characteristics include, for example, phenyltrichlorosilane, p-tolyltrichlorosilane, 3-phenylpropyltrimethoxysilane, butyltrichlorosilane, octyltrichlorosilane, and octyltrimethoxysilane. Octyltriethoxysilane, octadecyltrichlorosilane, octadecyltrimethoxysilane, octadecyldimethylchlorosilane, 11-phenoxyundecyltrichlorosilane, 11- (chlorodimethylsilylmethyl) tricosane, tridecafluoro-1,1,2,2-tetrahydro Octyltrichlorosilane, octylphosphonic acid, octadecylphosphonic acid, octanoic acid, dodecanoic acid, hexanol, octanol, octanethiol, pentafluorobenzene It can be used Lumpur like but not limited thereto.

In the method of forming the self-assembled monolayer 90 on the second substrate 80, first, the surface of the second substrate 80 is subjected to surface treatment such as corona treatment, plasma treatment, UV / ozone treatment, and the surface is hydrophilized. Then, a method of depositing a compound forming a self-assembled monolayer on the surface of the corresponding second substrate under vacuum, immersing the second substrate in a solution of the compound forming the self-assembled monolayer For example, a method of forming on the second substrate by the Langmuir-Blodgett method can be used, but the method is not limited to these. However, as a method for obtaining a self-assembled monolayer having a denser and smoother surface, see, for example, Langmuir 19, 1159 (2003). J. et al. Phys. Chem. B 110, 21101 (2006). Or J. Am. Chem. Soc. 131, 9396 (2009) is more preferably used. Surface roughness Rms ₁ surface 80a of the second substrate 80 after the formation of the self-assembled monolayer 90 is 0.3nm or less.

  Here, when the base second layer 22 is formed on the second substrate 80 on which the self-assembled monolayer 90 is formed, a resin or a polymer compound that forms the base second layer 22 is provided. A raw material is dissolved in water, alcohol or an organic solvent to form a solution for forming a second underlayer, which is applied or printed on the self-assembled monolayer 90 as shown in FIG. Alternatively, it can be formed by firing, UV irradiation, or electron beam irradiation.

  As a specific forming method, an existing wet coating method such as micro gravure coating, dip coating, screen coating, die coating, spin coating, flexographic printing, etc. can be used, and the film thickness after curing is preferably 1 μm or more and 10 μm or less. Preferably, it is not limited to these as long as a film thickness of 3 μm or more can be obtained. Further, drying, baking, UV irradiation, or electron beam irradiation may be performed under vacuum.

<Third step>
In the third step, as shown in FIG. 2 (c), the first layer 21 and the second layer 22 are bonded together to form a third layer 101 composed of a first layered body 101 and a second layered body 102. This is a step of obtaining the laminate 103.
As shown in FIG. 2C, the first base body 21 obtained as described above is bonded to the base second layer 22 so that the first stacked body 101 and the second stacked body 102 are bonded together. At this time, the base first layer 21 is preferably sticky or adhesive, or is preferably semi-cured or semi-cured. Further, the base first layer 21 may be fused in a molten state or a semi-molten state by heating.

  When the base first layer 21 and the base second layer 22 are bonded together, pressure may be applied from one or both base materials, or heating may be performed. Further, they may be bonded together while being irradiated with ultraviolet rays or electron beams. Further, after bonding, heating or pressure may be applied, or ultraviolet rays or electron beams may be irradiated. Prior to the bonding step, the surface of the base first layer 21 and the base second layer 22 may be subjected to a surface treatment such as UV / ozone treatment, plasma treatment, corona treatment, acid treatment, or alkali treatment.

  The third step may include a step of fixing one surface of the first substrate 10 of the first stacked body 101 to a third substrate (not shown) as a support substrate. . In this way, the first substrate 10 is fixed to one surface (the surface opposite to the surface in contact with the base first layer 21) on the third substrate (not shown) as the support substrate, and the first laminated layer By bonding the body 101 and the second stacked body 102 together, uniform adhesion without unevenness is possible, and occurrence of inadvertent peeling in a later process is reduced.

<4th process>
As shown in FIGS. 3A and 3B, the fourth step includes the first substrate 10 and the base layer 20 (the base first layer) from the second substrate 102 and the self-assembled monolayer 90. 21 and the base second layer 22) are peeled off from the fourth laminated body 104.
Here, when the first substrate 10 and the second substrate 80 are peeled from each other, the base first layer 21 and the base second layer 22 are bonded together to form the base layer 20 together. Formed on top. Since the self-assembled monolayer 90 having a low surface energy is formed on the surface of the second substrate 80, the underlayer 20 can be easily peeled off.

Surface 22a of the base which was in contact with the self-assembled monolayer 90 second layer 22 is equivalent to the surface roughness of the surface of the self-assembled monolayer 90, the surface roughness Rms ₂ is 0.3nm or less is there. Further, by sufficiently increasing the thickness of the base second layer 22, mixing of foreign matter, dust, or the like in the atmosphere does not adversely affect the smoothness of the surface of the base layer.
By using the underlayer forming method described above, an electronic circuit or an element formed over the underlayer is manufactured with high yield without a defect.

<Fifth step>
In the fifth step, as shown in FIG. 5A, first, the gate electrode 30 is stacked on the base layer 20 of the fourth stacked body 104.
Next, as illustrated in FIG. 5B, the gate insulating layer 40 is stacked on the base layer 20 and the gate electrode 30.
Thereafter, as shown in FIG. 5C, the source electrode 50 and the drain electrode 60 are stacked on the gate insulating layer 40.
Thereafter, as shown in FIG. 5D, the semiconductor layer 70 is stacked on the gate insulating layer 40 so as to be sandwiched between the source electrode 50 and the drain electrode 60. As described above, the field effect transistor 1 is manufactured through the first to fifth steps so far.

  As the gate electrode 30, the source electrode 50, and the drain electrode 60 of the present invention, metals such as Al, Cr, Mo, Cu, Au, Pt, Pd, Fe, Mn, and Ag are formed by methods such as PVD, CVD, and plating. After film formation, it can be formed using a known method such as photolithography. In addition, known transparent conductive materials such as indium / tin oxide (ITO) fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), PEDOT: PSS, polyaniline, polythiophene A known organic conductive material or the like can also be used. However, when these have a relatively high wiring resistance, it is more preferable to reduce the resistance by using a metal bus electrode. In addition, after processing the above metals, transparent oxides, conductive materials such as organic conductive polymers or their precursors into solutions, pastes, nanoparticle dispersions, etc., they are coated by a printing method, dried, It can also be formed by baking, photocuring or aging. The printing method to be used is not particularly limited, but it is possible to use a patternable printing method such as letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing, inkjet, thermal transfer printing, dispenser, etc. Since simplification, cost reduction, and high speed can be achieved, it is more preferable. Further, a spin coating, a die coating, a micro gravure coating, a dip coating, and the like may be combined with a patterning method such as photolithography. Further, a combination of the above printing methods may be used.

  The semiconductor 70 made of a metal oxide is formed using a sputtering method, a pulse laser deposition method, a vacuum evaporation method, a CVD method, an MBE (Molecular Beam Epitaxy) method, a sol-gel method, etc., preferably a sputtering method, Pulse laser deposition, vacuum deposition, and CVD. Examples of the sputtering method include RF magnetron sputtering method, DC sputtering method, vacuum deposition method include heating evaporation method, electron beam evaporation method, ion plating method, and CVD method include hot wire CVD method and plasma CVD method. It is not something.

  Examples of the organic semiconductor material used for the semiconductor 70 include π-conjugated organic polymers exhibiting semiconductivity, such as polypyrroles, polythiophenes, polyanilines, polyallylamines, fluorenes, polycarbazoles, polyindoles, poly (p -Phenylene vinylene) and the like, low molecular substances having a π-conjugated system, for example, polycyclic aromatic derivatives such as pentacene, phthalocyanine derivatives, perylene derivatives, tetrathiafulvalene derivatives, tetracyanoquinodimethane derivatives, fullerenes, Carbon nanotubes and the like can be used, but this is not a limitation.

  The method for forming the organic semiconductor can be a vacuum deposition method, a CVD method, a printing method using a solution, or the like, but it is applied using a semiconductor soluble in a solvent from the viewpoint of productivity and cost reduction. More preferably, the method is used. When using the printing method, there is no particular limitation, but letterpress printing, intaglio printing, planographic printing, reverse offset printing, screen printing method, ink jet, thermal transfer printing, dispenser, spin coating, die coating, micro gravure coating, dip A coat or the like can be used, and the above printing methods may be used in combination.

  The field effect transistor of the present invention may be used after further forming a sealing layer, an interlayer insulating layer, an upper pixel electrode, a protective film, a light shielding layer, an etch stopper layer, and the like. Although the details of the field effect transistor of the present invention have been described above along the structure of one pixel, the field effect transistor of the present invention normally has a pixel lighting device of an image display device by arranging pixels in an array. Can be used as In addition, a logic circuit can be manufactured by combining a field effect transistor in which p-type, n-type, or bipolar semiconductors are combined, a memory, a resistor, or the like with an electronic circuit.

Hereinafter, the present invention will be described in detail by way of specific examples. However, these examples are for the purpose of explanation, and the present invention is not limited thereto.
[Example 1]
A 1.1 mm thick soda lime glass was prepared as the second substrate, and the surface was cleaned using UV / ozone irradiation, brushing using a cleaning liquid, and ultrasonic waves. In addition, all the water used for washing | cleaning used the ultrapure water. At this time, the surface roughness Rms ₁ of the soda lime glass was 0.11 nm.

  The above soda lime glass is immersed in a trichloroethylene solution to which octadecyltrichlorosilane is added at 10 mmol / L for 10 hours in a dry nitrogen atmosphere, so that a monolayer of octadecyltrichlorosilane is formed as a self-assembled monolayer 90 on the surface of the soda lime glass. A molecular film was formed. At this time, the surface roughness of soda lime glass was 0.18 nm, and the pure water contact angle on the surface was 105 °.

The soda-lime glass obtained was coated with an acrylic resin-forming agent by microgravure coating, dried at 60 ° C., and then irradiated with UV light from a high-pressure mercury UV lamp under the condition of 400 mJ / cm ² , so An acrylic resin thin film 22 was formed on soda lime glass.
As the acrylic resin forming agent, a mixture of 20 g of dipentaerythritol hexaacrylate, 60 g of pentaerythritol triacrylate, 20 g of trimethylolpropane triacrylate, 30 g of isopropyl alcohol, and 4 g of a photopolymerization initiator Darocur 1173 (manufactured by Ciba) was used. The film thickness of the acrylic resin was 5 μm, and the pencil hardness was 3H.

Subsequently, a polyethylene naphthalate (PEN) film is used as the first substrate, and a polyimide adhesive is applied thereon by microgravure coating, and cured at 150 ° C. to form a polyimide resin thin film as a base first layer. Formed. The film thickness of the polyimide resin was 1 μm and had adhesiveness.
After the surface of the second ground layer was treated with UV / ozone for 10 minutes, the surface of the first ground layer thus obtained was laminated to the surface of the second ground layer, and passed through a laminating machine to pass the ground first layer and the second ground layer. The layer was allowed to stick. Lamination was performed at a pressure of 0.1 MPa, a speed of 1 cm / s, and room temperature.

After laminating, the substrate was baked at 180 ° C., and the first substrate and the underlying layer (underlying first layer + underlying second layer) were integrally peeled from the second substrate to produce an underlying layer forming substrate. At this time, was measured surface roughness Rms ₂ underlayer in an atomic force microscope, was 0.23 nm.

[Example 2]
As a second substrate, a 0.625 mm thick single-side polished 6-inch silicon wafer was prepared, and the surface was cleaned using UV / ozone irradiation and ultrasonic waves. In addition, all the water used for washing | cleaning used the ultrapure water. At this time, the surface roughness Rms ₁ of the silicon wafer was 0.10 nm.
The above silicon wafer is immersed in a hexane solution to which 3-phenoxypropyltrichlorosilane is added at 10 mmol / L for 10 hours under a dry nitrogen atmosphere, so that 3-phenoxypropyl is formed as a self-assembled monolayer 90 on the silicon wafer surface. A monomolecular film of trichlorosilane was formed. At this time, the surface roughness of the silicon wafer was 0.18 nm, and the pure water contact angle on the surface was 78 °.

  A polysilsesquioxane-based resin was applied to the obtained silicon wafer by microgravure coating and baked at 180 ° C. to form a polysilsesquioxane thin film on the silicon wafer as a second base layer. As the polysilsesquioxane resin, a 10% by mass 1-methoxy-2-acetoxypropane solution was used. The thickness of the polysilsesquioxane thin film was 5 μm, and the pencil hardness was H.

Subsequently, a polyimide (PI) film was used as the first substrate, PVP was applied thereon by microgravure coating, and dried at 100 ° C., thereby forming a PVP thin film as a base first layer. The PVP film thickness was 1 μm and was in a semi-cured state.
The surface of the obtained base first layer was bonded to the surface of the base second layer, and passed through a laminating machine to adhere the base first layer and the base second layer. Lamination was performed at a pressure of 0.1 MPa, a speed of 1 cm / s, and 100 ° C.
After laminating, the substrate was baked at 180 ° C., and the first substrate and the underlying layer (underlying first layer + underlying second layer) were integrally peeled from the second substrate to produce an underlying layer forming substrate. At this time, was measured surface roughness Rms ₂ of the surface of the underlying layer (underlying the second layer) by an atomic force microscope, was 0.21 nm.

[Example 3]
A field effect transistor having the same structure as that shown in FIG. 1 was formed in an 80 × 60 array. Specifically, a polyimide-based slightly adhesive resin was formed to a thickness of 1 μm on 1.1 mm thick soda lime glass, and the surface of the first substrate of the base layer forming substrate produced by the method of Example 1 was bonded.
Silver was formed as a gate electrode on the base layer forming substrate, and silver nanoparticles were printed in a pattern with a film thickness of 100 nm by an offset printing method, followed by baking at 180 ° C.

Subsequently, Cytop (manufactured by Asahi Glass Co., Ltd.) was spin-coated as an insulating layer, and then dried at 150 ° C. to form a film thickness of 500 nm.
A shadow mask was put on the insulating layer, and titanium and gold were successively formed at a film thickness of 5 nm and 50 nm by a vacuum vapor deposition method using an electron beam to form a pattern as a source electrode and a drain electrode.

Subsequently, a shadow mask was put on, and pentacene was deposited as a semiconductor at 40 ° C. to a thickness of 40 nm so as to straddle the source electrode and the drain electrode to obtain a field effect transistor.
-20V transfer characteristics of the field effect transistor obtained by the above gate voltage 20V, as measured by the drain voltage -15V, mobility 0.91cm ² / Vs or more 1.2 cm ² / Vs or less, on / off The ratio was about 105, and the threshold voltage was −2 to −1V.
None of the transistor elements in the 80 × 60 array were observed to have abnormal characteristics, and no leakage or short circuit of current between the gate electrode, the source electrode, and the drain electrode was observed.
Further, the obtained transistor array had flexibility by being peeled off from the soda lime glass, and could be used without changing its characteristics even when the substrate was bent.

[Example 4]
FIG. 5 is a cross-sectional view illustrating a configuration of a field effect transistor having a top contact structure manufactured according to the fourth embodiment.
In this example, field effect transistors having the structure shown in FIG. 5 were fabricated in an 80 × 60 array. Specifically, a polyimide-based slightly adhesive resin was formed to a thickness of 1 μm on 1.1 mm thick soda lime glass, and the surface of the first substrate 10 of the base layer forming substrate produced by the method of Example 2 was bonded. Aluminum having a thickness of 50 nm was formed as a gate electrode 30 on the underlayer 20 by vacuum deposition, and then patterned by photolithography and etching. Subsequently, SiON is formed to a thickness of 350 nm by RF sputtering using a silicon nitride (Si ₃ N ₄ ) target as the insulating layer 40, and then amorphous In − using an InGaZnO ₄ target as the semiconductor 70. Ga—Zn—O was formed to a thickness of 15 nm by an RF sputtering method, and was patterned by photolithography and etching.

Next, a resist was applied, dried and developed, and then ITO was formed with a film thickness of 50 nm by DC magnetron sputtering, and lift-off was performed to form the source electrode 50 and the drain electrode 60. The resulting array of field effect transistors was baked at 180 ° C.
-20V transfer characteristics of the field-effect transistor 1 obtained from the above the gate voltage 20V, as measured by the drain voltage 15V, mobility 4.0 cm ² / Vs or more 4.8 cm ² / Vs or less, on / off The ratio was about 106, and the threshold voltage was -1 or more and 0 V or less.

  None of the transistor elements in the 80 × 60 array were observed to have abnormal characteristics, and no leakage or short circuit of current between the gate electrode, the source electrode, and the drain electrode was observed. The obtained transistor array had flexibility by being peeled off from the soda lime glass, and could be used without changing its characteristics even when the substrate was bent.

[Example 5]
FIG. 6 is a cross-sectional view showing a configuration of a field effect transistor having a top gate structure manufactured according to the fifth embodiment.
In this example, field effect transistors having the structure shown in FIG. 6 were formed in an 80 × 60 array. Specifically, a polyimide slightly adhesive resin is formed with a thickness of 1 μm on a 1.1 mm thick soda lime glass, and the surface of the first substrate 10 on which the underlayer 20 produced by the method of Example 2 is bonded. It was. Titanium and gold were successively formed at 5 nm and 50 nm as the source electrode 50 and the drain electrode 60 on the underlayer 20 by vacuum vapor deposition, respectively, and then patterned by photolithography and etching.

  Subsequently, 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) was formed as a semiconductor 70 over the source and drain electrodes by letterpress printing. Subsequently, Cytop (manufactured by Asahi Glass Co., Ltd.) is spin-coated as the insulating layer 40, and then formed at a film thickness of 200 nm by drying at 150 ° C. Further, after spin-coating PVP, the film is dried at 180 ° C. The film was formed with a thickness of 600 nm.

Next, after forming aluminum with a film thickness of 40 nm as the gate electrode 30 on the insulating layer 40 by a vacuum deposition method, the field effect transistor 1 was obtained by patterning by photolithography and etching.
When the transfer characteristics of the field effect transistor 1 obtained as described above were measured at a gate voltage of 20 V to −20 V and a drain voltage of −15 V, the mobility was 0.2 cm ² / Vs to 0.3 cm ² / Vs, The off ratio was about 105, and the threshold voltage was 0 or more and −2 V or less.

  In addition, no transistor was observed in the characteristics of the transistor elements in the 80 × 60 array, and current leakage or short circuit between the gate electrode, the source electrode, and the drain electrode was not observed. The obtained transistor array had flexibility by being peeled off from the soda lime glass, and could be used without changing its characteristics even when the substrate was bent.

[Comparative Example 1]
An acrylic resin having the same composition ratio as that used in Example 1 was coated on polyethylene naphthalate (PEN) by microgravure coating, and formed with a film thickness of 3 μm to be used as a base layer forming substrate. At this time, the surface roughness Rms ₂ of the underlayer was measured by an atomic force microscope and found to be 0.38 nm.
Next, a polyimide slightly adhesive resin was formed to a thickness of 1 μm on soda lime glass having a thickness of 1.1 mm, and the surface of the PEN in the base layer forming substrate produced here was bonded.
Subsequently, an array of field effect transistors was produced thereon as in Example 3.

-20V transfer characteristics of the field effect transistor obtained by the above gate voltage 20V, as measured by the drain voltage -15V, mobility 0.89 cm ² / Vs or more 1.4 cm ² / Vs or less, on / off The ratio was about 105 and the threshold voltage was −2 to −1 V, and almost the same transistor characteristics as those in Example 1 were obtained. Of the transistor elements in the 80 × 60 array, three transistors had transfer characteristics. Abnormalities were observed, and in all cases, leakage of current between the gate electrode and the source electrode was observed.

From the above results, according to the method for producing a field effect transistor of the present invention, the unevenness of the underlayer can be made extremely small, so that a field effect transistor can be produced with high reproducibility and high yield. Thus, it is possible to obtain a highly reliable field effect transistor and video display device.
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

  The present invention is used for a display element such as a liquid crystal display element, organic EL, and electronic paper having a field effect transistor (FET) and an active matrix TFT array using the same as a back plate. In particular, it is used for flexible displays that are excellent in impact resistance, lightweight and capable of processing curved surfaces.

DESCRIPTION OF SYMBOLS 1 Field effect transistor 10 1st board | substrate 20 foundation | substrate layer 21 foundation | substrate 1st layer 22 foundation | substrate 2nd layer 30 gate electrode 40 gate insulating layer 50 source electrode 60 drain electrode 70 semiconductor layer 80 2nd board | substrate 90 self-organization monomolecule Film 101 First laminated body 102 Second laminated body 103 Third laminated body 104 Fourth laminated body

Claims (7)

A first step of obtaining a first laminate by forming a base first layer on a surface of a first substrate;
A second step of forming a self-assembled monolayer on the smooth surface of the second substrate, and further forming a base second layer on the self-assembled monolayer to obtain a second laminate;
A third step of obtaining a third laminate including the first laminate and the second laminate by bonding the foundation first layer and the foundation second layer;
The fourth laminate in which the first substrate and the base layer including the base first layer and the base second layer are integrated is peeled from the second substrate and the self-assembled monolayer. A fourth step;
A fifth step of stacking a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a semiconductor layer in this order on the base layer of the fourth stacked body; A method of manufacturing a field effect transistor. 2. The method of manufacturing a field effect transistor according to claim 1, wherein the second substrate has a surface roughness R _ms1 of 0.15 nm or less.   3. The method of manufacturing a field effect transistor according to claim 1, further comprising a step of cleaning the second substrate before the second step.   4. The method of manufacturing a field effect transistor according to claim 1, further comprising a step of surface-treating the first substrate before the first step. 5.   The second base layer is made of an acrylic resin, and the second step forms the second base layer by applying a compound containing a (meth) acrylic monomer or a compound having an epoxy group and then curing the compound. The method for manufacturing a field effect transistor according to claim 1, wherein:   6. The method according to claim 1, wherein the third step includes a step of fixing one surface of the first substrate of the first stacked body to a third substrate. A method for producing the field effect transistor according to 1.   7. The fifth step according to claim 1, wherein at least one of the gate electrode, the gate insulating layer, the source electrode, the drain electrode, and the semiconductor layer is formed by a printing method. A method for producing the field-effect transistor according to any one of the above items.

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