JP5565095B2 - Method for manufacturing printed circuit board - Google Patents

Description

  The present invention relates to a printed circuit board and a method for manufacturing the same.

  In recent years, along with demands for downsizing, high performance, and low prices for electronic devices, along with miniaturization of semiconductor chips and multi-terminals, miniaturization of circuit boards on which semiconductor chips are mounted, multilayering, and on circuit boards High-density mounting of electronic components is underway. As the number of terminals of a semiconductor chip is increased and the pitch of these terminals is reduced, the multilayer circuit board is also required to have fine wiring.

  Various forms such as a package substrate, a wafer level package (WLP), and a silicon interposer are known as the multilayer circuit board. In general, a semi-additive (SAP) method capable of finer wiring is applied to a wiring layer of a build-up substrate used for a package substrate, a rewiring layer of a wafer level package, or the like rather than a subtractive method. When forming a multilayer wiring, there are a method of stacking wirings by a semi-additive method and a method of contact-connecting wirings by via plugs by a photo via method or a damascene method.

  FIG. 1 and FIG. 2 are diagrams showing the structure of a conventional contact connection portion by an SAP method and a photo via or damascene method, respectively. In the case of the SAP method, as shown by a circle A1 in FIG. 1A, the first wiring layer M1 and the via layer V1 are formed on the base insulating layer 102 through the laminated film 103 of the Ti adhesion barrier layer and the Cu seed layer. Are piled up continuously. On the other hand, a second wiring layer M2 is formed on the via layer V1 and the interlayer insulating layer 104 via a laminated film 107 of a Ti adhesion barrier layer and a Cu seed layer. There is no interface between M1 and V1 due to Cu diffusion, but a Ti adhesion barrier layer is inserted between V1 and M2. Since the contact joint between V1 and M2 is a heterogeneous metal joint of Cu and Ti, Cu, which is more mobile than the metal material of the Ti adhesion barrier layer, causes migration in the via when thermal stress is applied. . As a result, as shown by a circle B1 in FIG. 1B, voids concentrate on the contact portion at the interface between M2 and V1, and a disconnection 110 occurs.

  In the case of FIG. 2, the via plug V1 and the second wiring layer M2 are continuously formed on the insulating layer 104 on M1 by a photo via or damascene method. Therefore, as shown in a circle A2 in FIG. 2A, there is no interface between V1 and M2, but a laminated film 207 of a Ti adhesion barrier layer and a Cu seed layer is inserted between M1 and V1. It will be. When thermal stress is applied, Cu in V1 is pulled in the direction of M2 by tensile stress. As a result, as shown in FIG. 2B, voids are concentrated on the interface between M1 and V1 forming a dissimilar metal junction, and a disconnection 210 occurs.

  The phenomenon shown in FIGS. 1B and 2B can also occur when the wiring is Ag, Au, Al, or the like, or when the adhesion barrier layer is W or the like. The disconnections 110 and 210 in FIGS. 1B and 2B are considered to be caused by the fact that the same metal material as the wiring layer is continuous without an interface in the upper or lower portion of the via plug. It is done.

  In order to prevent oxidation of the underlying Cu wiring exposed when forming the contact hole and prevent Cu diffusion into the insulating layer, the Cu wiring surface is formed on the barrier metal after the Cu wiring is formed in the wiring groove. The structure covered with is known (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 11-260967

  It is desirable to prevent disconnection of the contact junction in via connection. In order to realize this, the configuration shown in FIG. 3 is first considered in the process leading to the present invention. In FIG. 3A, the surface of Cu is covered with a barrier metal m1 in order to prevent a metal material constituting the first wiring layer M1, for example, Cu, from diffusing into an insulating layer (not shown). Further, in order to prevent the metal material of the second wiring layer M2 such as Cu from diffusing into the insulating layer and to secure the adhesion to the insulating layer, an adhesion layer barrier metal m1 is formed on the bottom surface of M2. To do. In this configuration, when the via layer V1 is made of a metal material m2 different from the barrier metal m1, a large number of M2 (Cu) / barrier metal m1 / via m2 / barrier metal m1 / M1 (Cu) is formed in the contact connection portion. A different metal interface exists, and the contact resistance increases.

  Therefore, as shown in FIG. 3B, it is conceivable to reduce the number of interfaces between different metals by using the same metal material for one of the barrier metals and the via layer to suppress an increase in contact resistance. However, since the other side of the via layer V1 is in contact with a different metal of m1 / m2, it eventually becomes the same state as in FIG. 1B, and when tensile stress due to heat is applied, as shown in FIG. A disconnection line 310 in the via portion occurs.

  It is an object of the present invention to provide a printed circuit board having a contact structure that can avoid an increase in contact resistance and prevent stress disconnection due to tensile stress, and a method for manufacturing the same.

In order to solve the above problems, according to the first aspect of the present invention, the printed circuit board electrically connects the first wiring layer, the second wiring layer, and the first wiring layer and the second wiring layer. A printed circuit board having contact wiring,
The contact wiring includes a first covering portion that covers a contact surface of the first wiring layer, a second covering portion that covers a contact surface of the second wiring layer, the first covering portion, and the second covering portion. Having a plug portion extending between
The first covering portion, the plug portion, and the second covering portion are contact wirings that are integrally formed of the same conductive material and have no interface inside.

In a second aspect of the present invention, a method for manufacturing a printed circuit board is provided. The manufacturing method of the printed circuit board is as follows:
Forming a first wiring layer on the substrate;
Forming a conductive first coating film covering the surface of the first wiring layer;
Forming an interlayer insulating layer covering the first wiring layer and the entire surface of the substrate;
Forming an opening in the interlayer insulating layer, exposing the first coating film in the opening;
In the opening, a conductive film of the same material as the first coating film is continuously grown from the first coating film to overflow a predetermined amount on the interlayer insulating layer,
Forming a second wiring layer electrically connected to the overflowed conductor film on the interlayer insulating layer;
Process.

  With the above configuration and method, it is possible to realize a contact structure that suppresses an increase in contact resistance and prevents disconnection due to thermal stress in the printed circuit board.

It is a figure for demonstrating the problem of the contact connection part formed by the conventional SAP method. It is a figure for demonstrating the problem of the contact connection part formed by the conventional photovia method or damascene method. It is a figure which shows the structure devised in the process leading to this invention. It is a schematic sectional drawing which shows the basic composition of the contact connection part applied to this invention. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by the SAP method; FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. FIG. 5 is a manufacturing process diagram for forming a printed circuit board having the contact structure of FIG. 4 by a damascene method. It is a cross-sectional block diagram of the printed circuit board of an Example. FIG. 8 is a schematic diagram of a daisy chain structure for verification of circuit wiring having the contact structure of FIG. 7. It is the graph which compared the defect incidence rate of the circuit wiring which has the contact structure of an Example, and the circuit wiring which has the conventional contact structure of FIG.

  FIG. 4 is a schematic cross-sectional view showing a basic configuration of a contact connecting portion applied to the wired circuit board of the present invention. The contact structure 1 includes a first wiring layer 5, a second wiring layer 7, and a contact wiring (via plug) 6 that electrically connects these wiring layers. The contact wiring 6 is formed of a metal material different from that of the first wiring layer 5 and the second wiring layer 7, and the cross-sectional shape thereof is I-shaped or “D”.

  The contact wiring 6 includes a first covering portion 6a that covers the contact surface (upper surface) of the first wiring layer 5, a second covering portion 6c that covers the contact surface (bottom surface) of the second wiring layer 7, and a first covering portion. 6a and a plug portion 6b extending between the second covering portions 6c, which are continuously formed integrally with the same conductor material. Here, the “contact surface” refers to a surface where the first wiring layer 5 and the contact wiring 6 are in contact and a surface where the contact wiring layer 6 and the second wiring layer 7 are in contact.

  The conductor material of the contact wiring 6 is a material that can be selectively grown (embedded) in the via portion and has a specific resistance smaller than 10 times that of Cu. From the viewpoint of suppressing an increase in contact resistance, it is preferable that the specific resistance is close to Cu. Examples of such a metal material include Au, Ag, Co, Ni, Co—W alloy, Ni—W alloy, Pt, Pd, and Al. When selective growth at the via portion is performed by electroless plating, Au, Ag, Co, Ni, Co—W alloy, Ni—W alloy, Pd, etc. are used, but CVD, PVD, MOCVD Al may be embedded by, for example. The atoms of these metal materials diffuse at the process temperature and do not leave an interface inside the contact wiring 6 having an I-shaped cross section. Generally, stress is applied starting from the interface and disconnection occurs, but the first covering portion 6a and the second covering portion 6c are flanges that continuously protrude from the plug portion 6b in a state where there is no interface. Demonstrates anchor effect against tensile stress. The first covering portion 6a and the second covering portion 6c also prevent the surface of the first wiring layer 5 and the second wiring layer 7 from being oxidized and prevent the wiring material from diffusing into the interlayer insulating layer (not shown). It also functions as a barrier layer.

  The interface configuration of the contact structure 1 is M1 / m2 / M2. Since there are only two interfaces of dissimilar metals, that is, the interface between the first wiring layer 5 and the first covering portion 6a and the interface between the second wiring layer 7 and the second covering portion 6c, it is possible to suppress an increase in contact resistance as a whole. Can do. Further, by increasing the contact area between the first covering portion 6a and the first wiring layer 5 and the contact area between the second covering portion 6c and the second wiring layer 7, the interface between different metals is increased. ing. Thereby, even when a tensile stress is applied, the stress can be dispersed and the voids can be prevented from concentrating on a narrow contact surface. As a result, disconnection at the contact connecting portion can be prevented.

<First Embodiment>
FIG. 5A to FIG. 5G are process flows when the printed circuit board having the contact structure of FIG. 4 is manufactured by the SPA method. First, as shown in FIG. 5A, a first wiring 14 is formed on a base insulating layer 12 on a substrate 11 via a laminated film 13 of an adhesion barrier layer and a plating seed layer. As the adhesion barrier layer, for example, Ti or a Ti compound is formed on the entire surface by sputtering. As a plating seed layer, a Cu seed film is formed on the entire surface of the Ti adhesion barrier layer by sputtering to form a laminated film 13. A resist film (not shown) is applied to the entire surface of the laminated film 13 and exposed and developed so as to have an opening corresponding to the shape of the first wiring. Thereby, a resist mask (not shown) having a predetermined opening pattern is formed. The Cu seed layer of the laminated film 13 is exposed in the opening of the resist mask. A metal wiring layer, for example, a Cu layer is grown in the opening by electroplating. After the Cu layer is grown to a predetermined height, the resist film is removed, and an excessive laminated film (Cu seed layer and Ti adhesion barrier layer) 13 on the base insulating layer 12 is removed by etching. It is desirable that the opening width of the resist mask and the plating growth film thickness are set in advance to allow for a decrease due to etching removal of the Cu seed layer. Thereby, the Cu wiring layer 14 as the first wiring layer is formed.

  Next, as shown in FIG. 5B, a coating film 15 that covers the entire exposed surface (side surface and upper surface) of the Cu wiring layer 14 is formed. In forming the coating film 15, first, the exposed surface of the Cu wiring layer 14 is acid-washed with an aqueous sulfuric acid solution or the like, and the surface of the Cu wiring layer 14 is activated. Subsequently, it is immersed in an aqueous solution containing an organic compound (such as an imidazole aqueous solution) to form a surface protective film (not shown), and then an alkaline cleaning solution having a predetermined pH value, for example, KHO having a pH of 8.0 to 10.0. The protective coating is removed by alkali washing with the solution. Thereafter, the surface of the Cu wiring layer 14 is activated by dipping in an active treatment solution containing, for example, Pd. By this series of activation treatments, the passivation of the surface of the Cu wiring layer 14 is destroyed. In this state, a Co-based or Ni-based coating film 15 is formed on the upper and side surfaces of the Cu wiring layer 14 by electroless plating. The coating film 15 is a CoWP film as an example, and the atomic concentration of Co in this case is, for example, 95 at% or more. The CoWP coating film 15 functions as a metal cap for preventing the Cu wiring layer 14 from being oxidized and diffused, and becomes a part of a contact wiring described later. A portion of the CoWP coating film 15 that covers the upper surface of the Cu wiring layer 14 is referred to as a first coating portion 15 for convenience.

  Next, as shown in FIG. 5C, an interlayer insulating layer 21 is formed on the entire surface, and the surface is planarized to form a via hole 22. A part of the CoWP coating film 15 that covers the Cu wiring layer 14 is exposed in the via hole 22. The interlayer insulating layer 21 is a photosensitive permanent resist such as phenol, and is used as it is as the interlayer insulating layer 21 without being peeled off.

  Next, as shown in FIG. 5D, CoWP is grown as it is in the via hole 22 by the electroless plating method and overflowed. Thereby, the plug part 16 and the 2nd coating | coated part 17 are formed. The plug portion 16 and the second covering portion 17 are continuously grown because the base is the same CoWP film 15, and there is no interface between them. The amount of overflow can be controlled by controlling the processing time of electroless plating. Specifically, the second coating portion 17 is formed in the upper layer so that it does not come into contact with the CoWP film (second coating film) overflowing from the adjacent via hole 22 and the thickness of the second coating portion 17 formed by overflow is formed in the upper layer. The thickness is controlled to be 2 to 15%, more preferably 5 to 10% of the thickness of the wiring layer. If the ratio of the film thickness that overflows is 2% or less, the concentration of voids and disconnection at the interface between different metals due to the tensile stress of the plug portion 16 cannot be sufficiently prevented. When the film thickness ratio is 15% or more, void concentration and disconnection can be sufficiently prevented, but the influence on the electrical characteristics of the second wiring is increased. In one embodiment, as will be described later, the thickness of the second covering portion 17 is controlled to be 10% of the thickness of the upper second wiring layer. The first covering portion 15, the plug portion 16, and the second covering portion 17 constitute a contact wiring 20. The contact wiring 20 is entirely made of CoWP, and has an I-shaped (or square-shaped) cross section without an interface inside.

  Next, as shown in FIG. 5E, an adhesion barrier layer and a plating seed layer are sequentially formed so as to cover the entire surface of the second coating film 17 and the interlayer insulating layer 21, thereby forming a laminated film 29. The adhesion / barrier layer is, for example, a sputtered film of Ti or Ti compound. The plating seed layer is, for example, a Cu seed layer. A resist film 31 is formed on the laminated film 29 and patterned by exposure and development processing so as to have an opening 32 corresponding to a predetermined wiring shape.

  Next, as shown in FIG. 5F, a Cu wiring layer 33 is grown in the opening 32 by electroplating. The Cu wiring layer 33 is a second wiring layer that is electrically connected to the lower first wiring layer 14 by the contact wiring 20.

  Next, as shown in FIG. 5F, the resist film 31 is removed, and the excess laminated film 29 remaining on the interlayer insulating layer 21 is removed, leaving only the second wiring layer 33. Similarly to the process of FIG. 5B, after the upper surface and side surface of the second wiring layer 33 are activated, a CoWP coating film 35 is formed on the upper surface and side surface of the second wiring layer 33 by electroless plating. Thereby, the circuit wiring including the contact wiring 20 having no I-shaped (D-shaped) interface in the cross-sectional shape is completed.

Second Embodiment
FIG. 6A to FIG. 6G are process flows when the printed circuit board having the contact structure of FIG. 4 is manufactured by the damascene method. First, as shown in FIG. 6A, an interlayer insulating layer 41 is formed on the entire surface of the base insulating layer 12 on the substrate 11, and a wiring groove 42 having a predetermined wiring shape is formed. The interlayer insulating layer 41 is, for example, a photosensitive permanent resist film, and the wiring groove 42 is formed by exposure and development. An adhesion barrier layer is sputtered by, for example, Ti or a Ti compound on the inner wall of the wiring groove 42 and the entire surface of the interlayer insulating layer 41, and then a plating seed layer is sputtered to form a laminated film 53.

  Next, as shown in FIG. 6B, the inside of the opening 42 is filled with a metal material such as Cu, and then the surface is polished and planarized until the interlayer insulating layer 41 is exposed. As a result, a buried wiring layer 54 of, for example, Cu is formed in the opening 42. Thereafter, a series of activation treatments such as acid washing, immersion in an organic aqueous solution, alkali washing, and immersion in an activation treatment solution are performed to activate the surface of the embedded wiring layer 54 such as Cu. Thereafter, a CoWP coating film 55 is formed on the Cu wiring layer 54 by electroless plating. The CoWP coating film 55 functions as a cap layer for preventing oxidation / diffusion of the Cu wiring layer 54 and becomes a part of a contact wiring described later as the first coating film 55.

  Next, as shown in FIG. 6C, an interlayer insulating layer 51 is formed on the entire surface, and a via hole 52 reaching the first coating film (CoWP coating film) 55 is formed. The interlayer insulating layer 51 is, for example, a phenol-based photosensitive permanent resist, and the via hole 52 is formed by exposure and development.

  Next, as shown in FIG. 6D, the CoWP film is grown as it is in the opening (via hole) 52 and overflowed by electroless plating. The Co ratio of CoWP is 95% or more. Also in this case, since the base is the CoWP film 55 as the first coating film, it can be continuously grown, and the plug portion 56 and the second coating portion 57 can be formed without an interface. The film thickness of the second covering portion 57 is 2 to 15%, preferably 5 to 10% of the film thickness of the second wiring layer formed in the process described later, and controls the processing time of electroless plating. And adjust the overflow amount. The first coating film 55, the plug portion 56, and the second coating film 57 form a contact wiring 60 having an I-shaped cross section without an interface inside.

  Next, as shown in FIG. 6E, for example, a photosensitive permanent resist film 61 is applied on the entire surface as an interlayer insulating layer to form a pattern having a wiring groove 62 having a predetermined shape. A laminated film 63 of an adhesion barrier layer of Ti or a Ti compound and a plating seed layer (for example, a Cu seed layer) is formed so as to cover the inner wall of the wiring groove 62 and the entire surface of the insulating layer 61.

  Next, as shown in FIG. 6F, for example, a Cu layer 64 is grown by electroplating.

  Finally, as shown in FIG. 6G, the Cu layer 64 is polished and planarized by CMP to a predetermined film thickness. Thereby, the second wiring layer 65 is formed. The second wiring layer 65 is electrically connected to the lower first wiring layer 54 by a contact wiring 60 having an I-shaped cross section and no interface.

  FIG. 7 is a cross-sectional configuration diagram of a printed circuit board 70 including a contact structure formed by the SAP method of FIGS. 5A to 5G. The printed circuit board 70 includes a lower first wiring layer 14 and an upper second wiring layer 33 with an interlayer insulating layer 21 interposed therebetween. The first wiring layer 14 is a Cu wiring layer having a film thickness of 2 μm and a wiring width of 2 μm. The second wiring layer is also a Cu wiring layer having a film thickness of 2 μm and a wiring width of 2 μm. The first wiring layer 14 is formed on the base insulating layer 12 on the substrate 11 via a Ti film 13 a having a film thickness of 20 nm as an adhesion barrier layer, and between the second wiring layer 33 and the interlayer insulating layer 21. Also, a Ti adhesion barrier layer having a thickness of 20 nm is inserted.

  The first wiring layer 14 and the second wiring layer 33 are electrically connected by a contact wiring 20 having an I-shaped cross section. The contact wiring 20 includes a first covering portion 15 covering the contact surface (upper surface) of the first wiring layer 14, a second covering portion 17 covering the contact surface (bottom surface) of the second wiring 33, and the first covering portion 15. The plug portion 16 extends between the second covering portions 17 and is integrally formed with the same material and without an interface.

  Specifically, the first covering portion 15 is a CoWP film having a thickness of 100 nm. The first covering portion 15 indicates the portion of the CoWP barrier layer 15 that covers the side surface and the upper surface of the first wiring layer (lower Cu wiring layer) 14 for the sake of convenience. The plug portion 16 and the second covering portion 17 are continuously grown from the first covering portion 15 with CoWP, which is the same material. The plug portion 16 has a diameter of 5 μm and a height of 3 μm. The film thickness of the 2nd coating | coated part 17 is 200 nm. In this example, the overflow amount (200 nm) of CoWP electroless plating is controlled to be 10% of the film thickness (2 μm) of the upper Cu wiring layer 33 as the second wiring layer, but it is 40 nm to 300 nm ( It can be appropriately set within a range of 2 to 15% of the film thickness of the second wiring layer 33. By setting the film thickness of the second covering portion 17 to this ratio, the stress disconnection between the contact wiring 20 and the second wiring layer 33 is effectively prevented and the influence on the electrical characteristics of the second wiring layer 33 is achieved. Can be suppressed.

  FIG. 8 is a schematic diagram of a verification daisy chain wiring produced based on the embodiment of FIG. The first wiring layer (lower wiring layer) 14 is electrically connected to the second wiring layer (upper wiring layer) 33 by the contact wiring (via plug) 20 in the land 25. In actual wiring, as shown in FIG. 7, the first covering portion 15 covering the upper surface of the first wiring layer 14, the second covering portion 17 covering the bottom surface of the second wiring layer 33, and the plug portion 16 are made of the same material ( CoWP) is integrally formed with no interface. The entire first wiring 14 is covered with the CoWP coating film 15, and the upper surface and side surfaces of the second wiring layer 33 are also covered with the CoWP film 35.

  On the other hand, although it was the same daisy chain wiring as a comparative example, a verification wiring having the contact structure of FIG. The daisy chain wiring of the comparative example also has a lower wiring (first wiring layer) and an upper wiring (second wiring layer) made of Cu wiring with a film thickness of 2 μm and a wiring width of 2 μm, and the diameter of a via plug as a contact wiring is 5 μm high However, the lower wiring and the via plug are formed of the same material (Cu), and a Ti adhesion barrier layer is inserted between the via plug and the upper Cu wiring, which is different from the wiring configuration of the embodiment.

  Fifty samples each having the daisy chain wiring of the example and the comparative example were prepared, and a reliability test for applying thermal stress was performed. In each sample, the number of via plugs included in one chain was 3000, and 1000 cycles were repeated at a thermal cycle of −55 ° C. to 135 ° C. Then, the resistance value of each sample was measured and the presence or absence of generation | occurrence | production of a disconnection defect was confirmed.

  FIG. 9 is a graph comparing disconnection failure rates by resistance value measurement after a reliability test. In the conventional configuration shown in FIG. 1B, the defect occurrence rate reaches nearly 30% after 1000 thermal cycles. On the other hand, in the verification wiring having the contact structure of the embodiment, the defect occurrence rate is only a few percent. From this, it was confirmed that the occurrence rate of disconnection failure can be greatly reduced by adopting the configuration and the manufacturing method of the embodiment.

  The present invention can be applied to both the SAP method and the damascene method, but if the damascene method is used, the wiring portion can be scaled down, so that it can also be applied to LSI fine wiring.

  In the above-described embodiment, a photosensitive permanent resist is used for the interlayer insulating layer and a via hole is formed by exposure and development. However, an inorganic insulating film such as a SiO2 or Low-k film is formed and a via hole is formed by dry etching. May be. The adhesion barrier layer and the plating seed layer can be formed by a film forming method such as a CVD method that can be appropriately performed by those skilled in the art. The excess plating seed layer and the adhesion barrier layer may be removed by wet etching or dry etching. Further, the adhesion barrier layer inserted between the upper wiring and the interlayer insulating layer may be formed of the same material as the contact wiring (plug portion and first and second covering portions). For the first wiring layer and the second wiring layer, an appropriate material such as Au or Ag can be used in addition to Cu. Alternatively, Al may be embedded in the damascene trench by a PVD method or the like to form a wiring layer. In the former case, a contact wiring having an I-shaped cross section can be formed from a material such as Co—W, Ni—W, or Pd by electroless plating. In the latter case, a contact wiring having an I-shaped cross section (or “D” shape) can be formed using a material such as Au, Ag, Co—W, Ni—W, or Pd.

  The present invention can be applied to a printed circuit board having via connection portions and wiring.

1 contact structure 6, 20, 60 contact wiring 5, 14, 54 first wiring layer 6 a, 15, 55 first coating film 6 b, 16, 56 plug part 6 c, 17, 57 second coating part 7, 33, 65 Second wiring layer 11 Semiconductor substrate 12 Underlying insulating layer 13, 29, 53, 63 Plating seed / adhesion barrier laminated film 21, 41, 51, 61 Interlayer insulating layer

Claims (3)

Forming a first wiring layer on the substrate;
Forming a conductive first coating film covering the surface of the first wiring layer;
Forming an interlayer insulating layer covering the first wiring layer and the entire surface of the substrate;
Forming an opening in the interlayer insulating layer, exposing the first coating film in the opening;
In the opening, a conductive film of the same material as the first coating film is continuously grown from the first coating film to overflow a predetermined amount on the interlayer insulating layer,
Forming a second wiring layer electrically connected to the overflowed conductor film on the interlayer insulating layer;
A method of manufacturing a printed circuit board, comprising: a step. The overflow amount is not in contact with a conductor film overflowing from an adjacent opening formed in the interlayer insulating layer, and the film thickness of the overflowing conductor film is 2 to 15% of the film thickness of the second wiring layer. the method of manufacturing the printed circuit board according to claim 1, characterized in that is controlled to be. The method for manufacturing a printed circuit board according to claim 2 , wherein the conductor film is grown from the first coating film by electroless plating.

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