JP5573038B2 - Multi-thread processor and program - Google Patents

Description

The present invention relates to a multithread processor and a program.

With the advancement of IT technology, the amount of data processed by computers is constantly increasing. Various types of processors have been proposed to process such a large amount of data at high speed.
For example, in a processor called VLIW (Very Long Instruction Word), a plurality of instruction words (for example, operation instruction, load instruction, etc.) are packed into one very long instruction (VLIW), and the plurality of instruction words are simultaneously transmitted. Run. In this case, when compiling the program, the order relation and data dependency relation between instructions are analyzed, and an instruction group that can be executed simultaneously is extracted.
This realizes performance improvement by simultaneous execution of multiple instructions without runtime overhead.

  On the other hand, in the case of an out-of-order execution type processor, analysis of instruction groups that can be executed simultaneously is executed by hardware at the runtime of the program. It also has a buffer that stores a number of instructions before execution, and executes them in order from the instruction with the operands necessary for execution. According to this method, an instruction group that can be executed simultaneously can be extracted and executed simultaneously without being restricted by the program order. However, the number of instructions that can be executed simultaneously in a single program (thread) is limited, and on average, the upper limit is 2 to 3 instructions / 1 cycle, which can further improve performance. It was difficult.

For this reason, in recent years, a multi-thread processor has been proposed that realizes further performance improvement by simultaneously executing a plurality of threads. In a multi-thread processor, a mechanism for reading and writing an arithmetic unit and a memory is shared by a plurality of threads. On the other hand, a register and a status register that are visible from software are separately prepared for each thread. , Multiple threads can be executed simultaneously.
As a thread switching method in a multithread processor, a fine grained multithreading method that switches multiple threads in units of clock cycles, and a simultaneous multithreading method that extracts and executes instructions that can be executed simultaneously from multiple threads (Simultaneous multithreading) and a coarse grained multithreading method that switches a thread to be executed only when a long stall such as a cache miss occurs has been proposed.

  As a known example in this field, for example, Patent Document 1 discloses an example of a multi-thread processor that employs a coarse-grain multithreading method. In the technology disclosed in Patent Document 1, the occurrence of an event such as a cache miss that causes a long stall is detected by hardware, and using this as a trigger, the thread to be executed is switched to execute different threads. continue. As a result, the processor can be prevented from stalling for a long time, and the processing performance per unit time can be improved. In addition, when an event for switching a thread such as a stall does not occur for a long time, a mechanism for switching to another thread when a predetermined fixed time has elapsed is also implemented.

JP 2006-40141 A

On the other hand, in the above background art, on the other hand, because of the necessity of realizing a higher-performance processor, the contents of individual instructions executed by the processor are also becoming more complicated, such as complex operations such as floating point arithmetic An order has appeared. Since these instructions have a long delay until an operation result is obtained, it is conceivable to arrange an instruction having no dependency in a delay cycle when there is a dependency between operands of the instruction. However, in the case of an instruction with a long delay, there is a case where it is difficult to secure an instruction having no dependency sufficient to fill the delay cycle.
For this reason, similar to the technique disclosed in Patent Document 1 described above, the dependency relationship between instructions is detected by hardware, and the thread to be executed is switched using this detection as a trigger, and the execution of different threads is continued. Implementation is conceivable (see FIG. 6).

FIG. 6 is a block diagram showing one configuration example of a conventional multi-thread processor.
The conventional multi-thread processor shown in FIG. 1 includes a program counter 91 (PC0 to PC3) that controls the instruction flow of a thread, a thread selection unit 92 that selects a thread to be executed, and an instruction fetch unit 93 that reads an instruction from the instruction memory. And an instruction execution unit 94 that executes instructions and a dependency detection unit 95 that detects operand dependency between instructions.
The processor shown in FIG. 6 is composed of a plurality of pipeline stages in order to improve the operating frequency like other processors in recent years.

FIG. 7 is an explanatory diagram showing an example of a program executed by a conventional multi-thread processor.
The program illustrated in the figure executes a floating-point instruction (fmul / fadd / fsub) with a long delay until an operation result is obtained. The fmul destination (r [1] and the source of fadd are executed. This is a case where a dependency relationship exists between the operands (r [1]).

FIG. 8 is an explanatory diagram showing an example of a thread switching method when a program is executed by a conventional multi-thread processor.
When the program shown in FIG. 7 is executed by the processor shown in FIG. 6, the thread to be executed is switched as shown in FIG.
In the processor shown in FIG. 6, the destination number of the instruction being executed in the instruction execution unit (fmul of thread 1 shown in FIG. 8) and the instruction fetched by the instruction fetch unit (fadd of thread 1 shown in FIG. 8) The dependency detection unit 95 (FIG. 6) compares the source operand numbers so that the dependency detection unit 95 detects the dependency between instructions.

  At the timing when the dependency is detected (third cycle shown in FIG. 8), an instruction that cannot be executed because the data dependency exists (fadd of thread 1 shown in FIG. 8) has been fetched. Therefore, in the third cycle shown in FIG. 8, even if the thread to be executed is switched from the thread 1 to the thread 2, the fmov of the thread 2 can be fetched from the instruction fetch unit 93 (FIG. 6). After the 4th cycle. Therefore, the multithread processor shown in FIG. 6 cannot execute a valid instruction for one cycle.

FIG. 9 is a block diagram showing a configuration example of a multi-thread processor obtained by improving the conventional multi-thread processor shown in FIG.
The multithread processor shown in the figure is a multithread processor that is an extension of the multithread processor shown in FIG. 6, and is in a state in which a valid instruction cannot be executed for one cycle due to the above-described thread switching. Provide an implementation to prevent the occurrence.
In the multithread processor shown in FIG. 9, an instruction buffer 96 and an instruction selection unit 97 for each thread are added to the multithread processor shown in FIG. 6, and a thread selection unit is used as a connection destination of the dependency detection unit 95. In addition to 91, an instruction selection unit 97 is added.

In the multi-thread processor shown in FIG. 9, after the instruction read from the instruction fetch unit 93 is temporarily stored in the instruction buffer 96, the instruction selection unit 97 selects the instruction stored in the buffer 96, and the instruction execution unit 94 to supply to 94. With this configuration, it is possible to continuously execute valid instructions when thread switching occurs.
However, each of the unit buffers corresponding to each thread in the instruction buffer 96 needs to be capable of buffering instructions for two cycles or more. At the time when the thread switching is determined, the instruction of the thread before switching is read from the instruction buffer 96. For this reason, when the instruction buffer 96 buffers only one cycle of instructions, an executable instruction cannot be read from the instruction buffer 96 in the cycle immediately after the thread is switched.

FIG. 10 is an explanatory diagram showing another example of a thread switching method when a program is executed by a conventional multi-thread processor.
The conventional multi-thread processor shown in FIG. 9 controls to always switch threads regardless of the presence or absence of data dependence in the case of an instruction having a long delay until an operation result is obtained. However, in such a configuration, programming using a delay cycle as shown in FIG. 10 cannot be performed. This is because if the control is performed so that the thread is always switched regardless of the presence or absence of data dependence, the instruction having no data dependence (the thread shown in FIG. 10) is included in the delay cycle of the instruction having a long delay (fmul of thread 1 shown in FIG. 10). This is because, even if it is possible to arrange 1 (fadd), thread switching is performed.
In addition, when there is no other thread that can be executed, a valid instruction cannot be continuously executed.

An object of the present invention, Ru near to provide a multi-threaded processor and programs that solve the problems described above surgery.

In order to solve the above problems, the Ru good to the first aspect of the present invention, comprises a plurality of pipeline stages, a multi-threaded processor to switch a plurality of threads at a predetermined fine-grained, per-thread A program counter that controls the instruction flow, a thread selection unit that selects one of the program counters, an instruction fetch unit that fetches an instruction based on the value of the program counter selected by the thread selection unit, and an instruction fetch unit and a command execution means for executing the instructions, the instructions, viewing including the thread switching flag for requesting the switching of the execution thread within the instruction word, the thread switching flag, predetermined value cycles to obtain the calculation result In an instruction that causes a delay of Is set to active instructing to request switching of the execution thread when the number of cycles is smaller than the predetermined number of cycles, and the instruction fetch means includes a thread switch flag included in the instruction word of the fetched instruction. If it is set to active, an instruction to switch the execution thread is transmitted to the thread selection means, and the thread selection means, based on the instruction, receives a program counter corresponding to the currently executing thread and Selects an address from another program counter and sends it to the instruction fetch means .

When Ru good to a second embodiment of the present invention, comprises a plurality of pipeline stages, a program to function as a multi-threaded processor to switch a plurality of threads at a predetermined fine grain, a multi-thread processor, each thread Counter for controlling the instruction flow of the program, thread selection means for selecting one of the program counters, instruction fetch means for fetching instructions based on the value of the program counter selected by the thread selection means, and instructions sent from the instruction fetch means The instruction includes a thread switching flag for requesting execution thread switching in the instruction word, and the thread switching flag has a delay of a predetermined value cycle to obtain the operation result. Present in the delay cycle in the resulting instruction When the number of instructions that do not use the operation result is smaller than the number of predetermined value cycles, the instruction fetch means is set to active instructing to request switching of the execution thread. When the thread switching flag included in the above is set to active, an instruction to switch the execution thread is transmitted to the thread selecting unit, and the thread selecting unit is currently executing based on the instruction. An address from a program counter different from the program counter corresponding to the thread is selected and functioned to be sent to the instruction fetch means .

  As described above, according to the multi-thread processor of the present invention, in a multi-thread processor that switches a plurality of threads in units of fine-grained clock cycles, based on the thread switching flag provided in the instruction word of the instruction to be executed. Thus, it is possible to switch the thread to be executed, thereby providing an effect of providing a multi-thread processor capable of increasing the instruction processing amount per unit time and improving the throughput performance.

It is a block diagram which shows the basic composition of the multithread processor which concerns on embodiment of this invention. It is an instruction block diagram which shows an example of the instruction format used with the multithread processor which concerns on this embodiment. It is explanatory drawing which shows an example of the thread switching method at the time of running a program with the multithread processor which concerns on embodiment of this invention. It is a flowchart explaining the procedure of the process which sets the thread switching flag (tcf) provided in the instruction word of the instruction | indication which the multithread processor which concerns on embodiment of this invention performs. It is a block diagram which shows the structure as one Example of the multithread processor which concerns on embodiment of this invention. It is a block diagram which shows one structural example of the conventional multithread processor. It is explanatory drawing which shows an example of the program run with the conventional multithread processor. It is explanatory drawing which shows an example of the thread switching method at the time of running a program with the conventional multithread processor. FIG. 7 is a configuration diagram showing a configuration example of a multithread processor obtained by improving the conventional multithread processor shown in FIG. 6. It is explanatory drawing which shows another example of the thread switching method at the time of running a program with the conventional multithread processor.

Hereinafter, embodiments of a multi-thread processor of the present invention will be described in detail with reference to the drawings.
However, the embodiments of the present invention are not limited to the following embodiments, and may take other various forms as long as they belong to the technical scope of the present invention.

FIG. 1 is a configuration diagram showing a basic configuration of a multi-thread processor according to an embodiment of the present invention.
The multi-thread processor according to the embodiment of the present invention shown in the figure is characterized in that the thread to be executed is switched based on a thread switching flag provided in the instruction word of the instruction to be executed.
The multi-thread processor of this embodiment shown in FIG. 1 has, as a basic configuration, a program counter 1 (PC0 to PC3) that controls the instruction flow of a thread, a thread selection unit 2 that selects a thread to be executed, and a thread selection unit 2 Is provided with an instruction fetch unit 3 that reads an instruction from an instruction memory (not shown) and an instruction execution unit 4 that executes the instruction read by the instruction fetch unit 3.

The multithread processor of the present embodiment shown in FIG. 1 shows a configuration in which four threads are switched. In general, however, the multithread processor according to the present invention is not necessarily limited to this embodiment, and can be switched. The number of threads that can be made is arbitrary.
In addition, the multi-thread processor of the present embodiment is composed of a plurality of pipeline stages in order to improve the operating frequency, as in recent processors.
Furthermore, in the multithread processor of the present embodiment shown in FIG. 1, a configuration including two pipeline stages of an instruction fetch stage and an instruction execution stage is shown, but in general, the multithread processor according to the present invention includes: It is not necessarily limited to such a configuration, and the number of pipeline stages constituting the processor is arbitrary.

FIG. 2 is an instruction configuration diagram illustrating an example of an instruction format used in the multithread processor according to the present embodiment.
As shown in the figure, the instruction format used in the multi-thread processor according to the present embodiment includes an opcode (Opcode) that specifies the type of instruction to be executed and a source operand (r1 / r2) that specifies data to be operated on. And a destination (r3) for designating a storage destination of the operation result, and a thread switching flag (tcf) for instructing switching of a thread to be executed.

  In the instruction format shown in FIG. 2, the instruction format includes two source operands and one destination. However, in general, the instruction format used in the multi-thread processor according to the present invention is not necessarily limited to this. For example, the number of source operands and the number of destinations may be zero or three. Further, the command format may include a field (for example, a simple value) different from the above.

Hereinafter, functions of the multi-thread processor according to the embodiment of the present invention will be described.
First, the instruction fetch unit 3 fetches an instruction in the instruction format shown in FIG. 2 from the instruction memory (not shown) according to the address specified by the thread selection unit 2. Thereafter, the instruction fetch unit 3 requests the thread selection unit 2 to switch the thread to be executed when the thread switching flag (tcf) provided in the instruction word of the fetched instruction is active (more specifically, , A thread switching request for an internal flag (not shown) is set to active).
The thread selection unit 2 detects that the internal flag thread switching request is active, selects an address from a program counter different from the program counter corresponding to the currently executing thread, and instructs the address to Send to fetch unit 3.

FIG. 3 is an explanatory diagram showing an example of a thread switching method when a program is executed by the multithread processor according to the embodiment of the present invention.
FIG. 3 shows how threads to be executed are switched when the above-described program shown in FIG. 7 is executed in the multi-thread processor shown in FIG.
In the case of the program example shown in FIG. 7, the thread switching flag provided in the instruction word of the fmul instruction is set to active. Further, Ia-b shown in FIG. 3 indicates the b-th instruction of the thread a.

  First, as shown in FIG. 3, when the fmul (I1-2) of the thread 1 is fetched in the second cycle, the thread switching flag provided in the instruction word of the fmul (I1-2) instruction is active. As a trigger, the thread selection unit in FIG. 1 switches the thread to be executed from thread 1 (PC1) to thread 2 (PC2). In the third cycle, the fmov (I2-1) instruction of thread 2 is fetched from the instruction fetch unit. Similarly, in the fourth cycle, switching from thread 2 (PC2) to thread 3 (PC3) is performed.

FIG. 4 is a flowchart illustrating a processing procedure for setting a thread switching flag (tcf) provided in an instruction word of an instruction executed by the multithread processor according to the embodiment of the present invention.
Hereinafter, the thread switching flag (tcf) provided in the instruction word of the instruction executed by the multithread processor according to the present embodiment will be described with reference to FIGS. A procedure of processing to be set will be described.

The setting of the thread switch flag (tcf) shown in the figure depends on the operand depending on the assembly language program generated by the programmer, the machine language program generated by the compiler, or the intermediate language description used by the compiler corresponding to the machine language program. The analysis can be performed by analyzing the relationship and the like, and the analysis can be performed by executing a dedicated program that is a computer program according to the embodiment of the present invention.
The dedicated program can be included in the compiler itself, and can also be included in other basic software executed after execution of the compiler. Here, the dedicated program will be described as being included in basic software such as the compiler.

The program created by executing the dedicated program according to the above-described embodiment of the present invention is also a computer program according to the embodiment of the present invention.
(Step S1)
First, for each instruction in the input assemble program, machine language program, or intermediate language description, it is checked whether or not a delay of N (> 0) cycles is generated to obtain the operation result of each instruction. . For this reason, in step S1, basic software such as a compiler that outputs an instruction sequence assigns 1 to the temporary variable S, and then checks the (first value of the temporary variable S) -th instruction in order from the first instruction. Get ready.

(Step S2)
Next, in step S2, the basic software such as the compiler verifies whether or not the (temporary variable S value) instruction has a delay of N (> 0) cycles to obtain the operation result. If N (> 0) cycles are not delayed in obtaining the calculation result, the process proceeds to step S10 in order to set the new value of the temporary variable S to (the value of the temporary variable S) +1. On the other hand, if a delay of N (> 0) cycles occurs to obtain the calculation result, the process proceeds to step S3.
(Step S3)
In step S3, basic software such as the compiler assigns 1 to the temporary variable T and 0 to the temporary variable C, and verifies the operand dependency between the instructions following (the value of the temporary variable S). Make preparations.

(Step S4)
Next, in step S4, the basic software such as the compiler verifies whether or not each of the (S + 1) th to (S + N) th instructions uses the operation result of the Sth instruction, and the (S + 1) th If the (S + N) th instruction from to does not use the operation result of the Sth instruction, the process proceeds to step S5. On the other hand, if each of the (S + 1) th to (S + N) th instructions uses the operation result of the Sth instruction, the process proceeds to step S6.
(Step S5)
In step S5, the basic software such as the compiler adds 1 to the value of the temporary variable C and proceeds to step S6.

(Step S6)
In step S6, the basic software such as the compiler adds 1 to the value of the temporary variable T, and proceeds to step S7.
(Step S7)
In step S7, it is verified whether basic software such as the compiler satisfies T> N. If T> N, the process proceeds to step S8. On the other hand, if T> N is not true, the process returns to step S4.
(Step S8)
In step S8, the basic software such as the compiler verifies whether or not C <(N / 2). If C <(N / 2), the process proceeds to step S9. On the other hand, if not C <(N / 2), the process proceeds to step S10.

(Step S9)
In step S9, basic software such as the compiler sets the thread switching flag (tcf) of the Sth instruction to active, and the process proceeds to step S10.
(Step S10)
In step S10, the basic software such as the compiler adds 1 to the value of the temporary variable S, and proceeds to step S11.
(Step S11)
In step S11, the basic software such as the compiler verifies whether or not S ≧ the number of instructions in the program. If S ≧ the number of instructions in the program, the process returns to step S2. On the other hand, if S ≧ the number of instructions in the program, the process is immediately terminated.

In this procedure, the number of instructions that do not use the operation result of the Sth instruction is counted. That is, in order from the (S + 1) th instruction, the (S + T) th instruction is checked, and if the (S + T) th instruction does not use the operation result of the Sth instruction, the temporary variable C is counted up. .
This check is sequentially performed for each (S + N) th instruction, and the thread switching flag (tcf) of the Sth instruction is set based on the number of instructions (C) that do not use the operation result of the Sth instruction. Is what you do. If the number of unused instructions (C) is smaller than half of the number of cycles (N) until an operation result is obtained, the thread switching flag (tcf) of the Sth instruction is set to active. The above processing is performed for all instructions in the program.
In this way, the thread switching flag (tcf) for each instruction can be set.

  In the processing procedure shown in FIG. 4, the number (C) of instructions that do not use the operation result for setting the thread switching flag (tcf) is less than half the number of cycles (N) until the operation result is obtained. In general, the present invention is not necessarily limited to this condition. For example, the thread switching flag (C is smaller than N, C is smaller than 1/4 of N, or the like). It may be a condition for setting tcf).

FIG. 5 is a configuration diagram showing a configuration as one example of the multi-thread processor according to the embodiment of the present invention.
The multi-thread processor shown in the figure is a multi-thread processor that switches a thread to be executed based on a thread switching flag provided in an instruction word of an instruction to be executed.
As shown in FIG. 5, the multi-thread processor as an example of the multi-thread processor according to the embodiment of the present invention includes a program counter 1 (PC0 to PC3) for controlling the instruction flow of the thread, and a thread for each thread. A thread counter 10 (TC0 to TC3) that counts the number of cycles that are not executed, a thread selection unit 2 that selects a thread to execute, and an instruction is read from the instruction memory based on the program counter value of the thread selected by the thread selection unit Instruction fetch unit 3, instruction execution unit 4 that executes an instruction sent by NOP replacement unit 12 to be described later, NOP 11 that sends a NOP (None Operation) command, and an instruction fetched based on an instruction from thread selection unit 2 And a NOP replacement unit 12 that replaces with a NOP instruction.

The multi-thread processor shown in FIG. 5 shows a multi-thread processor that switches four threads, but in general, the multi-thread processor according to the present invention is not necessarily limited to this embodiment. Further, the number of threads to be switched is arbitrary. Further, the multi-thread processor shown in FIG. 5 is assumed to be composed of a plurality of pipeline stages in order to improve the operating frequency, like other multi-thread processors in recent years.
Furthermore, although the multithread processor shown in FIG. 5 shows two stages, an instruction fetch stage and an instruction execution stage, in general, the multithread processor according to the present invention is not necessarily limited to this embodiment. is not. The number of pipeline stages constituting the processor is arbitrary.

In the following, the function of the multithread processor shown in FIG. 5 will be described with particular attention to differences from the function of the multithread processor shown in FIG.
As in the multithread processor shown in FIG. 1, the multithread processor shown in FIG. 5 executes an instruction having the instruction format shown in FIG. 2, and executes a thread switching flag (tcf provided in the instruction word of the fetched instruction. ) Is active, the thread selection unit 2 switches the thread to be executed. At that time, the thread selection unit 2 determines the next thread to be selected based on the count value of the thread counter 10 corresponding to each thread. Specifically, the thread whose count value of the thread counter 10 is 0 is selected as the thread to be executed next.

Each thread counter (TC0 to TC3) of the thread counter 10 stores 0 as an initial value. When a thread is switched, a predetermined value is stored in the thread counter corresponding to the thread that was originally executed. Is done. The thread counter in which a value other than 0 is stored is decremented until it reaches 0 for each cycle in which the corresponding thread is not selected.
When a thread is switched, a predetermined value stored in the thread counter 10 is determined based on an opcode of an instruction fetched last in the thread that was originally executed. For example, when an instruction corresponding to a certain opcode has a delay of N (> 0) cycles to obtain an operation result, a value of (N−1) is stored in the thread counter as a predetermined value. For this reason, the predetermined value stored in the thread counter 10 is selected by a selector (not shown) controlled based on the operation code, and the selected value is supplied to the thread counter.

By using such a thread counter 10, it is possible to prevent the thread A from being selected again after switching from the thread A to the thread B and before the data dependency in the thread A is resolved.
On the other hand, the NOP replacement unit 12 replaces the instruction read by the instruction fetch unit 3 with a NOP (None OPeration) instruction based on the control from the thread selection unit 2. Specifically, when the thread selection unit 2 detects that there are no other executable threads when switching threads, the thread selection unit 2 sends a replacement to the NOP instruction to the NOP replacement unit 12. (More specifically, an internal flag indicating a NOP replacement request is set to active). The thread selection unit 2 determines that there is no other executable thread when there is no other thread waiting for execution whose count value of the thread counter 10 is 0 other than the thread being executed.

  In the multi-thread processor as one embodiment, 0 is set as the initial value of the thread counter 10 and the predetermined value set based on the operation code is decremented. In general, the multi-thread processor according to the present invention is However, the present invention is not necessarily limited to this embodiment, and the initial value may be a value other than zero. Further, the thread counter 10 may be incremented.

  The present invention can be applied to the construction of a multi-thread processor in which a plurality of threads can be switched in units of fine-grained clock cycles. In particular, it is suitable for the construction of a multi-thread processor that can realize the thread switching function based on the operand dependency relationship between instructions reliably (that is, at an arbitrarily deep optimization level) and can be realized even with low-cost hardware. It is.

DESCRIPTION OF SYMBOLS 1 Program counter 2 Thread selection part 3 Instruction fetch part 4 Instruction execution part 10 Thread counter 12 NOP replacement part

Claims (6)

A multi-thread processor having a plurality of pipeline stages and capable of switching a plurality of threads to a predetermined fine granularity;
A program counter that controls the instruction flow for each thread;
Thread selection means for selecting one of the program counters;
Instruction fetch means for fetching an instruction based on a value of a program counter selected by the thread selection means;
An instruction execution means for executing the instruction sent from the instruction fetch means;
The instruction includes a thread switching flag for requesting execution thread switching inside the instruction word,
In the thread switching flag, in an instruction that causes a delay of a predetermined value cycle to obtain an operation result, the number of instructions that do not use the operation result that exist in the delay cycle is smaller than the number of the predetermined value cycle. If set to active, indicating that the execution thread should be requested to switch
The instruction fetch means, when the thread switching flag included in the instruction word of the fetched instruction is set to active, transmits an instruction to switch the execution thread to the thread selection means,
The thread selection means selects an address from a program counter different from the program counter corresponding to the currently executing thread based on the instruction, and sends the address to the instruction fetch means. Processor. For each thread, a thread counter that counts the number of cycles in which the thread is not executed,
And NOP replacement means for replacing the instruction fetched by the instruction fetch means with a NOP instruction,
The thread selection means selects a thread waiting for execution whose counter value of the thread counter is 0 as a thread to be executed next when switching a thread to be executed, and is waiting for execution whose counter value of the thread counter is 0 2. The multithread processor according to claim 1, wherein when there is no thread, the NOP replacement unit is requested to replace it with a NOP instruction. The thread counter stores 0 as an initial value, and when a thread is switched, the thread counter corresponding to the thread that was being executed is determined based on the opcode of the last fetched instruction in the thread that was being executed. And decrementing the predetermined value until it becomes 0 for each cycle in which the corresponding thread is not selected,
The multi-value according to claim 2, wherein the predetermined value determined based on the opcode of the last fetched instruction is a value based on the number of delay cycles necessary to obtain an operation result of the instruction. Thread processor. A program having a plurality of pipeline stages and functioning as a multi-thread processor capable of switching a plurality of threads to a predetermined fine granularity,
The multi-thread processor;
A program counter that controls the instruction flow for each thread,
Thread selection means for selecting one of the program counters;
Instruction fetch means for fetching an instruction based on a value of a program counter selected by the thread selection means;
Function as instruction execution means for executing the instruction sent from the instruction fetch means;
The instruction includes a thread switching flag for requesting execution thread switching inside the instruction word,
In the thread switching flag, in an instruction that causes a delay of a predetermined value cycle to obtain an operation result, the number of instructions that do not use the operation result that exist in the delay cycle is smaller than the number of the predetermined value cycle. If set to active, indicating that the execution thread should be requested to switch
The instruction fetch means, when the thread switching flag included in the instruction word of the fetched instruction is set to active, transmits an instruction to switch the execution thread to the thread selection means,
The thread selection means functions to select an address from a program counter different from the program counter corresponding to the currently executing thread based on the instruction and send the address to the instruction fetch means. Program. The multi-thread processor;
For each thread, a thread counter that counts the number of cycles in which the thread is not executed,
Further function as NOP replacement means for replacing the instruction fetched by the instruction fetch means with a NOP instruction,
The thread selection means selects a thread waiting for execution whose counter value of the thread counter is 0 as a thread to be executed next when switching a thread to be executed, and is waiting for execution whose counter value of the thread counter is 0 5. The program according to claim 4, wherein when there is no thread, the program is made to function so as to request the NOP replacement means to replace it with a NOP instruction. The thread counter stores 0 as an initial value, and when a thread is switched, the thread counter corresponding to the thread that was being executed is determined based on the opcode of the last fetched instruction in the thread that was being executed. And decrementing the predetermined value until it becomes 0 for each cycle in which the corresponding thread is not selected,
The predetermined value determined based on the opcode of the last fetched instruction is made to function so as to be a value based on the number of delay cycles necessary for obtaining the operation result of the instruction. The program described in.

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