JP5580138B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor having a channel layer made of InAs.

  There is a need for field effect transistors (FETs) that can operate at higher speeds for faster computations and higher frequency oscillations. High-speed field effect transistors require high electron mobility and high electron saturation speed. For example, a field effect transistor having a basic structure of a GaAs / AlGaAs heterostructure in which an electron channel layer is made of GaAs and an InGaAs / InAlAs / InP heterostructure in which an electron channel layer is made of InGaAs, and an operation of 500 GHz or more is realized. ing.

  Under such circumstances, InAs is a material having higher electron saturation density and higher mobility than the above-described GaAs and InGaAs, and a heterostructure field effect transistor having a channel layer made of InAs is capable of operating at higher speed. Expected to be possible. As shown in FIG. 9, the field effect transistor includes a first barrier layer 902 made of AlGaSb formed on a substrate 901, a channel layer 903 made of InAs formed on the first barrier layer 902, And a second barrier layer 904 made of AlGaSb formed on the channel layer 903. The field effect transistor is formed on the cap layer 905 made of GaSb formed on the second barrier layer 904, the oxide layer 906 formed on the cap layer 905, and the oxide layer 906. And a source electrode 908 and a drain electrode 909 which are arranged with the gate electrode 907 interposed therebetween and are ohmically connected to the channel layer 903.

  In general, in a heterostructure field effect transistor using InAs for a channel layer, a quantum layer in which a channel layer 903 made of InAs is sandwiched between a first barrier layer 902 and a second barrier layer 904 made of AlSb or AlGaSb having a lattice constant close to InAs. A well structure is used. In the production of these structures, each layer made of a compound semiconductor is deposited by molecular beam epitaxy (MBE) or metal organic vapor phase epitaxy (MOVPE).

If the channel layer 903 made of InAs is thick to some extent (about 10 nm or more), the energy level of electrons in InAs becomes lower than the deep acceptor energy level in AlSb (or AlGaSb) constituting each barrier layer. Electrons of about × 10 ¹² cm ⁻² accumulate in the channel layer 903 (see Non-Patent Documents 1, 2, and 3).

  By the way, AlSb (or AlGaSb) constituting the barrier layer is easily oxidized because it contains Al and has deliquescence in the atmosphere. For this reason, in the fabrication of a quantum well structure in which the channel layer is made of InAs, generally, a cap layer 905 made of GaSb having a lattice constant close to that of the second barrier layer 904 is formed and used as a lower layer. Oxidation and deliquescence of the Al-containing layer is prevented.

  In order to form a field effect transistor using the above-described quantum well structure, an insulating layer is required between the channel layer 903 and the gate electrode 907. For example, in a field effect transistor using silicon, an insulating layer made of silicon oxide is used as a gate insulating layer. In a field effect transistor having a GaAs / AlGaAs heterostructure, an AlGaAs layer used as a barrier layer is a gate insulating layer.

  On the other hand, in the case of a field effect transistor using InAs for the channel layer, the insulation properties of the second barrier layer 904 made of AlSb or AlGaSb and the cap layer 905 made of GaSb are low. Therefore, when the gate electrode 907 is formed directly on the cap layer 905 without using the oxide layer 906, a leakage current flows between the gate and the channel, so that an electric field cannot be applied, and the transistor functions as a field effect transistor. do not do. Therefore, for example, an oxide layer 906 such as aluminum oxide is formed on the cap layer 905, and the gate electrode 907 is disposed thereon. Note that the oxide layer 906 can be formed by, for example, plasma induced chemical vapor deposition (PECVD) (see Non-Patent Document 4), atomic layer deposition (ALD) (see Non-Patent Document 5), or the like.

D.J.Chadi, "Electron accumulation at undoped AlSb-InAs quantum wells; Theory", Physical Review B, vol.47, no.20, pp.13478-13484, 1993. J. Shen et al., "Remote n-type modulation doping of InAs quantum wells by" deep acceptors "in AlSb", Journal of Applied Physics, vol.73, no.12, pp.8313-8318, 1993. M.Ideshita et al., "Electron accumulation in AIGaSb / lnAs / AIGaSb quantum well system", Applied Physics Letters, vol.60, no.20, pp.2549-2511, 1992. C. Nguyen et al., "Magneto-transport in InAs / AlSb quantum wells with large electron concentration modulation", Surface Science, vol.267, pp.549-552, 1992. Ian J. Gelfand et al., "Surface-gated quantum Hall effect in an InAs heterostructure", Applied Physics Letters, vol.88, 252105, 2006.

By the way, in the field effect transistor having a heterostructure as described above, the second barrier layer is formed so that the Fermi level formed on the surface of the cap layer 905 made of GaSb matches the Fermi level in the channel layer 903. The potential of 904 (first barrier layer 902) bends spatially. Therefore, as shown in FIGS. 10 and 11, a deep acceptor level E _A of the second barrier layer 904 (the first barrier layer 902) is so traversing the Fermi level E _F. In FIG. 10 and FIG. 11, black circles indicate acceptors that accommodate electrons, and white circles indicate acceptors that do not accommodate electrons.

  As a result, the following problem occurs.

(Problem 1)
As shown in FIG. 10, when a positive bias voltage is applied to the gate electrode 907, positive charge is accumulated in the gate electrode 907 and the electron concentration of the channel layer 903, which is negative charge, increases due to the principle of the capacitor. Thus, the electron concentration in the channel layer 903 changes by changing the voltage between the gate and the channel. Ideally Q = CV + Q _0. Note that Q is the amount of charge in the channel layer 903, and assuming that the electron concentration n and the elementary charge amount e are Q / e = n. Q ₀ is the amount of charge in the channel layer 903 when the voltage is 0, V is the gate voltage, and C is the combined capacitance in the gate insulating layer.

  However, when a positive bias voltage is applied to the gate electrode 907, the acceptor region 1001 containing the electrons of the second barrier layer 904 (first barrier layer 902) spreads toward the channel layer 903, and the gate electrode 907 This cancels the electric field and suppresses the increase in electron concentration.

  As shown in FIG. 11, when a negative bias voltage is applied to the gate electrode 907, the electron concentration in the channel layer 903 tends to decrease. However, at this time, the acceptor region 1001 that accommodates electrons in the second barrier layer 904 (first barrier layer 902) is moved away from the channel layer 903 side, and the electrons accommodated in the acceptor region 1001 are emitted, so that the channel Reduction of the electron concentration in the layer 903 is suppressed. As a result, the capacitance is apparently reduced, and the change rate of the electron concentration with respect to the voltage of the gate electrode 907 is reduced.

(Problem 2)
Since the response speed of emission and incorporation of electrons accompanying the change of the acceptor region 1001 containing electrons described above is as slow as several minutes, the response speed of the change in electron concentration with respect to the gate voltage is remarkably reduced.

(Problem 3)
Even when the gate voltage is the same, the region of the acceptor that accommodates electrons in the final stable state differs in the gate sweep direction, so the relationship between the gate voltage and the electron concentration is bistable. It is not decided one-on-one. As shown in FIG. 12A, the change in the electron concentration n with respect to the change in the gate voltage V is bistable with hysteresis. For this reason, even with the same gate voltage, there are two states, the state shown in FIG. 12B and the state shown in FIG. Thus, the electron concentration is not uniquely determined for the same gate voltage.

  As described above, the field effect transistor having a hetero structure in which the channel layer is made of InAs has a problem that it cannot operate stably at high speed.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to be a heterostructure field effect transistor having a channel layer made of InAs and capable of stable operation at high speed. To do.

A field effect transistor according to the present invention includes a first barrier layer made of a compound semiconductor selected from AlGaSb and AlSb formed on a substrate, and a channel layer made of InAs formed on the first barrier layer. A second barrier layer made of AlGaSb and a compound semiconductor selected from AlSb formed on the channel layer; a cap layer made of GaSb formed on the second barrier layer; and An oxide layer formed on the oxide layer; a gate electrode formed on the oxide layer; a source electrode and a drain electrode that are disposed across the gate electrode and are in ohmic contact with the channel layer; and a first barrier layer is an impurity which becomes shallow acceptor relative to the compound semiconductor and is introduced is formed, a compound semiconductor with electrons are accommodated in a shallow acceptor A first impurity introduction region to have acceptor not electrons are housed, impurities serving as a shallow acceptor relative to the compound semiconductor is formed on the second barrier layer is introduced, deep compound semiconductor with electrons in a shallow acceptor is housed The acceptor includes a second impurity introduction region in which electrons are not accommodated , and the first impurity introduction region and the second impurity introduction region are formed apart from the channel layer in a range that does not cause impurity scattering in the electrons of the channel layer. Yes.

  In the field effect transistor, the first impurity introduction region and the second impurity introduction region may be formed 5 nm apart from the channel layer. The impurity may be selected from zinc, magnesium, carbon, and beryllium.

  As described above, according to the present invention, the first barrier layer and the second barrier layer are provided with the first impurity introduction region and the second impurity introduction region into which the impurity that becomes a shallow acceptor with respect to the compound semiconductor is introduced. As a result, the field effect transistor having a hetero structure in which the channel layer is made of InAs has an excellent effect of being able to operate stably at high speed.

FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. FIG. 2 is a band diagram showing a band structure in the field effect transistor according to Embodiment 1 of the present invention. FIG. 3 is a characteristic diagram showing a change in the electron concentration n of the channel layer 103 with respect to a change in the gate voltage V of the field effect transistor in the first embodiment. FIG. 4 is a cross-sectional view showing the configuration of the field effect transistor according to Embodiment 2 of the present invention. FIG. 5 is a characteristic diagram showing measurement results of the first comparison element. FIG. 6 is a characteristic diagram showing measurement results of the first comparison element. FIG. 7 is a characteristic diagram showing measurement results of the second comparison element. FIG. 8 is a characteristic diagram showing a measurement result of the field effect transistor in the second embodiment. FIG. 9 is a cross-sectional view showing the configuration of a field effect transistor using InAs for the channel layer. FIG. 10 is a band diagram showing a band structure in a field effect transistor using InAs for the channel layer. FIG. 11 is a band diagram showing a band structure in a field effect transistor using InAs for the channel layer. FIG. 12 is an explanatory diagram for explaining the relationship between the gate voltage and the electron concentration in a field effect transistor using InAs for the channel layer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to Embodiment 1 of the present invention. This field effect transistor is formed on the first barrier layer 102 made of AlGaSb formed on the substrate 101, the channel layer 103 made of InAs formed on the first barrier layer 102, and the channel layer 103. And a second barrier layer 104 made of AlGaSb.

  The field effect transistor is formed on the cap layer 105 made of GaSb formed on the second barrier layer 104, the oxide layer 106 formed on the cap layer 105, and the oxide layer 106. A gate electrode 107, and a source electrode 108 and a drain electrode 109 which are arranged with the gate electrode 107 interposed therebetween and are ohmically connected to the channel layer 103.

  In addition, the field-effect transistor is formed in the first barrier layer 102, the first impurity introduction region 110 into which an impurity that becomes a shallow acceptor with respect to AlGaSb is introduced, and the second barrier layer 104 formed in the AlGaSb. And a second impurity introduction region 111 into which an impurity that becomes a shallow acceptor is introduced. Further, the first impurity introduction region 110 and the second impurity introduction region 111 are formed away from the channel layer 103 in a range in which no impurity scattering occurs in the electrons of the channel layer 103.

According to the field effect transistor of the present embodiment, since the first impurity introduction region 110 and the second impurity introduction region 111 are formed, as shown in the band diagram of FIG. An electron shown by a black circle is accommodated in a certain shallow acceptor, and a deep acceptor is in a state where no electron is accommodated. Even when a gate voltage is applied, this state is preserved, and emission of electrons from the acceptors existing in the second barrier layer 104 and the first barrier layer 102 and electron uptake are suppressed, and a decrease in capacitance is suppressed. .

Further, when the operation is performed by applying a gate voltage, the emission of electrons from the acceptors existing in the second barrier layer 104 and the first barrier layer 102 and the incorporation of electrons are suppressed, so that high-speed operation is not hindered. Further, since the electron concentration is determined one-to-one with respect to the gate voltage, the electron concentration n of the channel layer 103 changes in a linear function with respect to the change of the gate voltage V as shown in FIG. Depending on the form, high-speed and stable operation can be performed.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. FIG. 4 is a cross-sectional view showing the configuration of the field effect transistor according to Embodiment 2 of the present invention. This field effect transistor includes a first barrier layer 402 having a layer thickness of 50 nm made of Al _0.7 Ga _0.3 Sb formed on a substrate 401 made of InAs or GaAs, and InAs formed on the first barrier layer 402. A channel layer 403 having a layer thickness of 15 nm and a second barrier layer 404 having a layer thickness of 30 nm made of Al _0.7 Ga _0.3 Sb formed on the channel layer 403. The main surface of the substrate 401 is the (001) plane.

The field effect transistor also includes a 5 nm thick cap layer 405 made of GaSb formed on the second barrier layer 404 and aluminum oxide (Al ₂ O ₃ ) formed on the cap layer 405. An oxide layer 406 having a layer thickness of 20 nm, a gate electrode 407 made of Ti / Au formed on the oxide layer 406, a source electrode 408 disposed across the gate electrode 407 and ohmically connected to the channel layer 403, and A drain electrode 409. The source electrode 408 and the drain electrode 409 are made of AuGeNi alloy. The source electrode 408 and the drain electrode 409 are formed on the cap layer 405, and are electrically connected to the channel layer 403 by forming an alloy layer.

  In addition, this field effect transistor includes a first impurity introduction region 410 formed by so-called delta doping of beryllium (Be) as an impurity which is formed in the first barrier layer 402 and becomes a shallow acceptor with respect to AlGaSb. Similarly, a second impurity introduction region 411 in which beryllium (Be) is introduced by so-called delta doping as an impurity which is formed in the second barrier layer 404 and becomes a shallow acceptor with respect to AlGaSb is provided. In addition, the first impurity introduction region 410 and the second impurity introduction region 411 are formed away from the channel layer 403 within a range where no impurity scattering occurs in the electrons of the channel layer 403.

  Further, on the substrate 401, a superlattice layer 421 in which AlSb and GaSb layers are alternately stacked for 10 cycles, a 500 nm-thick semiconductor layer 422 made of AlGaSb, and AlSb and GaSb layers are alternately stacked in 10 cycles. Superlattice layer 423 is formed as a buffer layer, and first barrier layer 402 is formed thereon. In each superlattice layer, the AlSb layer has a thickness of 2.5 nm, and the GaSb layer has a thickness of 2.5 nm.

  Each of these layers may be formed by epitaxial growth using a molecular beam epitaxy method. The oxide layer 406 may be formed by an atomic layer growth method in which an aluminum material such as trimethylaluminum or triethylaluminum and an oxidant gas are alternately supplied to form an aluminum oxide layer one atomic layer at a time. Further, an aluminum oxide layer formed by an atomic layer growth method is patterned by a known lithography technique and etching technique to form an opening, and a source electrode 408 and a drain are formed on the cap layer 405 exposed in the opening. The electrode 409 may be formed. Note that the oxide layer 406 may be formed after the source electrode 408 and the drain electrode 409 are formed first. In this case, when the wiring is connected to the source electrode 408 and the drain electrode 409, the oxide layer 406 at the connection portion may be removed.

Here, the first impurity introduction region 410 is momentarily grown when the thickness of the first barrier layer 402 is about 45 nm in the process of epitaxially growing Al _0.7 Ga _0.3 Sb by molecular beam epitaxy to form the first barrier layer 402. It is formed by irradiating a Be beam under a dose amount condition of 2 × 10 ¹¹ cm ⁻² . After this momentary Be beam irradiation, the Be beam shutter and valve are closed to stop the irradiation, and then epitaxial growth of Al _0.7 Ga _0.3 Sb is continued for a layer thickness of 5 nm. Accordingly, the formed first impurity introduction region 410 is formed to be separated from the channel layer 403 by about 5 nm.

Similarly, the second impurity introduction region 411 is instantaneously formed when the second barrier layer 404 is formed by epitaxially growing Al _0.7 Ga _0.3 Sb by molecular beam epitaxy and when the second barrier layer 404 is grown to a thickness of about 5 nm. It is formed by irradiating a Be beam under a dose amount condition of 2 × 10 ¹¹ cm ⁻² . After this momentary Be beam irradiation, the Be beam shutter and valve are closed to stop the irradiation, and then epitaxial growth of Al _0.7 Ga _0.3 Sb is continued to a layer thickness of 25 nm. Therefore, the formed second impurity introduction region 411 is also formed away from the channel layer 403 by about 5 nm.

The Al _0.7 Ga _0.3 Sb layer having a thickness of about 5 nm between the first impurity introduction region 410 and the second impurity introduction region 411 and the channel layer 403 functions as a spacer layer, around Be as an introduced impurity. Random potential fluctuations that are formed are averaged, and the impurity scattering of electrons in the channel layer 403 is suppressed to improve mobility.

  Also in the field effect transistor in this embodiment, since the first impurity introduction region 410 and the second impurity introduction region 411 are formed, the first barrier layer 402 has a deeper acceptor on the substrate side than the first impurity introduction region 410. Electrons are always accommodated, and an acceptor deeper than the second impurity introduction region 411 of the second barrier layer 404 is always in a state of accommodating electrons. In the first impurity introduction region 410 and the second impurity introduction region 411, electrons are accommodated in the introduced shallow acceptor impurity, and the deep acceptor does not accommodate electrons. Further, in the channel side 403 from the first impurity introduction region 410 of the first barrier layer 402 and the channel side 403 from the second impurity introduction region 411 of the second barrier layer 404, the deep acceptor does not contain electrons. Become. The electrons accommodated in these acceptors are suppressed from being changed by application (change) of the gate voltage and are fixed.

  As a result, first, during the operation by applying the gate voltage, the emission and incorporation of electrons accompanying the change in the acceptor region that accommodates the electrons with a slow response speed are suppressed, and the high-speed operation is not hindered. In addition, since the first barrier layer 402 and the second barrier layer 404 do not emit and capture electrons even when the gate voltage sweep direction is changed, a decrease in capacitance is suppressed, and for the same gate voltage, The electron concentration is uniquely determined. Thus, according to the present embodiment, a stable operation can be performed at high speed.

  Hereinafter, experimental results of the actually fabricated elements will be described. First, the measurement is performed on the first comparison element and the second comparison element in addition to the field effect transistor in the second embodiment described above. In this experiment, the change in the electron concentration in the channel layer with respect to the sweep rate of the gate voltage is measured.

The first comparison element includes an Al _0.7 Ga _0.3 Sb layer with a thickness of 50 nm, a GaSb layer with a thickness of 18 nm formed thereon, a channel layer made of InAs with a thickness of 12 nm, and a layer formed thereon An Al _0.7 Ga _0.3 Sb layer with a thickness of 25 nm, a cap layer with a thickness of 5 nm made of GaSb formed thereon, an oxide layer with a thickness of 20 nm made of aluminum oxide formed thereon, and A Ti / Au gate electrode formed; and a source electrode and a drain electrode made of an AuGeNi alloy that are disposed across the gate electrode and are ohmic-connected to the channel layer. The first comparison element has a form in which no impurity that becomes a shallow acceptor is introduced into AlGaSb.

The second comparison element includes a first barrier layer made of Al _0.7 Ga _0.3 Sb with a thickness of 50 nm, a channel layer made of InAs formed thereon with a thickness of 15 nm, and an Al _0.7 layer formed thereon. A second barrier layer made of Ga _0.3 Sb with a thickness of 30 nm, a cap layer made of GaSb with a thickness of 5 nm formed thereon, and an oxide layer made of aluminum oxide with a thickness of 20 nm formed thereon; And a gate electrode made of Ti / Au formed thereon, and a source electrode and a drain electrode made of AuGeNi alloy, which are arranged across the gate electrode and are ohmic-connected to the channel layer. The second comparison element has a form in which an impurity that becomes a shallow acceptor is not introduced into the AlGaSb layer on the substrate side.

  In the first comparison element, when the sweep is reciprocated between 0V and 3V at 0.1V / 1 second, there is hysteresis as shown in FIG. Further, when the gate voltage is changed at a sweep rate of 0.1 V / 1 second, the electron concentration changes as shown by the solid line in FIG. Note that the region 601 is a pinch-off region where electrons disappear. Further, in the first comparison element, when the gate voltage is changed at a sweep speed of 1 V / 30 minutes, the electron concentration changes in a state different from the case of the solid line as shown by the one-dot chain line in FIG. Thus, the first comparison element shows different changes depending on the sweep speed of the gate voltage. Thus, in the first comparison element, the influence of the slow response that the acceptor region that accommodates electrons changes is observed.

  Next, in the second comparison element, when the sweep is reciprocated between 0 V and 4 V at 0.1 V / 1 second, the hysteresis becomes smaller than that of the first comparison element as shown in FIG. In the second comparison element, since the change of the acceptor region containing electrons is only on the substrate side, it can be seen that the influence is small when FIG. 5 is compared with FIG.

  Next, in the field effect transistor according to the present embodiment, when the sweep is reciprocated between 8 V and 11 V at 0.1 V / 1 second, as shown in FIG. Hysteresis is smaller than that of the first comparison element and the second comparison element. The electron concentration is determined one-to-one with respect to the gate voltage.

  Since the electron concentration is determined on a one-to-one basis with respect to the gate voltage, a faster and more stable operation is possible with respect to the second comparison element. Thus, according to the present embodiment, the electron concentration of the channel layer can be controlled efficiently, and there is no bistability or instability with respect to time, high-speed response is possible, and highly accurate characteristics are obtained. It will be obtained. It can also be seen that the above-described effects can be obtained if the first impurity introduction region 410 and the second impurity introduction region 411 are formed 5 nm apart from the channel layer 403.

  The present invention is not limited to the embodiments described above, and many combinations and modifications can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. Although the case where the first barrier layer and the second barrier layer are made of AlGaSb has been described above, the present invention is not limited to this, and the first barrier layer and the second barrier layer may be made of AlSb. The first barrier layer and the second barrier layer may be made of a compound semiconductor selected from AlGaSb and AlSb.

  In the above description, the case where Be is introduced into the first barrier layer and the second barrier layer as an impurity that becomes a shallow acceptor has been described. However, the present invention is not limited to this. The impurity may be selected from zinc (Zn), magnesium (Mg), carbon (C), and Be.

  In the above description, as an example, the first impurity introduction region and the second impurity introduction region are formed by delta doping of impurities, but the present invention is not limited to this, and the first impurity introduction region is uniformly doped. In addition, a second impurity introduction region may be formed.

For example, when a first barrier layer is formed by epitaxially growing Al _0.7 Ga _0.3 Sb by molecular beam epitaxy, irradiation with a Be beam is performed so that Be is introduced at a rate of about 1 × 10 ¹⁸ cm ^−3. After the Al _0.7 Ga _0.3 Sb layer is formed to a thickness of about 45 nm, the Be beam shutter and valve are closed to stop the irradiation, and then the Al _0.7 Ga _0.3 Sb epitaxial growth is continued for 5 nm. . Thus, the first impurity introduction region can be formed at a distance of about 5 nm from the channel layer.

Further, when the Al _0.7 Ga _0.3 Sb on the channel layer by molecular beam epitaxy grown epitaxially forming a second barrier layer, firstly, a layer of Al _0.7 Ga _0.3 Sb without irradiation of Be beams After forming a layer thickness of about 5 nm, a Be beam is irradiated so that Be is introduced at a rate of about 1 × 10 ¹⁸ cm ⁻³ to form an Al _0.7 Ga _0.3 Sb layer having a layer thickness of about 25 nm. Thus, the second impurity introduction region can be formed at a distance of about 5 nm from the channel layer.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... First barrier layer, 103 ... Channel layer, 104 ... Second barrier layer, 105 ... Cap layer, 106 ... Oxide layer, 107 ... Gate electrode, 108 ... Source electrode, 109 ... Drain electrode, 110 ... first impurity introduction region, 111 ... second impurity introduction region.

Claims (3)

A first barrier layer made of a compound semiconductor selected from AlGaSb and AlSb formed on a substrate;
A channel layer made of InAs formed on the first barrier layer;
A second barrier layer made of a compound semiconductor selected from AlGaSb and AlSb formed on the channel layer;
A cap layer made of GaSb formed on the second barrier layer;
An oxide layer formed on the cap layer;
A gate electrode formed on the oxide layer;
A source electrode and a drain electrode which are arranged across the gate electrode and are in ohmic contact with the channel layer;
Impurities that are formed in the first barrier layer and become shallow acceptors with respect to the compound semiconductor are introduced , electrons are accommodated in the shallow acceptors, and electrons are not accommodated in the deep acceptor of the compound semiconductor. When,
Impurities that are formed in the second barrier layer and become shallow acceptors for the compound semiconductor are introduced , electrons are accommodated in the shallow acceptor, and electrons are not accommodated in the deep acceptor of the compound semiconductor. And
The field effect transistor according to claim 1, wherein the first impurity introduction region and the second impurity introduction region are formed apart from the channel layer in a range that does not cause impurity scattering in electrons of the channel layer. The field effect transistor of claim 1, wherein
The field effect transistor according to claim 1, wherein the first impurity introduction region and the second impurity introduction region are formed 5 nm apart from the channel layer. The field effect transistor according to claim 1 or 2,
The field effect transistor according to claim 1, wherein the impurity is selected from zinc, magnesium, carbon, and beryllium.