JP5585576B2 - Manufacturing method of electronic parts - Google Patents

Description

  The present invention relates to a method for manufacturing an electronic component, and more particularly, to a method for manufacturing an electronic component including a laminate in which insulator layers are stacked.

  As a conventional method for manufacturing an electronic component, for example, a method for manufacturing a surface-mounted electronic component described in Patent Document 1 is known. Hereinafter, a method for manufacturing the surface mount electronic component will be described with reference to the drawings. FIG. 12 is a perspective view showing a manufacturing process of the surface mount electronic component 501 described in Patent Document 1. In FIG.

  First, a mother laminate 510 in which a coil is incorporated is manufactured. Specifically, a flat mother laminate 510 is produced by laminating a ceramic sheet and a conductor layer. Then, the mother laminate 510 is fired.

  Next, as illustrated in FIG. 12A, a U-shaped groove 511 extending in a predetermined direction is formed in the mother stacked body 510.

  Next, as shown in FIG. 12B, external electrodes 506 are formed around the groove 511 and its periphery. For example, a conductive paste is applied and baked around the groove 511 and its periphery. Next, as shown in FIG. 12C, the mother laminate 510 is cut to obtain a plurality of surface mount electronic components 501. According to the method for manufacturing the surface mount electronic component 501 as described above, it is possible to obtain the surface mount electronic component 501 that can be easily inspected for solderability and does not interfere with the insulation on the upper surface of the substrate.

  By the way, in the method for manufacturing the surface mount electronic component 501, the external electrode 506 is formed on the mother laminate 510 after the mother laminate 510 is fired. Therefore, at the time of firing the mother laminate 510, the shrinkage behavior of the external electrode 506 and the shrinkage behavior of the mother laminate 510 are different, and unnecessary stress is generated between the external electrode 506 and the mother laminate 510. End up. As a result, in the method for manufacturing the surface mount electronic component 501, the external electrode 506 may not sufficiently adhere to the mother laminate 510.

JP-A-7-106144

  Then, the objective of this invention is providing the manufacturing method of the electronic component which can suppress that an external electrode peels from a laminated body.

In a method for manufacturing an electronic component according to an aspect of the present invention, a plurality of first insulator layers and a plurality of first conductor layers are provided on the first insulator layer. And a step of forming on the first insulator layer a second insulator layer provided with a plurality of first grooves extending in a predetermined direction when viewed from the stacking direction. And a second conductor layer serving as an external electrode with respect to the inner peripheral surface of the first groove and the region adjacent to the first groove on the second insulator layer. A step of electrically connecting to the conductor layer, and a step of firing the first insulator layer, the second insulator layer, the first conductor layer, and the second conductor layer together. It is characterized by comprising.

  According to this invention, it can suppress that an external electrode peels from a laminated body.

It is a perspective view of the electronic component which concerns on one Embodiment of this invention. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. FIG. 2 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. It is a perspective view of the electronic component which concerns on a modification. FIG. 10 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component of FIG. 9. It is a perspective view of the electronic component which concerns on another modification. FIG. 10 is a perspective view showing a manufacturing process of the surface mount electronic component described in Patent Document 1.

  Below, the manufacturing method of the electronic component which concerns on embodiment of this invention is demonstrated, referring drawings.

(Configuration of electronic parts)
Below, the structure of the electronic component produced in the manufacturing method which concerns on one Embodiment of this invention is demonstrated, referring drawings. FIG. 1 is a perspective view of an electronic component 10a according to an embodiment of the present invention. In the present embodiment, the direction in which the insulator layers are stacked when the electronic component 10a is formed is defined as the upward direction in the stacking direction. In the electronic component 10a, since the insulator layers are stacked from the upper side to the lower side in FIG. 1, the upward direction in the stacking direction is the downward direction in FIG. The stacking direction is defined as the z-axis direction. In addition, a direction along the long side of the electronic component 10a is defined as an x-axis direction, and a direction along the short side of the electronic component 10a is defined as a y-axis direction.

  As shown in FIG. 1, the electronic component 10a includes a laminate 12 and external electrodes 14 (14a, 14b). The laminated body 12 is configured by laminating an insulator layer and a conductor layer, and has a rectangular shape. The laminated body 12 has a built-in coil L. In FIG. 1, the coil L is a schematic diagram and is different from the actual shape.

  The external electrode 14a is provided on the surface of the multilayer body 12 on the positive side in the z-axis direction, is constituted by the conductor layers 15a and 16a, and is connected to the conductor layer 17a. The conductor layer 15a extends along the short side on the negative direction side in the x-axis direction on the surface on the positive direction side in the z-axis direction of the multilayer body 12. The conductor layer 16a extends along the side on the negative side in the x-axis direction of the multilayer body 12 along the side on the positive direction side in the z-axis direction. In addition, the conductor layer 17a extends in the y-axis direction at a position away from the conductor layer 15a by a predetermined distance to the negative direction side in the z-axis direction in the multilayer body 12. The conductor layer 15a and the conductor layer 16a are connected, and the conductor layer 16a and the conductor layer 17a are connected. Therefore, the external electrode 14a and the conductor layer 17a have a U-shape when viewed in plan from the y-axis direction.

  The external electrode 14b is provided on the surface of the multilayer body 12 on the positive side in the z-axis direction, is configured by the conductor layers 15b and 16b, and is connected to the conductor layer 17b. The conductor layer 15 b extends along the short side on the positive direction side in the x-axis direction on the surface on the positive direction side in the z-axis direction of the multilayer body 12. The conductor layer 16b extends along the side on the positive direction side in the z-axis direction on the side surface on the positive direction side in the x-axis direction of the multilayer body 12. In addition, the conductor layer 17b extends in the y-axis direction at a position away from the conductor layer 15b by a predetermined distance to the negative direction side in the z-axis direction in the multilayer body 12. The conductor layer 15b and the conductor layer 16b are connected, and the conductor layer 16b and the conductor layer 17b are connected. Therefore, the external electrode 14b and the conductor layer 17b are U-shaped when viewed in plan from the y-axis direction.

  As shown in FIG. 1, the coil L has a coil axis extending in the z-axis direction and is connected between the external electrodes 14a and 14b. In addition, the coil L is actually comprised by the coil conductor and via-hole conductor mentioned later.

  A direction recognition mark 60 is provided on the surface of the laminate 12 on the negative direction side in the z-axis direction. The direction recognition mark 60 is a mark for confirming the direction of the electronic component 10a when the electronic component 10a is mounted.

(Method for manufacturing electronic parts)
Below, the manufacturing method of the electronic component 10a which concerns on one Embodiment of this invention is demonstrated, referring drawings. 2 to 8 are a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component 10a. 2 to 8, the upper direction of FIGS. 2 to 8 is the positive direction of the z-axis direction. 2 to 8 show the manufacturing process of the plurality of electronic components 10a. 2 to 8 are cut lines L1 to L4 when cut into a plurality of electronic components 10a. The cut lines L1 and L2 extend in the y-axis direction, and the cut lines L3 and L4 extend in the x-axis direction. The cut line L1 is located on the negative direction side in the x-axis direction from the cut line L2, and the cut line L3 is located on the negative direction side in the y-axis direction from the cut line L4.

  First, as shown in FIG. 2A, an insulating layer 120 is formed by applying a ceramic insulating paste mainly composed of glass mixed with a blue paint. The insulator layer 120 has an area corresponding to a plurality of negative-side surfaces in the z-axis direction of the stacked body 12, and is a layer free from defects, blank portions, and the like.

  Next, as shown in FIG. 2B, in the insulator layer 120, when viewed in plan from the z-axis direction, a resist film is formed in a region overlapping the region where the circular direction recognition mark 60 shown in FIG. 50a is formed. Further, as shown in FIG. 2C, light is irradiated (exposed) using the resist film 50a as a mask. Thereby, in the insulator layer 120, regions other than the region where the resist film 50a is provided are cured by light. Thereafter, the resist film 50a is removed and development is performed to remove the insulator layer 120 in the region where the resist film 50a is provided, as shown in FIG. By the photolithography process shown in FIGS. 2A to 3A as described above, the insulator layer 20 provided with the opening O1 is formed.

  Next, as shown in FIG. 3B, an insulating layer 22a is formed on the insulating layer 20 by applying a ceramic insulating paste mainly composed of glass. At this time, the opening O1 is filled with an insulating paste. The insulating paste used for forming the insulator layer 22a is not mixed with blue paint. Therefore, the direction recognition mark 60 shown in FIG. 1 is formed on the insulator layer 20.

  Next, as shown in FIG. 3C, a conductive paste containing Ag as a main component is applied on the insulator layer 22a to form a conductor layer 124a. The conductor layer 124a has an area corresponding to a plurality of negative-side surfaces in the z-axis direction of the multilayer body 12, and is a layer that does not have any defects or blank portions.

  Next, as shown in FIG. 4A, in the conductor layer 124a, an opening O2 is provided in a region overlapping the region where the coil conductor 24a in FIG. 4C is formed when viewed in plan from the z-axis direction. A resist film 50b is formed. Further, as shown in FIG. 4B, light is irradiated (exposed) using the resist film 50b as a mask. Thereby, in the conductor layer 124a, a region other than the region where the resist film 50b is provided (that is, a region overlapping with the opening O2) is cured by light. Thereafter, the resist film 50b is removed and development is performed to remove the conductor layer 124a in the region where the resist film 50b is provided, as shown in FIG. 4C. The coil conductor 24a is formed on the insulator layer 22a by the photolithography process shown in FIGS. 3C to 4C as described above.

  Next, as shown in FIG. 5A, an insulator layer 22b having openings O3 and O4 is formed on the insulator layer 22a and the coil conductor 24a by a photolithography process. The openings O3 and O4 are located at both ends of the coil conductor 24a, and become via-hole conductors b1 and B1 shown in FIG. Note that the photolithography process in FIG. 5A is the same as the photolithography process described in FIGS. 2A to 3A, and thus the description thereof is omitted.

  Next, as shown in FIG. 5B, the coil conductor 24b is formed on the insulator layer 22b by the photolithography process, and the via-hole conductors b1 and B1 are formed in the openings O3 and O4 of the insulator layer 22b. To do. Thereby, the coil conductors 24a and 24b are connected via the via-hole conductor b1. Note that the photolithography process in FIG. 5B is the same as the photolithography process described in FIG. 3C to FIG.

  Next, as shown in FIG. 5C, an insulator layer 22c provided with openings O5 and O6 is formed on the insulator layer 22b and the coil conductor 24b by a photolithography process. The opening O5 is located at one end of the coil conductor 24b, and becomes a via-hole conductor b2 shown in FIG. 6A by being filled with a conductive paste in a process described later. The opening O6 is provided so as to overlap with the via-hole conductor B1 when viewed in plan from the z-axis direction, and is filled with a conductive paste in a process described later, whereby the via-hole conductor B2 shown in FIG. It becomes. Note that the photolithography process in FIG. 5C is the same as the photolithography process described with reference to FIGS.

  Next, as shown in FIG. 6A, the coil conductor 24c is formed on the insulator layer 22c by the photolithography process, and the via-hole conductors b2 and B2 are formed in the openings O5 and O6 of the insulator layer 22b. To do. Thereby, the coil conductors 24b and 24c are connected via the via-hole conductor b2. Note that the photolithography process in FIG. 6A is the same as the photolithography process described in FIGS. 3C to 4C, and thus the description thereof is omitted. Thereafter, by repeating the steps shown in FIGS. 5A to 6A, the insulator layers 22d and 22e, the coil conductors 24d to 24e, and the via-hole conductors b3, b4, B3, and B4 are formed. The coil conductors 24c and 24e have the shape shown in FIG. 6A and have the number of turns of one turn. Further, the coil conductors 24b and 24d have the shape shown in FIG. 5B and have the number of turns of one turn. That is, in the coil L, two types of coil conductors 24 are alternately arranged in the z-axis direction.

  Next, as shown in FIG. 6B, an insulator layer 22f provided with openings O7 and O8 is formed on the insulator layer 22e and the coil conductor 24e by a photolithography process. Since the process shown in FIG. 6B is the same as the process shown in FIG. 5A, further detailed description is omitted.

  Next, as shown in FIG. 6C, a coil conductor 24f and conductor layers 17a and 17b are formed on the insulator layer 22f by a photolithography process, and via holes are formed in the openings O7 and O8 of the insulator layer 22f. Conductors b5 and B5 are formed. More specifically, the conductor layer 17a extending in the y-axis direction along the cut line L1 is formed, and the conductor layer 17b extending in the y-axis direction along the cut line L2 is formed. In FIG. 6C, since the plurality of electronic components 10a are simultaneously formed, the conductor layer 17a is also formed on the negative side of the conductor layer 17a in the x-axis direction. Similarly, the conductor layer 17b is also formed on the positive side of the conductor layer 17b in the x-axis direction. As shown in FIG. 6, the two conductor layers 17a and 17b arranged side by side have a width W1 in the x-axis direction when viewed in plan from the z-axis direction.

  One end of the coil conductor 24f is connected to the conductor layer 17a. On the other hand, the via-hole conductor B5 is connected to the conductor layer 17b. Thereby, the conductor layer 17b is connected to the coil conductor 24a via the via-hole conductors B1 to B5 (the via-hole conductors B3 and B4 are not shown). Therefore, the coil L is connected between the conductor layers 17a and 17b. As described above, the insulator layers 20 and 22a to 22f, the coil conductors 24a to 24e, and the coil conductors 24 and 24e are obtained by laminating the insulator layer and the conductor layer in the steps shown in FIGS. Via-hole conductors b1 to b4 and B1 to B4 are formed.

  Next, as shown in FIG. 7A, an insulator layer 22g having openings O9 and O10 is formed on the insulator layer 22g, the coil conductor 24f, and the conductor layers 17a and 17b by a photolithography process. . The opening O9 is a groove extending in the y-axis direction so as to overlap the cut line L1 and the conductor layer 17a when viewed in plan from the z-axis direction. The opening O9 has a width W2 that is narrower than the width W1 of the two conductor layers 17a. The opening O10 is a groove extending in the y-axis direction so as to overlap the cut line L2 and the conductor layer 17b when viewed in plan from the z-axis direction. The opening O10 has a width W2 that is narrower than the width W1 of the two conductor layers 17b. The openings O9 and O10 overlap so as not to protrude from the conductor layers 17a and 17b, respectively.

  Next, as shown in FIG. 7B, an insulator layer 22h provided with openings O11 and O12 is formed on the insulator layer 22g by a photolithography process. The opening O11 is a groove extending in the y-axis direction so as to overlap the cut line L1 and the opening O9 when viewed in plan from the z-axis direction. The opening O11 has a width W3 wider than the width W1 of the conductor layer 17a and the width W2 of the opening O9. The opening O12 is a groove extending in the y-axis direction so as to overlap the cut line L2 and the opening O10 when viewed in plan from the z-axis direction. The opening O12 has a width W3 wider than the width W1 of the conductor layer 17b and the width W2 of the opening O10. The conductor layers 17a and 17b and the openings O9 and O10 overlap so as not to protrude from the openings O11 and O12, respectively.

  Next, as shown in FIG. 7C, the inner peripheral surfaces of the openings O9 and O10 and the region adjacent to the openings O9 and O10 on the insulator layer 22g when viewed in plan from the z-axis direction. Thus, the conductor layers 15a, 15b, 16a, and 16b to be the external electrodes 14a and 14b are formed so as to be electrically connected to the coil conductor 24. Specifically, the openings O9 to O12 are filled with a conductive material by a photolithography process. Thereby, conductor layers 16a and 16b are formed in the openings O9 and O10, respectively, and conductor layers 15a and 15b are formed in the openings O11 and O12, respectively. When viewed in plan from the z-axis direction, the regions adjacent to the openings O9 and O10 on the insulator layer 22g are the openings O11 and O12 when viewed in plan from the z-axis direction in FIG. 7B. In FIG. 3, the region does not overlap the openings O9 and O10. Through the above steps, an unfired mother laminate 112 made of the insulator layers 20 and 22a to 22h is obtained.

  Next, the mother laminated body 112 is cut along the openings O9 and O10 to obtain a plurality of unfired laminated bodies 12. Specifically, the mother laminate 112 is cut along the cut lines L1 to L4. Thereby, the unfired laminated body 12 shown in FIG. 8 is obtained.

  Next, the plurality of unfired laminated bodies 12 are fired at a temperature of 800 ° C. or higher. Thereby, the insulator layers 20, 22a to 22h, the coil conductors 24a to 24f, the via-hole conductors b1 to b5, B1 to B5, and the conductor layers 15a, 15b, 16a, 16b, 17a, and 17b are fired simultaneously.

  The fired laminated body 12 is obtained through the above steps. Next, the laminated body 12 is barrel-processed and chamfered. Finally, the external electrodes 14a and 14b are formed by performing Ni plating / Sn plating on the surfaces of the conductor layers 15a, 15b, 16a and 16b. Through the above steps, an electronic component 10a as shown in FIG. 1 is completed.

(effect)
According to the manufacturing method of the electronic component 10a as described above, the external electrode 14 can be prevented from being peeled off from the multilayer body 12 as described below. More specifically, in the conventional method for manufacturing the surface mount electronic component 501 (see FIG. 12), the external electrode 506 is formed on the mother laminate 510 after the mother laminate 510 is fired. Therefore, in the method for manufacturing the surface mount electronic component 501, the external electrode 506 may not sufficiently adhere to the mother laminate 510.

  Therefore, in the manufacturing method of the electronic component 10a, the laminate 12 and the external electrode 14 are fired simultaneously. Thereby, at the time of baking the laminated body 12 and the external electrode 14, the shrinkage behavior of the laminated body 12 and the shrinkage behavior of the external electrode 14 can be aligned, and unnecessary stress is generated between the laminated body 12 and the external electrode 14. Occurrence can be suppressed. For this reason, in the electronic component 10 a, the external electrode 14 comes into close contact with the multilayer body 12 as compared with the surface-mounted electronic component 501. As a result, according to the method for manufacturing the electronic component 10a, the external electrode 14 is prevented from being peeled from the multilayer body 12.

  Moreover, according to the manufacturing method of the electronic component 10a, it can suppress that the external electrode 14 peels from the laminated body 12 also for the following reasons. More specifically, in the electronic component 10 a, the conductor layer 17 connected to the external electrode 14 is provided in the multilayer body 12. Therefore, an anchor effect occurs between the conductor layer 17 and the multilayer body 12. As a result, according to the method for manufacturing the electronic component 10a, the external electrode 14 is prevented from being peeled from the multilayer body 12.

  Moreover, according to the manufacturing method of the electronic component 10a, the stray capacitance generated between the external electrode 14 and the coil L can be reduced as described below. More specifically, the external electrode 14 is provided only on a part of the surface of the multilayer body 12 on the positive side in the z-axis direction and a part of the side surface of the multilayer body 12 located at both ends in the x-axis direction. Therefore, in the electronic component 10a, for example, the area where the external electrode 14 and the coil L face each other is smaller than when the external electrode 14 is provided on the entire side surface located at both ends of the laminated body 12 in the x-axis direction. Become. As a result, in the electronic component 10a, stray capacitance generated between the external electrode 14 and the coil L can be reduced.

(Modification)
Below, the manufacturing method of the electronic component 10b which concerns on a modification is demonstrated, referring drawings. FIG. 9 is a perspective view of an electronic component 10b according to a modification. The difference between the electronic component 10a and the electronic component 10b is that, in the electronic component 10a, the conductor layers 15a and 15b are embedded in the multilayer body 12, whereas in the electronic component 10b, the conductor layers 15a and 15b are different from the multilayer body 12. It is a point formed on the surface on the positive direction side in the z-axis direction.

  Below, the manufacturing method of the electronic component 10b is demonstrated, referring drawings. FIG. 10 is a top view and a cross-sectional structure diagram in the manufacturing process of the electronic component 10b. Until the step of forming the insulator layer 22g in the manufacturing process of the electronic component 10b (see FIG. 10A), the step of forming the insulator layer 22g in the manufacturing process of the electronic component 10a (see FIG. 7A). ).

  Next, as shown in FIG. 10B, the inner peripheral surfaces of the openings O9 and O10 and the region adjacent to the openings O9 and O10 on the insulator layer 22g when viewed in plan from the z-axis direction. Thus, conductor layers 15a, 15b, 16a, 16b to be the external electrodes 14a, 14b are formed. Specifically, the openings O9 and O10 are filled with a conductive material to form conductor layers 15a and 15b by a photolithography process, and the cut lines L1 and L2 are defined when viewed in plan from the z-axis direction. Conductor layers 16a and 16b having a width W3 as the center in the x-axis direction are formed. Thereby, the unbaked mother laminated body 112 which consists of the insulator layers 20 and 22a-22g is obtained.

  Next, the mother laminated body 112 is cut along the openings O9 and O10 to obtain a plurality of unfired laminated bodies 12. Specifically, the mother laminate 112 is cut along the cut lines L <b> 1 to L <b> 4 to obtain a plurality of unfired laminates 12. Further, the plurality of unfired laminates 12 are fired at a temperature of 800 ° C. or higher. Thereby, the insulator layers 20, 22a to 22g, the coil conductors 24a to 24f, the via-hole conductors b1 to b5, B1 to B5, and the conductor layers 15a, 15b, 16a, 16b, 17a, and 17b are simultaneously fired. Since the process performed after this is the same as the process performed in the electronic component 10a, description thereof is omitted.

  FIG. 11 is a perspective view of an electronic component 10c according to another modification. As shown in FIG. 11, the external electrode 14 may further include conductor layers 16 (16′a, 16′b) and 17 (17′a, 17′b). The conductor layer 16 ′ is provided on the side surface of the multilayer body 12 on the negative side of the conductor layer 16 in the z-axis direction. In addition, the conductor layer 17 ′ extends in the y-axis direction at a position away from the conductor layer 17 by a predetermined distance on the negative direction side in the z-axis direction in the multilayer body 12. The conductor layer 16 and the conductor layer 16 ′ are connected, and the conductor layer 16 ′ and the conductor layer 17 ′ are connected. According to such an electronic component 10c, it is possible to more effectively reduce the external electrode 14 from being peeled from the stacked body 12.

  The circuit element built in the laminate 12 is not limited to the coil L. Therefore, the laminated body 12 may contain elements such as capacitors and filters.

  Moreover, the conductor layer 17 does not necessarily need to be provided.

  Further, instead of exposure through the resist films 50a and 50b, exposure may be performed through a photomask.

  INDUSTRIAL APPLICABILITY The present invention is useful for a method for manufacturing an electronic component, and is particularly excellent in that the external electrode can be prevented from peeling from the laminate.

B1-B5, b1-b5 Via-hole conductor L Coil L1-L4 Cut line O1-O12 Opening 10a-10c Electronic component 12 Laminated body 14a, 14b External electrode 15a, 15b, 16a, 16b, 16'a, 16'b, 17a , 17b, 17'a, 17'b, 124a Conductor layer 20, 22a-22h, 120 Insulator layer 24a-24f Coil conductor 50a, 50b Resist film 60 Direction recognition mark 112 Mother laminate

Claims (6)

Laminating a plurality of first insulator layers and a plurality of first conductor layers so that the first conductor layer is provided on the first insulator layer;
Forming a second insulator layer provided with a plurality of first grooves extending in a predetermined direction when viewed from the stacking direction on the first insulator layer;
A second conductor layer serving as an external electrode is formed on the inner peripheral surface of the first groove and a region adjacent to the first groove on the second insulator layer. Forming to be electrically connected to;
Firing the first insulator layer, the second insulator layer, the first conductor layer and the second conductor layer together;
Having
A method of manufacturing an electronic component characterized by the above. Cutting a mother laminate including the first insulator layer and the second insulator layer along the first groove to obtain a plurality of laminates;
In addition,
In the step of collectively firing the first insulator layer, the second insulator layer, the first conductor layer, and the second conductor layer, firing the plurality of stacked bodies,
The manufacturing method of the electronic component of Claim 1 characterized by these. The step of laminating the plurality of first insulator layers and the plurality of first conductor layers includes:
Forming a third conductor layer extending in the predetermined direction on the first insulator layer;
Including
In the step of forming the second insulator layer, when viewed in plan from the stacking direction, the first groove overlaps the third conductor layer and is wider than the width of the third conductor layer. Forming the second insulator layer on the first insulator layer and the third conductor layer so as to have a narrow width;
The method for manufacturing an electronic component according to claim 1, wherein: A third insulator layer provided so that the second groove having a width wider than the first groove overlaps the first groove when viewed in plan from the stacking direction; Forming on the two insulator layers,
In addition,
Filling the first groove and the second groove with a conductive material in the step of forming the second conductor layer;
The manufacturing method of the electronic component of Claim 1 characterized by these. Cutting a mother laminate including the first insulator layer, the second insulator layer, and the third insulator layer along the first groove to obtain a plurality of laminates;
In addition,
In the step of collectively firing the first insulator layer, the second insulator layer, the first conductor layer, and the second conductor layer, firing the plurality of stacked bodies,
The manufacturing method of the electronic component of Claim 4 characterized by these. The second insulator layer provided with the first groove is formed by a photolithography process;
The method for manufacturing an electronic component according to claim 1, wherein:

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