JP5589263B2 - Method for forming trench in silicon carbide semiconductor substrate - Google Patents

Description

  The present invention relates to a method for forming a trench by etching in a semiconductor power device such as a MOSFET using a silicon carbide semiconductor (hereinafter abbreviated as SiC) used for high breakdown voltage and large current.

A semiconductor power device using a silicon (Si) semiconductor is a device that is usually used for an inverter, power control, and the like, and includes a power MOSFET and an IGBT. However, the improvement of the semiconductor characteristics in the silicon (hereinafter abbreviated as Si) semiconductor has already reached the ultimate level, and the power device is approaching the characteristic limit due to the physical properties of the silicon semiconductor. On the other hand, SiC (4H-SiC) semiconductors have not only a single-digit higher breakdown electric field than silicon semiconductors, but also have a band gap of 2.9 times, a thermal conductivity of 3.2 times, and a temperature at which an intrinsic semiconductor becomes a semiconductor. From 3 to 4 times, particularly from the viewpoint of power device materials, it has extremely excellent physical properties. In addition, power devices using silicon carbide (hereinafter abbreviated as SiC) semiconductors are also expected as devices having a low on-resistance while having a high breakdown voltage, and in recent years, many approaches to commercialization of semiconductor power devices have been made. To date, rectifying devices such as diodes and switching devices such as transistors and thyristors have been prototyped. Among such switching devices, in particular, UMOSFET (trench type insulated gate field effect transistor) can increase the channel density by miniaturizing the trench gate structure and the unit pattern having the channel. It has a feature that it can be further reduced, and has attracted particular attention.

The manufacturing method is almost the same as the manufacturing method of a normal Si semiconductor power device. After forming a trench by anisotropic etching in a SiC semiconductor substrate (which may be abbreviated as SiC substrate), an oxidation used as an etching mask. After the film is removed and a gate insulating film is formed, the trench is filled with polycrystalline silicon serving as a gate electrode. Thereafter, the source / drain electrodes are formed to form a trench MOS type SiC semiconductor device.
However, in the case of a SiC substrate, the physical hardness of the substrate is high, and it is a chemically difficult to etch material. Therefore, as a mass production trench formation method, RIE (normally used for trench formation of Si semiconductors) is used. Unlike the Reactive Ion Etching (etching) method, trench formation must be performed by physical etching (dry etching) in which the surface is scraped by colliding accelerated plasma ions with the substrate. Therefore, it is difficult to control the shape of the Si semiconductor in which the trench is formed by the RIE method, and it cannot be said that etching with a good shape is easy. For example, it is often difficult to make the shape of the bottom of the trench into a U-shape that is preferable for the breakdown voltage characteristics of a semiconductor device and to improve the smoothness of the trench side wall only by physical dry etching. As a result, in the trench shape having a width of about 3 μm immediately after the dry etching, the edge corner of the trench opening portion is sharp, or there are shape defects such as protrusions and surface irregularities on the sidewall and bottom of the trench. When such a shape defect is present in the trench, there is a problem that electric field concentration is likely to occur in that portion and the withstand voltage is likely to be lowered.

Further, as an etching method of SiC, it is immersed in a KOH (potassium hydroxide) solution heated to 450 ° C. to 600 ° C. or dry etched by reactive ion etching (RIE). However, wet etching with KOH only etches crystal defects on the Si surface (silicon surface) of SiC having a crystal structure of 4H. In the case of C surface (carbon surface), the entire substrate surface is etched. Therefore, it is difficult to form a concave portion having an arbitrary shape. Accordingly, the formation of the recess in SiC is generally performed by dry etching. In order to perform dry etching, it is necessary to cover an unetched portion with a mask material (Ni, Al metal or oxide such as SiO ₂ ) and perform anisotropic etching. ₆ + O ₂ or CF ₄ + O ₂ ) or a chlorine-based gas (Cl ₂ + O ₂ ) must be introduced to generate a high-density plasma for reaction. Therefore, side etching or sub-trench may occur in the etching shape, and it is difficult to control the angle of the etching side wall, and it is difficult to etch vertically.
For example, when fabricating a trench type semiconductor device (such as a trench MOSFET) using SiC, it is difficult to control the taper angle of the mask material or the etching condition, and the trench angle varies, side etching or sub-etching is performed. A trench or the like may occur, and the shape may be inconvenient. In this way, it is often difficult to control the angle of the side wall of the SiC recess formed by dry etching.

The above-mentioned problems such as shape defects that occur when a trench is formed by physical dry etching, in which plasma particles accelerated under high pressure under high pressure are struck against such a SiC substrate and cut off, It is already improved by heat treatment at a temperature of 1700 ° C. or lower in a mixed gas atmosphere of (hereinafter referred to as H ₂ ) and argon (hereinafter referred to as Ar) or by surface etching in the trench with hydrogen at 1300 ° C. or higher under reduced pressure. It has been announced (Patent Documents 1 and 2).
JP 2005-332013 A JP 2005-332014 A

However, in the case of an SiC substrate, hydrogen is used at a high temperature in the improvement methods described in Patent Documents 1 and 2 regarding the shape defect at the time of trench formation. Since not only silicon atoms but also carbon atoms exist, carbon atoms become obstacles, and surface diffusion of Si atoms, which was effective for smoothing on the Si surface, is difficult to be actively performed on the SiC surface, and the smoothing effect Is not so big.
Furthermore, since the SiC substrate is more active in etching the SiC surface by high-temperature hydrogen than the surface diffusion of atoms and its control is difficult, it has been found that the influence of the high-temperature hydrogen treatment on the shape control is greater. As a result, it has been found that high-temperature hydrogen treatment is difficult to adopt in the sense of a practical production method for improving the shape of the trench because the trench shape tends to change excessively as it is.
This invention is made | formed in view of such a point, and when the trench is formed in a silicon carbide (SiC) board | substrate by dry etching, the objective of this invention is to make smooth the surface property in a trench easily. At the same time, it is to provide a method for manufacturing a silicon carbide semiconductor device capable of setting the side wall angle of the trench to 90 °.

The present invention relates to a method for forming a trench by etching a substrate having a silicon carbide epitaxial film formed on the surface of a silicon carbide single crystal substrate having a {0001} plane as a main surface or a silicon carbide single crystal substrate. After formation , in a mixed vacuum atmosphere of silane and argon with a silane flow rate sccm (standard cc / min) ratio of 0.3% or more and 0.6% or less with respect to argon in a temperature range of 1700 ° C to 1800 ° C for 60 minutes or more Heat treatment is performed so that the sidewall angle of the trench is 88 ° or more.
In the present invention, the trench is formed by dry etching.
Further, according to the present invention, the atmosphere in the mixed reduced pressure atmosphere is 2666.44 Pa (20 Torr) to 1.01325 × 10 ⁵ Pa (760 Torr).
In the present invention, when the crystal orientation of the side wall surface of the trench is 4H—SiC, the (1-100) plane is used.

According to the present invention, problems such as side etching generated on the side wall by dry etching and sub-trench generated at the bottom of the etching are eliminated, and the etching angle of the side wall which is 90 ° or less is changed to heat treatment after etching. The side wall can be vertically deformed with good reproducibility. When the trench side wall is 88 ° or more , the mobility of the trench MOSFET is improved and the reproducibility of the mobility is enhanced.

Hereinafter, a method for forming a trench in a silicon carbide semiconductor (SiC) substrate according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. In the following description, the trench in the case of trench etching is intended not to deteriorate the breakdown voltage even if the trench for forming the MOS gate of the MOS type semiconductor device in the trench and the pn junction termination are exposed on the substrate surface. This includes a trench for obtaining a mesa surface to be formed, a trench for separating elements, a trench for forming a SiC microstructure by a MEMS technology, a trench for a diode, and the like.
FIG. 1 is an electron micrograph sectional view of a trench obtained by dry etching a SiC substrate, FIG. 2 is a characteristic diagram showing a relationship between a heat treatment pressure and a radius of curvature of a trench corner, and FIG. 3 is a heat treatment time and a trench. FIG. 4 to FIG. 6 are electron micrograph cross-sectional views of trenches with different heat treatment times, and FIG. 7 is created using the method according to the present invention. It is principal part sectional drawing of trench type MOSFET.

A SiO ₂ film is formed on SiC and patterned by RIE is used as an etching mask, and dry etching is performed to form a recess in SiC. After the etching, heat treatment is performed for 90 minutes or more in an atmosphere at a high temperature (1700 ° C. or higher) and a pressure of 20 Torr (2666.44 Pa) or higher and 760 Torr (1.01325 × 10 ⁵ Pa) or lower. By this heat treatment, SiC evaporates, aggregates and diffuses on the surface, and the shape of the recess is deformed. During the deformation, when a stable crystal plane (1-100) appears on the side wall, no further deformation occurs, and the side wall surface becomes completely vertical as a result.
A method of verticalizing the side walls of the recesses (trench) formed in SiC by dry etching will be described with reference to the drawings. After thoroughly cleaning the (000-1) C face of the SiC substrate with a crystal structure of 4H (or the C face substrate of a 4H-SiC substrate with an SiC epitaxial film), a SiO ₂ film of 2.5 μm is formed on the substrate by plasma CVD. Film. The film forming gas was SiH ₄ + O ₂ + Ar, 50 Pa pressure, 60 MHz VHF power 500 W, and substrate heating temperature 400 ° C. After cleaning the substrate after film formation, a resist is applied onto the SiO ₂ film with a coater. Thereafter, exposure was performed using a reticle having a 1 μm-wide trench pattern formed by a stepper apparatus. After exposure, development was performed, and after confirming that patterning was properly performed, baking was performed at 100 ° C. for 1 minute. Thereafter, in order to improve the RIE etching resistance of the resist, baking was further performed at 120 ° C. for 15 minutes. The thickness of the resist at this time is about 2.5 μm.

Next, the SiO ₂ film was dry-etched using a resist as a mask with an RIE etching apparatus. Etching was performed using a mixed gas of CHF ₃ / Ar = 10/10 sccm and a pressure of 3 Pa and an RF power of 75 W. Ashing is performed after etching to remove the remaining resist. The ashing was performed using a mixed gas of CHF ₃ / O ₂ = 4/100 sccm at a pressure of 150 Pa and an RF power of 150 W. After ashing, the resist was immersed in a stripping solution to completely remove the resist, immersed in isopropyl alcohol, washed with pure water and dried. SiC is dry-etched using the SiO ₂ mask thus prepared. An ICP etching apparatus was used as an etching apparatus. The etching conditions were ICP power 450 W, bias 8 W, etching gas SF ₆ / O ₂ /Ar=8.5/1.5/50 sccm, and etching under a pressure of 2 Pa. The etching depth was 3.5 μm to 4.5 μm.
After etching, the substrate was immersed in hydrofluoric acid for 30 minutes or longer to remove the remainder of the SiO ₂ mask. FIG. 1 shows the result of cross-sectional observation of the shape of the SiC trench in this state with an electron microscope (SEM). Side etching occurs from the trench opening in FIG. 1 to a depth of 0.5 μm to 1 μm (position of the arrow), and the trench width is slightly widened. It can also be seen that the width decreases and narrows toward the bottom of the trench. As a result, although the trench side wall depends on the location, the side wall angle becomes 78 ° deep and about 85 ° near the opening, and it is difficult to completely etch to 90 °.

Next, the SiC trench was heat-treated in a furnace in which a pressure of 2 to 760 Torr was controlled at a high temperature of 1800 ° C. or higher and a mixed gas of SiH ₄ and Ar could be introduced.
Figure 2 shows the change in the corner curvature radius of the trench opening due to the pressure during heat treatment. The heat treatment was performed at 1700 ° C. for 5 minutes in an Ar atmosphere containing SiH ₄ -0.4%. At 2 Torr, there was no change in the trench shape, and it was confirmed that no deformation occurred in SiC. Above 20 Torr, the trench corner gradually rounded, and above 120 Torr, the value of the radius of curvature remained unchanged until 760 Torr.
From this result, in order to deform SiC, a pressure of 20 Torr or more is required, and it is necessary to perform heat treatment in the range of 20 Torr to 760 Torr. In order to increase the amount of deformation, it is desirable to perform heat treatment at a pressure in the range of 80 Torr to 760 Torr.
FIG. 3 shows changes in the trench sidewall angle when the heat treatment is performed for 10 minutes to 120 minutes under the three conditions of heat treatment temperatures of 1600 ° C., 1700 ° C., and 1800 ° C. When the heat treatment temperature is high, the trench side wall angle becomes 90 ° in a short time. Even at a heat treatment of 120 minutes at a temperature of 1600 ° C, it does not deform until it is completely 90 °. As can be seen from FIG. 3, heat treatment for 90 minutes or more was required at 1700 ° C. and heat treatment for 60 minutes or more at 1800 ° C. was required to completely set the trench sidewall angle to 90 °. Even if the heat treatment is performed for a longer time, the side wall angle does not change and only the round amount of the trench corner increases. If the round at the trench corner is too large, the straight portion of the trench sidewall is reduced, which is not preferable as a trench MOS. When the trench sidewall becomes 90 °, the angle no longer changes. This is because the stable 1-100 plane (the second axis on the left side of 1 is shown as the negative coordinate display of the crystal axis) is exposed on the trench side wall, and the surface diffusion is more than that. This is thought to be because it does not happen. Thus, if the temperature and the heat treatment time are appropriately performed, the trench sidewall angle can be surely made vertical. Fig. 4 is a cross-sectional photograph taken with an electron microscope at 1700 ° C in SiH ₄ -0.4% added Ar gas at a pressure of 80 Torr for 10 minutes, Fig. 5 for 90 minutes, and Fig. 6 for 120 minutes. Show. Compared to the heat treatment of 1700 ° C for 10 minutes before the heat treatment in Fig. 1 (immediately after dry etching), the width of the deep part near the bottom of the trench is broadened, but the deformation (surface diffusion) of the side etching part is insufficient ( In the arrow portion in FIG. 4, it can be confirmed that the angle of the trench sidewall is not vertical. 1700 ° C 90 minutes, 1700 ° C 120 minutes heat treatment, the trench sidewall angle is 90 °, and the trench sidewall angle is the same vertical for 90 minutes or 120 minutes. It can be confirmed that when the is exposed, no further deformation of the shape occurs, and the trench side wall can be surely made vertical.

Table 1 shows the surface RMS (irregularity state) and Si / C composition ratio when the SiH ₄ gas flow rate is changed for the heat treatment in which SiH ₄ gas is added to Ar gas.
The amount of SiH ₄ added is the amount added to Ar gas, the surface RMS is an RMS value measured by an atomic force microscope (AFM) in the range of 10 μm square, and the Si / C composition ratio is obtained by analyzing the SiC surface by X-ray photoelectron spectroscopy. It is a result.

It can be seen that when SiH ₄ is not added (ie, 0%), the SiC surface is only roughened, Si is evaporated, and the Si / C ratio of the SiC surface is excessive. Thus, without addition of SiH ₄ , surface roughness and composition shift occur, the contact resistance increases in the trench MOSFET, and the channel mobility also decreases in the planar MOSFET. When the amount of SiH ₄ added is 0.8% or more, the surface roughness is reduced, but it is observed that many surface defects are generated, and Si is deposited on the substrate, and the Si / C ratio becomes Si excessive. If Si is deposited on the surface, a process for removing the Si is required, which is not preferable in terms of process and characteristics in manufacturing the SiC device. In order to reduce the surface roughness so that the Si / C composition does not change from 50/50, the addition amount of SiH ₄ gas to Ar is appropriately 0.3 to 0.6%.
As described above, there is a shape defect in dry etching, and even if it is difficult to control the recess sidewall angle, it is possible to perform heat treatment for 60 minutes or more at a heat treatment temperature of 1700 ° C to 1800 ° C in a reduced pressure atmosphere of 40 Torr to 760 Torr or more. As shown in FIG. 3, the trench side wall angle is improved by 2 ° or more to 88 ° or more, and the trench side wall angle can be reliably deformed vertically.
As a result, the mobility that changes with the trench sidewall angle of the trench MOSFET can be stably obtained with good reproducibility, and the process can be simplified even when ion implantation is required at the bottom of the trench, The injection damage to the side wall can be reduced.

FIG. 7 shows a cross-sectional view of the main part of a vertical trench MOSFET according to Example 2 of the present invention. As shown in FIG. 7, an n-type field stopping layer 41, an n-type withstand voltage layer 42, and an n-type current spreading layer 52 are formed on one main surface of an n ⁺ -type 4H—SiC substrate 40 having a {0001} plane as a main surface. And a p-type body layer 45 are sequentially laminated. On the p-type body layer 45, an n ⁺ -type source contact region 48 and a p ⁺ -type body contact region 46 are provided adjacent thereto.
The trench 44 passes through the n ⁺ -type source contact region 48, the p-type body layer 45 and the n-type current spreading layer 52 and reaches the n-type breakdown voltage layer 42. The side wall surface and bottom surface of the trench 44 are covered with a gate oxide film 51. A gate electrode 43 is embedded inside the gate oxide film 51 in the trench 44. The upper side of the gate electrode 43 is covered with an interlayer insulating film 50. The source electrode 47 is in ohmic contact with both the n ⁺ type source contact region 48 and the p ⁺ type body contact region 46. A drain electrode 49 is in ohmic contact with the other main surface of the n ⁺ -type 4H—SiC substrate 40.
The n-type field stopping layer 41 and the n-type current spreading layer 52 may not be provided.
Next, a manufacturing procedure of the device shown in FIG. 7 will be described. First, n having (000-1) _C 8 ° off-plane and (0001) _Si 8 ° off-plane (donor density: 1 × 10 ¹⁸ cm ⁻³ or more, off-direction: [11-20] direction) as main surfaces. ^{A +} type 4H—SiC substrate 40 is prepared.

For example, an n-type field stopping layer 41 (donor density: 0.5 to 10 × 10 ¹⁷ cm ⁻³ ) having a thickness of about 2 μm and an n-type having a thickness of about 10 μm are formed on the n ⁺ -type 4H—SiC substrate 40. Type breakdown voltage layer 42 (donor density: about 1 × 10 ¹⁶ cm ⁻³ ), n-type current spreading layer 52 having a thickness of about 0.4 μm (donor density: about 1 × 10 ¹⁷ cm ⁻³ ) and a thickness of about 2 μm is a p-type body layer 45 (acceptor density: 2 × 10 ¹⁷ cm ^-3) were sequentially epitaxially grown, further p ⁺ -type semiconductor layer which is a p ⁺ -type body contact region 46 is formed thereon (acceptor density: 5 × 10 ¹⁹ cm ^-3 or more) is epitaxially grown to a thickness of about 0.3 [mu] m.
Here, the thickness and doping density of each layer described above are examples, and those values are appropriately designed based on characteristics such as a withstand voltage and a process error to be allowed. In addition, any layer does not need to have a uniform doping density, and the doping density may change along the film forming direction.
Following the epitaxial growth of each layer described above, plasma CVD is performed using TEOS (Tetra Ethyl Oxy Silicate) as a source gas, and SiO ₂ is deposited to a thickness of about 3.5 μm, for example. Next, a photolithography process is performed to form a photoresist mask pattern, and ICP plasma etching using CHF ₃ as a source gas is performed to form a SiO ₂ mask pattern. Then, deposits and photoresist generated during etching of SiO ₂ are removed by O ₂ plasma to form a SiO ₂ mask for ion implantation. After that, for example, thermal oxidation is performed for 30 minutes in a wet atmosphere at 1200 ° C. to form a screen oxide film.

Next, in a state where the sample is heated to, for example, 800 ° C., a box profile having an average density of, for example, 2 × 10 ²⁰ cm ⁻³ is obtained at a depth of, for example, 0.45 μm from the surface of the p ⁺ type epitaxial growth layer. Implant phosphorus. For example, the substrate is held at about 1600 ° C. for 30 minutes in an Ar atmosphere, and the implanted phosphorus is activated to form the n ⁺ -type source contact region 48.
Next, the trench 44 is formed. The etching condition 18 was used as the trench etching condition. That is, the power for generating ICP plasma is 600 W, the RF bias power is 9 W, the etching gas flow rate is 10 sccm for SF ₆ , no O ₂ , Ar is 43 sccm, and the pressure is 2.7 Pa. A trench 44 having a depth of 3.2 μm, a trench width of 3.4 μm, and a trench angle of 88 degrees was formed.
Subsequently, the plasma etching mask made of the SiO ₂ film is removed. Thereafter, a gate oxide film 51 is formed. Subsequent to the formation of the gate oxide film 51, for example, highly doped phosphorus-doped polysilicon is deposited. Then, the gate electrode 43 is formed by removing the polysilicon outside the trench 44 by etching back. Subsequently, an SiO ₂ film is deposited on the entire front surface by a thermal CVD method or the like to form an interlayer insulating film 50.

Next, the front surface is covered with a photoresist and immersed in buffered hydrofluoric acid to remove the oxide film on the back surface. Then, for example, Ni is deposited on the back surface by sputtering. Subsequently, the photoresist on the front surface is removed, and a mask for forming a source contact hole is formed by a photolithography process. Then, a source contact hole is formed in the interlayer insulating film 50 with buffered hydrofluoric acid.
Subsequently, for example, Ni is formed on the front surface by sputtering and patterned. Thereafter, the back electrode and the front surface are simultaneously annealed in, for example, an Ar atmosphere at 1000 ° C. for 30 minutes to form the drain electrode 49 and the source electrode 47.
Next, a mask for forming a gate contact hole is formed by a photolithography process, and the gate contact hole is formed by buffered hydrofluoric acid. For example, when Al is formed on the front surface by sputtering and patterned, and annealed at 450 ° C. for 5 minutes in an Ar atmosphere to form a gate extraction electrode, the vertical direction according to Example 2 of the present invention is applied. A type trench MOSFET is completed.

Cross-sectional view of electron microscope photograph of trench shape when SiC is dry etched Characteristic diagram showing the relationship between the heat treatment pressure and the radius of curvature of the trench corner Characteristic diagram showing the relationship between trench sidewall angle depending on heat treatment temperature and time Cross section of a trench-shaped electron microscope photograph heat-treated at 1700 ° C for 10 minutes Cross section of trench-shaped electron microscope photograph heat-treated at 1700 ° C for 90 minutes Cross section of a trench-shaped electron microscope photograph heat-treated at 1700 ° C for 120 minutes It is principal part sectional drawing of the trench type | mold MOSFET produced using the method concerning this invention. 40 SiC substrate 41 Field stopping layer 42 n-type breakdown voltage layer 43 gate electrode 44 trench 45 p-type body layer 46 p ⁺ -type body contact region 47 source electrode 48 n ⁺ -type source contact region 49 drain electrode 50 interlayer insulating film 51 gate oxidation Film 52 n-type current spreading layer.

Claims (4)

In a method of forming a trench by etching a substrate having a silicon carbide epitaxial film formed on the surface of a silicon carbide single crystal substrate having a {0001} plane as a principal surface or a silicon carbide single crystal substrate , 1700 after forming the trench , A trench is heat-treated in a reduced pressure atmosphere of silane and argon with a flow rate sccm (standard cc / min) ratio of 0.3% to 0.6% with respect to argon for 60 minutes or more in the temperature range of 1 ° C to 1800 ° C. A method for forming a trench in a silicon carbide semiconductor substrate, wherein the side wall angle of the silicon carbide semiconductor substrate is 88 ° or more. 2. The method for forming a trench in a silicon carbide semiconductor substrate according to claim 1, wherein the trench is formed by dry etching. 2. The method for forming a trench in a silicon carbide semiconductor substrate according to claim 1, wherein an atmosphere in the mixed reduced pressure atmosphere is set to 2664.44 Pa to 1.01325 × 10 ⁵ Pa. 3. 2. The method for forming a trench in a silicon carbide semiconductor substrate according to claim 1, wherein the trench has a sidewall orientation of 4H—SiC and is a (1-100) plane.