JP5589907B2 - Semiconductor device, electronic device, and method of manufacturing electronic device - Google Patents

Description

  The present invention relates to a semiconductor device, an electronic device, and an electronic device manufacturing method.

  In order to electrically connect semiconductor devices or to mount a semiconductor device on a circuit board, pads, bumps, and the like that are arranged to face each other are bonded.

  In order to bond the gold bump on the substrate to the bonding pad on the chip, a structure is known in which an intermediate member is formed on the bonding pad on the chip side. The intermediate member is formed of a glass substrate or the like having a tapered step on the inner surface and a through hole in the center.

  In such a structure, the gold bumps on the substrate are passed through the through holes of the intermediate member on the chip and brought into contact with the bonding pads, and further, a heavy load and heat are applied. As a result, the gold bump and the bonding pad are bonded, and the gold bump spreads in the intermediate member. Therefore, the intermediate member is prevented from being displaced due to the horizontal load of the bonded gold bump and bonding pad.

JP 2009-184070 A

  According to the chip structure having the intermediate member as described above, if the gold bump on the substrate is slightly removed from the through hole of the intermediate member on the chip, the gold bump may press the intermediate member to be damaged. Therefore, the gold bump and the intermediate member are required to be aligned with high accuracy.

  Further, when the volume of the gold bump is large, the molten gold bump may overflow from the through hole of the intermediate member and flow laterally. Therefore, it is necessary to form the gold bump volume with high accuracy.

  Furthermore, since heat treatment is required to connect the bonding pads and the bumps, there is a risk of damaging the semiconductor elements and wirings formed in the chip when the heating temperature is high.

  An object of the present invention is to provide a semiconductor device, an electronic device, and a method for manufacturing the electronic device, which can satisfactorily connect opposing bumps, pads, and the like and increase the horizontal strength of the connection portion.

According to one aspect, a first insulating film formed over a semiconductor substrate, a conductive pattern formed in the first insulating film, a second insulating film formed on the first insulating film, , is formed on the second insulating lining, and a via plug that connects to the conductive pattern, formed on the via plug, connected to the via plug, and an electrode pad having an opening, the lower of the electrode pad There is provided a semiconductor device having an internal space formed around the via plug in a second insulating film.
According to another aspect, a first insulating film formed above the first substrate, a conductive pattern formed in the first insulating film, and a second insulating film formed on the first insulating film A via plug formed in the second insulating film and connected to the conductive pattern; an electrode pad formed on the via plug and connected to the via plug and having an opening; and the first electrode under the electrode pad. 2 and the inner space formed in the periphery of the via plug in the insulating film, is formed on one of upper and lower second substrate, and a protruding electrode that be joined to the upper surface and in the opening of the electrode pad An electronic device is provided.
According to another aspect, a step of forming a first insulating film on the first substrate, a step of forming a conductive pattern on the first insulating film, and a second insulating film on the first insulating film Forming a via plug connected to the conductive pattern on the second insulating film; forming an electrode pad connected to the via plug and having an opening; and forming the via plug and the electrode pad. A step of removing the second insulating film under the electrode pad to form an internal space around the via plug ; and a protrusion formed on the electrode substrate on the upper or lower side of the second substrate. There is provided a method of manufacturing an electronic device comprising: a step of facing an electrode-like electrode; and a step of pressing the first substrate and the second substrate toward each other to join the protruding electrode to the electrode pad. .
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

  Since the opening is formed in the electrode pad, when the protruding electrode of another element is pressed and connected to the electrode pad, the protruding electrode can be bonded to the upper surface of the electrode pad and the opening. For this reason, even if the electrode pad and the protruding electrode are misaligned, the protruding electrode remains in the opening, so that the horizontal strength of the connecting portion can be kept high. In addition, it is possible to prevent the protruding electrode from overflowing in the lateral direction by allowing the protruding electrode to enter the opening.

FIG. 1 is a cross-sectional view illustrating an example of a state before connection of first and second semiconductor devices for forming an electronic device according to the first embodiment. FIG. 2 is a perspective sectional view showing an example of an electrode pad of the first semiconductor device included in the electronic device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating an example of the electronic device according to the first embodiment. 4A and 4B are a first plan view and a cross-sectional view illustrating an example of a manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. FIGS. 5A and 5B are a second plan view and a cross-sectional view showing an example of the manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 6A and 6B are a third plan view and a cross-sectional view showing an example of a manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 7A and 7B are a fourth plan view and a cross-sectional view showing an example of the manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 8A and 8B are a fifth plan view and a cross-sectional view showing an example of a manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 9A and 9B are a sixth plan view and a cross-sectional view showing an example of the manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. FIGS. 10A and 10B are a seventh plan view and a cross-sectional view showing an example of a manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 11A and 11B are an eighth plan view and a cross-sectional view illustrating an example of a manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. 12A and 12B are a ninth plan view and a cross-sectional view showing an example of the manufacturing process of the first semiconductor device included in the electronic device according to the first embodiment. FIG. 13 is a cross-sectional view illustrating an example of a state before connection of the first and second semiconductor devices included in the electronic device according to the second embodiment. FIG. 14 is a cross-sectional view illustrating an example of an electronic device according to the second embodiment. FIG. 15 is a cross-sectional view illustrating an example of a state before connection of the first and second semiconductor devices included in the electronic device according to the third embodiment. FIG. 16 is a cross-sectional view illustrating an example of an electronic device according to the third embodiment. 17A and 17B are cross-sectional views illustrating an example of a semiconductor device included in the electronic device according to the fourth embodiment. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device included in an electronic device according to the fifth embodiment.

  Hereinafter, preferred embodiments will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
FIG. 1 is a cross-sectional view illustrating an example of a state before the first and second semiconductor devices included in the electronic device according to the first embodiment are connected to each other.

  The first semiconductor device 1 has a semiconductor substrate, for example, a silicon substrate 2, and an element isolation insulating layer 3 surrounding the P well 4 is formed on the surface of the silicon substrate 2. An n-type MOS transistor 5 is formed in the P well 4 and in the region above it.

  The n-type MOS transistor 5 includes a gate electrode 5g formed on the P-well 4 via a gate insulating film 5a, n-type source / drain regions 5s formed in the silicon substrate 2 on both sides of the gate electrode 5g, 5d. In addition, n-type extension regions 5e and 5f are formed in regions near the gate electrode 5g among the n-type source / drain regions 5s and 5d. An insulating side wall 6 is formed on the side wall of the gate electrode 5g.

  Although one n-type MOS transistor 5 is illustrated in FIG. 1, a plurality of n-type MOS transistors 5 may be formed. Further, a p-type MOS transistor (not shown) and other elements may be formed on the silicon substrate 2 together.

  A first interlayer insulating film 7 is formed on the n-type MOS transistor 5, the element isolation insulating layer 3, and the silicon substrate 2. Further, in the first interlayer insulating film 7, first and second contact plugs 8 and 9 connected to the source / drain regions 5 s and 5 d of the n-type MOS transistor 5 are formed.

  A second interlayer insulating film 11 is formed on the first interlayer insulating film 7. In the second interlayer insulating film 11, first and second wirings 12 and 13 that are individually connected to the first and second contact plugs 8 and 9 are formed. The first and second wirings 12 and 13 have a damascene structure.

  A first metal barrier insulating film 14 and a third interlayer insulating film 15 are sequentially formed on the first and second wirings 12 and 13 and the second interlayer insulating film 11. In the lower part of the third interlayer insulating film 15, first and second via plugs 16, 17 that penetrate the first metal barrier insulating film 14 and are individually connected to the first and second wirings 12, 13. Is formed. Further, third and fourth wirings 18 and 19 connected individually to the first and second via plugs 16 and 17 are formed in the upper portion of the third interlayer insulating film 15. The conductive pattern which is the fourth wiring 19 has a wide area overlapping with an area where an electrode pad 25 described later is formed.

  The first via plug 16 and the third wiring 18 have a dual damascene structure formed integrally. Similarly, the second via plug 17 and the fourth wiring 19 also have a dual damascene structure.

A second metal barrier insulating film 20 and a fourth interlayer insulating film 21 are sequentially formed on the third and fourth wirings 18 and 19 and the third interlayer insulating film 15. A third via plug 22 that penetrates through the second metal barrier insulating film 20 and reaches the third wiring 18 is formed in the lower portion of the fourth interlayer insulating film 21. Furthermore, a fifth wiring 23 connected to the third via plug 22 is formed in the upper part of the fourth interlayer insulating film 21. The third via plug 22 and the fifth wiring 23 have a dual damascene structure.

  Furthermore, a plurality of fourth via plugs 24 that penetrate the second metal barrier insulating layer 20 and reach the fourth wiring 19 are formed in the lower portion of the fourth interlayer insulating film 21. There may be at least one fourth via plug 24. A metal electrode pad 25 connected to the fourth via plug 24 is formed in the upper part of the fourth interlayer insulating film 21. The fourth via plug 24 and the electrode pad 25 have a dual damascene structure formed integrally.

  In the electrode pad 25, as illustrated in FIG. 2, a plurality of matrix-shaped openings 25 a are formed around the fourth via plug 24 so as to penetrate in the vertical direction. Further, a lattice-like internal space 21 a connected to the opening 25 a of the electrode pad 25 is formed below the electrode pad 25 and around the fourth via plug 24. A method for forming the electrode pad 25 and the fourth via plug 24 will be described later. One opening 25a may be formed.

Next, the second semiconductor device 31 will be described.
The second semiconductor device 31 has a semiconductor substrate, for example, a silicon substrate 32. In the silicon substrate 32, an element isolation insulating layer 33 formed on the surface of the silicon substrate 32, for example, a P well 34 surrounded by a silicon oxide layer is formed. An n-type MOS transistor 35 is formed in the P well 34 and in the region above it.

The n-type MOS transistor 35 has a gate electrode 35g formed on the P well 34 via a gate insulating film 35a. The gate electrode 35g is formed by patterning a polysilicon film formed on the gate insulating film 35a. Formed by.

  In the P well 34, n-type extension regions 35e and 35f are formed by impurity ion implantation using the gate electrode 35g as a mask. Furthermore, an insulating sidewall 36 is formed on the side wall of the gate electrode 35g. Further, n-type source / drain regions 35 s and 35 d are formed in the P well 34 by ion implantation using the gate electrode 35 g and the sidewall 36 as a mask.

  In the second semiconductor device 31 illustrated in FIG. 1, one n-type MOS transistor 35 is illustrated, but a plurality of n-type MOS transistors 35 may be formed. Further, a p-type MOS transistor (not shown) and other elements may be formed on the silicon substrate 32.

  On the n-type MOS transistor 35 and the silicon substrate 32, for example, a silicon oxide film is formed as a first interlayer insulating film 37 by a vapor deposition (CVD) method. In the first interlayer insulating film 37, first and second contact plugs 38 and 39 reaching the n-type source / drain regions 35s and 35d of the n-type MOS transistor 35 are formed.

  On the first interlayer insulating film 37, for example, a silicon oxide film is formed as the second interlayer insulating film 41 by the CVD method. In the second interlayer insulating film 41, first and second wirings 42 and 43 that are individually connected to the first and second contact plugs 38 and 39 are formed. Each of the first and second wirings 42 and 43 is formed in a damascene structure having a barrier layer having a laminated structure of titanium and tantalum and a copper main conductor film formed thereon.

  A first metal barrier insulating film 44 and a third interlayer insulating film 45 are sequentially formed on the first and second wirings 42 and 43 and the second interlayer insulating film 41. As the first metal barrier insulating film 44, for example, a silicon nitride film is formed by the CVD method, and as the third interlayer insulating film 45, for example, a silicon oxide film is formed by the CVD method.

  In the lower part of the third interlayer insulating film 45, first and second via holes are formed through the first metal diffusion preventing insulating film 44 and connected to the first and second wirings 42 and 43, respectively. Has been. Furthermore, third and fourth wiring trenches that individually overlap the first and second via holes are formed in the upper portion of the third interlayer insulating film 45.

  A first via plug 46 and a third wiring 48 are formed in the first via hole and the third wiring groove, respectively. The first via plug 46 and the third wiring 48 are formed in a dual damascene structure having a barrier metal layer and a main conductor layer. Similarly, a second via plug 47 and a fourth wiring 49 are formed in the second via hole and the fourth wiring groove, respectively. The second via plug 47 and the fourth wiring 49 have a dual damascene structure. doing. In this case, a laminated structure of titanium and tantalum is formed as the barrier metal layer, and a copper layer, for example, is formed as the main conductor layer.

  A second metal barrier insulating film 50 and a fourth interlayer insulating film 51 are sequentially formed on the third and fourth wirings 48 and 49 and the third interlayer insulating film 45. As the second metal barrier insulating film 50, for example, a silicon nitride film is formed by the CVD method, and as the third interlayer insulating film 45, for example, a silicon oxide film is formed by the CVD method.

In the lower part of the fourth interlayer insulating film 51, third and fourth via holes that penetrate the second metal diffusion preventing insulating film 50 and reach the third and fourth wirings 48 and 49 individually are formed. Has been. Furthermore, fifth and sixth wiring trenches connected to the third and fourth via holes are formed in the upper portion of the fourth interlayer insulating film 51. Third and fourth via plugs 52 and 53 are formed in the third and fourth via holes, respectively, and fifth and sixth wirings are formed in the fifth and sixth wiring grooves, respectively. 54 and 55 are formed.
For example, a silicon nitride film is formed as a cover insulating film 56 on the fifth and sixth wirings 54 and 55 and the fourth interlayer insulating film 51 by a CVD method.

A third via plug 52 and the fifth wiring 54 connected to each other physician, the fourth via plugs 53 and the sixth wiring 55 which are connected to one another each have a dual damascene structure. A laminated structure of titanium and tantalum is formed as the barrier metal layer of the dual damascene structure, and a copper layer, for example, is formed as the main conductor layer.

  A substrate-side via hole 32 a is formed in the silicon substrate 32 and below the second wiring 43. In the first interlayer insulating film 37, a first-layer via hole 37a connected to the substrate-side via hole 32a is formed. An insulating protective film 57 for preventing metal diffusion, such as a silicon nitride film, is formed on the inner peripheral surfaces of the substrate-side via hole 32a and the first-layer via hole 37a.

The substrate-side via hole 32a is formed using, for example, dry etching, wet etching, laser drilling, or the like. The first via hole 37a is formed, for example, by forming the protective insulating film 57 and then etching the first interlayer insulating film 37 through the substrate side hole 32a.

Further, in the substrate-side via hole 32 a and the first- layer via hole 37 a, a protruding electrode 58 surrounded by the insulating protective film 57 is formed so as to protrude below the silicon substrate 32 from the lower surface of the second wiring 43. The protruding electrode 58 has a diameter of, for example, about 5 μm or more and protrudes from the lower surface of the silicon substrate 32 in an amount of, for example, about 1 μm.

The first semiconductor device 1 and the second semiconductor device 31 having the above structure are connected by the following method.

  First, an organic resin such as epoxy or polyimide is applied to the entire upper surface of the first semiconductor device 1 to a thickness of, for example, about 200 nm as the spacer insulating film 28. As a result, the generation of voids between the first semiconductor device 1 and the second semiconductor device 31 is prevented. In this case, an opening is formed on the electrode pad 25 in the spacer insulating film 28.

  Subsequently, the upper surface of the first semiconductor device 1 and the lower surface of the second semiconductor device 31 are made to face each other in a state where the protruding electrode 58 is disposed immediately above the electrode pad 25. Further, when a load is applied by bringing the first semiconductor device 1 and the second semiconductor device 31 close to each other, as illustrated in FIG. 3, the protruding electrode 58 penetrates the spacer insulating film 28, and subsequently illustrated in FIG. It is connected to the electrode pad 25 to be cut and further recessed into the opening 25a. Thereby, the protruding electrode 58 and the electrode pad 25 are joined in the surface direction and the thickness direction of the electrode pad 25. In this case, a good connection can be obtained without heating treatment. Note that heat treatment may be performed.

  Further, when the protruding electrode 58 is bonded to the electrode pad 25, at least the protruding electrode 58 is deformed and enters the opening 25 a of the electrode pad 25. Furthermore, since an excessive load is applied, the protruding electrode 58 can be protruded into the internal space 21a from below the opening 25a, so that it is possible to suppress lateral expansion and protrusion on the upper surface of the electrode pad 25. Can do. Therefore, the volume error of the protruding electrode 58 can be absorbed by the opening 25a and the internal space 21a.

  As described above, even if the alignment between the protruding electrode 58 and the electrode pad 25 is slightly shifted, the protruding electrode 58 enters the opening 25a of the electrode pad 25. Therefore, the connection portion between the electrode pad 25 and the protruding electrode 58 is not affected. The horizontal strength can be increased.

Next, a method for forming the first semiconductor device 1 will be described with reference to FIGS. In each of FIGS. 4 to 12, (a) shows an example of a plane, and (b) shows an example of a side cross section as viewed from line II in (a).
First, steps required until a structure illustrated in FIG. 4 is formed will be described.

  As shown in FIG. 4B, a shallow trench isolation is formed as an element isolation insulating layer 3 by forming an element isolation groove in the element isolation region of the silicon substrate 2 and then embedding a silicon oxide film in the element isolation groove. To do. The element isolation insulating layer 3 may be formed by a LOCOS method. Thereafter, p-type impurity ions such as boron ions are implanted into the element formation region to form the P well 4.

  Thereafter, a gate insulating film 5a and a polysilicon film are sequentially formed on the silicon substrate 2 and the element isolation insulating layer 3 by the CVD method, and then these films are patterned. A silicon film is used as the gate electrode 5g. Further, n-type extension regions 5e and 5f are formed by implanting n-type impurity ions, for example, phosphorus ions, into the P well 4 using the gate electrode 5g and the element isolation insulating layer 3 as a mask.

  Further, for example, a silicon oxide film is formed on the silicon substrate 2 by the CVD method, and this is subjected to anisotropic dry etching in the vertical direction to form the insulating sidewall 6 on the side wall of the gate electrode 5g. Thereafter, n-type impurity ions are implanted into the P well 4 using the gate electrode 5g, the insulating sidewall 6 and the element isolation insulating layer 3 as a mask. Thus, n-type source / drain regions 5s and 5d are formed in the P well 4 on both sides of the gate electrode 5g. Thus, the basic structure of the n-type MOS transistor 5 is formed.

  Thereafter, a silicon oxide film is formed as a first interlayer insulating film 7 on the silicon substrate 2 and the n-type MOS transistor 5 by a plasma vapor deposition (PCVD) method. Further, by patterning the first interlayer insulating film 7, first and second contact holes 7a and 7b reaching the source / drain regions 5s and 5d are formed. Thereafter, for example, a titanium nitride film is formed on the inner surfaces of the first and second contact holes 7a and 7b, and tungsten is embedded in the first and second contact holes 7a and 7b. As a result, first and second contact plugs 8 and 9 are formed in the first and second contact holes 7a and 7b, respectively. In this case, the titanium nitride film and the tungsten film formed on the first interlayer insulating film 7 are removed by, for example, a chemical mechanical polishing (CMP) method.

  Next, for example, a silicon oxide film or the like is formed as the second interlayer insulating film 11 on the first interlayer insulating film 7 by the PCVD method. Subsequently, the second interlayer insulating film 11 is patterned to form first and second wiring grooves 11a and 11b partially overlapping each of the first and second contact plugs 8 and 9, respectively. A barrier metal layer having a laminated structure of tantalum and titanium nitride and a copper main conductor layer are formed in this order in the wiring grooves 11a and 11b. The barrier metal layer and the main conductor layer on the second interlayer insulating film 11 are removed by the CMP method. The barrier metal layer and the main conductor layer left in the first and second wiring grooves 11a and 11b are used as the first and second wirings 12 and 13 having a damascene structure, respectively.

  Next, a first metal barrier insulating film 14 and a third interlayer insulating film 15 are sequentially formed on the first and second wirings 12 and 13 and the second interlayer insulating film 11 by a PCVD method. For example, a silicon nitride film is formed as the first metal barrier insulating film 14 by PCVD. Further, a silicon oxide film is formed as a third interlayer insulating film by a PCVD method.

  The third interlayer insulating film 15 and the first metal barrier insulating film 14 are patterned to form first and second via holes 15a and 15b having a depth reaching the first and second wirings 12 and 13, respectively. Thereafter, third and fourth wiring trenches 15 c and 15 d partially overlapping the first and second via holes 15 a and 15 b are formed on the third interlayer insulating film 15. Subsequently, a barrier metal layer having a laminated structure of tantalum and titanium nitride and a copper main conductor layer are sequentially formed in the first and second via holes 15a and 15b and the third and fourth wiring grooves 15c and 15d.

  Subsequently, the barrier metal layer and the main conductor layer on the third interlayer insulating film 15 are removed by the CMP method. Thereby, the barrier metal layer and the main conductor layer in the first via hole 15a and the third wiring groove 15c are used as the first via plug 16 and the third wiring 18 having a dual damascene structure. Further, the barrier metal layer and the main conductor layer in the second via hole 15 b and the fourth wiring groove 15 d are used as the second via plug 17 and the fourth wiring 19 having a dual damascene structure.

  As shown in FIG. 4A, the fourth wiring 19 has a pad portion 19 a that overlaps with an electrode pad 25 formed in a later process in the same area or more. The pad portion 19a has, for example, a square planar shape with one side of 10 μm or more.

  Next, a second metal barrier insulating film 20 and a fourth interlayer insulating film 21 are sequentially formed on the third and fourth wirings 18 and 19 and the third interlayer insulating film 15. For example, a silicon nitride film is formed as the second metal barrier insulating film 20 by PCVD, and a silicon oxide film is formed as the fourth interlayer insulating film 21 to a thickness of 1450 nm to 1550 nm by PCVD. Further, a silicon nitride film is formed as a base insulating film 29 on the fourth interlayer insulating film 21 to a thickness of 45 nm to 55 nm by the PCVD method.

Next, steps required until a structure shown in FIGS.
First, a first photoresist 61 is applied on the base insulating film 29, and this is exposed and developed to form a third via opening 61a at a position overlapping the third wiring 23, and the fourth via A plurality of fourth via openings 61 b are formed on the pad portion 19 a of the wiring 19. Each of the third and fourth via openings 61a and 61b has a diameter of 350 nm to 450 nm, for example.
In this embodiment, for example, a chemically amplified resist containing an organic polymer, a crosslinking agent, and a photoacid generator is used as the photoresist.

Next, steps required until a structure shown in FIGS.
First, using the first photoresist 61 as a mask, the base insulating film 29 and the fourth interlayer insulating film 21 are etched by plasma etching through the third and fourth via openings 61a and 61b. For example, a gas containing CO, Ar, and C ₄ F ₈ is used as a reactive gas for etching.

As a result, third and fourth via holes 21d and 21e having an opening diameter of 300 nm to 400 nm are formed below the third and fourth via openings 61a and 61b of the first photoresist 61, respectively. Is done. This ensures that the third, fourth via hole 21d, 21e, the third, is formed at a position overlapping a portion of the fourth wiring 18, 19. Subsequently, the remaining first photoresist 61 is removed.

  After that, as shown in FIG. 7B, a second photoresist 62 is applied on the base insulating film 29 and in the third and fourth via holes 21d and 21e, and the second photoresist 62 is exposed and developed. To do. As a result, in the second photoresist 62, a fifth wiring groove opening 62a partially overlapping the third via hole 21d is formed, and as shown in FIGS. A mesh-shaped pad opening 62b is formed in a region including the via hole 21e. The planar outer shape of the pad opening 62b is formed in a quadrangle having a side of 400 nm or more.

  Thus, the upper end of the third via hole 21d embedded in the second photoresist 62 is exposed from the fifth wiring groove opening 62a. Further, in the pad opening 62b of the second photoresist 62, the upper ends of the plurality of fourth via holes 21e embedded in the second photoresist 62 are exposed, and the region sandwiched between the plurality of fourth via holes 21e. In each case, an island resist 62c is formed.

Next , the base insulating film 29 is etched through the fifth wiring groove opening 62a and the pad opening 62b, and further, the fourth interlayer insulating film 21 is etched to an intermediate depth. As a result, as shown in FIGS. 8A and 8B, a fifth wiring groove 21f partially overlapping with the third via hole 21d is formed in the fourth interlayer insulating film 21, and a plurality of second A mesh-shaped pad groove 21g partially overlapping the four via holes 21e is formed. The depth of the fifth wiring groove 21f and the pad groove 21g is, for example, 700 nm to 800 nm from the upper surface.

  In this case, the second metal barrier insulating film 20 is etched through the third and fourth via holes 21d and 21e under the etching conditions in which the second photoresist 62 does not remain, and the third and fourth wirings 18 and 19 are etched. Expose part. Further, the fourth interlayer insulating film 21 and the base insulating film 29 under the island-shaped resist 62c are left as protrusions 21t.

Subsequently, as shown in FIGS. 9A and 9B, the surface of the base insulating film 29 and the fourth interlayer insulating film 21, the third and fourth via holes 21d and 21e, the fifth wiring groove 21f, and the pad. A barrier metal film 63 is formed on the inner surface of the groove 21g to a thickness of 40 nm to 50 nm, for example. As the barrier metal film 63, for example, titanium and tantalum are sequentially formed by sputtering. Subsequently, a copper film 64 is deposited on the barrier metal film 63 by electroplating to 2000 nm to 2500 nm.
The thickness is formed. A thin copper seed layer may be formed on the barrier metal film 63 before the electrolytic plating.

  Next, for example, the silicon substrate 2 is rotated while pressing the upper surface of the copper film 64 against a polishing pad (not shown) to which a slurry containing abrasive grains, a dispersant, and a chelating material is supplied, thereby the copper film 64 and the barrier metal film 63. Then, the base insulating film 29 is polished in order. Thereby, as shown in FIGS. 10A and 10B, the copper film 64, the barrier metal film 63, and the base insulating film 29 are removed from the upper surface of the fourth interlayer insulating film 21. Further, the polishing is continued and the fourth interlayer insulating film 21 is etched from the upper surface to a depth of 45 nm to 55 nm, and the upper surfaces of the fourth interlayer insulating film 21, the copper film 64, and the barrier metal film 63 are planarized.

  As a result, the copper film 64 and the barrier metal film 63 in the third and fourth via holes 21d and 21e become the third and fourth via plugs 22 and 24, respectively, and the copper film 64 in the fifth wiring groove 21f. The barrier metal film 63 is used as the fifth wiring 23. Further, the copper film 64 and the barrier metal film 63 in the pad groove 21 g are used as the electrode pad 25.

  As illustrated in FIG. 2, the planar shape of the electrode pad 25 is a mesh shape, and the upper surfaces of the plurality of island-shaped protrusions 21 t of the fourth interlayer insulating film 21 are exposed from the inside. Each of the copper film 24 and the barrier metal film 23 of the electrode pad 25 is integrated with the fourth via plug 24 to form a dual damascene structure. Similarly, the third via plug 22 and the fifth wiring 23 also have a dual damascene structure.

  Thereafter, as shown in FIGS. 11A and 11B, a protective insulating film 26 made of silicon nitride, silicon carbide, or the like is formed on the fifth wiring 23, the electrode pad 25, and the fourth interlayer insulating film 21. It is formed to a thickness of 65 nm to 75 nm by the PCVD method.

  Thereafter, a third photoresist 66 is applied on the protective insulating film 26, and this is exposed and developed to form an opening 66a on the electrode pad 25. The opening 66 a may be formed narrower than the planar shape of the electrode pad 25 by covering the outer peripheral edge of the electrode pad 25.

  Subsequently, as shown in FIGS. 12A and 12B, the protective insulating film 26 is etched through the opening 66 a of the third photoresist 66 to form the opening 27 exposing the electrode pad 25. For the etching of the protective insulating film 26, for example, a wet etching method using hydrofluoric acid or phosphoric acid, or a plasma etching method using a fluorine-containing gas is used, and the etching selectivity is higher than the copper film of the electrode pad 25. And

  As a result, the plurality of island-shaped protrusions 21t appearing in the electrode pad 25 are also etched to form openings 25a at a plurality of locations, and the fourth interlayer insulating film 21 around the fourth via plug 24 through the openings 25a. Are also etched. Thereby, an internal space 21 a is formed under the electrode pad 25.

  In the case of etching the protective insulating film 26, when selecting a condition in which the etching rate of the fourth interlayer insulating film 21 is slow, the fourth insulating film 26 is formed by using a buffered hydrofluoric acid solution after forming the opening 27 in the protective insulating film 26. The interlayer insulating film 21 is isotropically etched. Thereafter, the third photoresist 65 is removed with a solvent, whereby the first semiconductor device 1 illustrated in FIG. 1 is formed.

(Second Embodiment)
FIG. 13 is a cross-sectional view illustrating an example of a state before the first and second semiconductor devices included in the electronic device according to the second embodiment are connected to each other. In FIG. 13, the same reference numerals as those in FIG. 1 denote the same elements.

  In FIG. 13, the first semiconductor device 1 has the structure shown in the first embodiment, and the second semiconductor device 71 includes the second semiconductor device 31 shown in the first embodiment and an external terminal. Except for this, it has almost the same structure.

  Similar to the first embodiment, a substrate side via hole 32a is formed in the silicon substrate 32 included in the second semiconductor device 71, and a fifth via hole is formed in the first interlayer insulating film 37 on the substrate side via hole 32a. 37a is formed. An insulating protective film 57 for preventing metal diffusion, such as a silicon nitride film, is formed on the inner peripheral surfaces of the fifth via hole 37a and the substrate-side via hole 32a that are formed to overlap each other.

  The substrate-side via hole 32a is formed using, for example, dry etching, wet etching, laser drilling, or the like. The fifth via hole 37a is formed, for example, by anisotropically etching the first interlayer insulating film 37 in the vertical direction through the substrate side hole 32a.

  Further, in the substrate side via hole 32 a and the fifth via hole 37 a, a substrate side via plug 68 surrounded by the insulating protective film 57 is formed so as to reach the back surface of the silicon substrate 32 from the lower surface of the second wiring 43. . For example, the substrate side via plug 68 is formed to have a diameter of about 5 μm or more.

  A surface wiring 66 connected to the lower surface of the substrate side via plug 68 is formed on the lower surface of the silicon substrate 32, and a bump 67, which is a kind of protruding electrode, is bonded on the pad region of the surface wiring 66. . As the bump 67, for example, a metal such as lead, tin, nickel, gold, silver, copper, or an alloy thereof is used.

  When the bump 67 of the second semiconductor device 71 having such a structure is connected to the electrode pad 25 of the first semiconductor device 1, the following method is used.

  First, an organic resin such as epoxy or polyimide is applied to the entire upper surface of the first semiconductor device 1 as a spacer insulating film 28 to a thickness of about 200 nm. An opening for exposing the electrode pad 25 is formed in the spacer insulating film 28. As a result, the generation of voids between the first semiconductor device 1 and the second semiconductor device 71 is prevented.

  Subsequently, in order to position the bump 67 directly above the electrode pad 25, the upper surface of the first semiconductor device 1 and the lower surface of the second semiconductor device 71 are opposed to each other and are aligned via the spacer insulating film 28. Further, when a load is relatively applied from the second semiconductor device 71 toward the first semiconductor device 1, the bump 67 penetrates the spacer insulating film 28 and then the electrode pad 25 as illustrated in FIG. Connect to.

  Thereby, the bump 67 and the electrode pad 25 are joined in the surface direction and the thickness direction of the electrode pad 25. In this case, a good connection can be obtained without heating treatment. Note that heat treatment may be performed.

Further, when the bump 67 sinks into the electrode pad 25, at least the bump 67 is deformed and enters the opening 25 a of the electrode pad 25. Thereby, even if the alignment of the bump 67 and the electrode pad 25 is slightly shifted, the horizontal strength of the bonding between the electrode pad 25 and the bump 67 can be increased. Furthermore, even if a formation error occurs in the volume of the bump 67, the bump 67 enters the opening 25a and the internal space 21a, so that it is possible to eliminate the spread or protrusion on the upper surface of the electrode pad 25 or insufficient bonding.

(Third embodiment)
FIG. 15 is a cross-sectional view illustrating an example of a state before the first and second semiconductor devices included in the electronic device according to the third embodiment are connected to each other. 15, the same reference numerals as those in FIG. 1 denote the same elements.

  In FIG. 15, the first semiconductor device 1 has the same structure as that shown in the first embodiment, and the second semiconductor device 72 includes the second semiconductor device 31 shown in the first embodiment and an external terminal. Except for this, it has almost the same structure. However, the second semiconductor device 72 is described in a state in which the vertical direction is opposite to that in FIG.

  On the fifth and sixth wirings 54 and 55 and the fourth interlayer insulating film 51 of the second semiconductor device 72, for example, a silicon carbide oxide film is formed as the fifth interlayer insulating film 74 by the CVD method. A via plug 75 connected to the sixth wiring 55 is formed in the fifth interlayer insulating film 74. The via plug 75 has a structure in which, for example, a tungsten film is formed on a barrier metal film of titanium or titanium nitride.

  On the fifth interlayer insulating film 74, an aluminum uppermost wiring 76 connected to the upper surface of the via plug 75 is formed. A silicon nitride film is formed as a cover protective film 56 on the uppermost wiring 76 and the fifth interlayer insulating film 74 by the CVD method. Further, an opening that overlaps a part of the uppermost wiring 76 is formed above the via plug 75 in the cover protective film 56. A bump 77 is bonded onto the uppermost wiring 76 through the opening of the cover protective film 56. As the bump 77, for example, a metal such as lead, tin, nickel, gold, silver, or copper is used.

  When the bump 77 of the second semiconductor device 72 having such a structure is connected to the electrode pad 25 of the first semiconductor device 1, the following method is used.

  First, an organic resin such as epoxy or polyimide is applied to the entire upper surface of the first semiconductor device 1 as a spacer insulating film 28 to a thickness of about 200 nm. As a result, the generation of voids between the first semiconductor device 1 and the second semiconductor device 72 is prevented. Further, an opening for exposing the electrode pad 25 is formed in the spacer insulating film 28.

  Subsequently, the upper surface of the first semiconductor device 1 and the upper surface of the second semiconductor device 72 are made to face each other with the bump 77 positioned immediately above the electrode pad 25. Further, when a load is applied in the direction from the second semiconductor device 72 to the first semiconductor device 1, the bump 77 penetrates the spacer insulating film 28 and then the electrode pad 25 as illustrated in FIG. Connect to.

  Thereby, the bump 77 and the electrode pad 25 are joined in the surface direction and the thickness direction of the electrode pad 25. In this case, a good connection can be obtained without heating treatment. Note that heat treatment may be performed.

  Further, when the bump 77 sinks into the electrode pad 25, at least the bump 77 is deformed and enters the opening 25 a of the electrode pad 25. Thereby, even if the alignment of the bump 77 and the electrode pad 25 is slightly shifted, the horizontal strength of the bonding between the electrode pad 25 and the bump 77 can be increased. Furthermore, even if a formation error occurs in the volume of the bump 77, the bump 77 enters the opening 25a and the internal space 21a, so that it is possible to eliminate the spread and protrusion on the upper surface of the electrode pad 25 or insufficient bonding.

(Fourth embodiment)
FIG. 17A is a plan view showing an example of an electrode pad of a semiconductor device used in the electronic device according to the fourth embodiment and its periphery, and FIG. 17B shows the electronic device according to the fourth embodiment. It is an example of the 1st semiconductor device used, Comprising: It is sectional drawing which follows the II line | wire of Fig.17 (a). 17A and 17B, the same reference numerals as those in FIG. 1 denote the same elements.

  In the fourth interlayer insulating film 21 shown in FIGS. 17 (a) and 17 (b), a guard groove 21h having an annular shape is formed around the electrode pad 25 at an interval, and the guard groove 21h is further formed in the guard groove 21h. A guard ring pattern 69 having a damascene structure is formed. The card ring 69, which is an annular metal film, may be formed at multiple positions that extend several times in the lateral direction at intervals around the electrode pad.

  The guard groove 21h is formed simultaneously with the wiring groove 21g in FIG. 8 illustrated in the description of the first embodiment. Furthermore, the barrier metal layer 63 and the main conductor layer 64 illustrated in FIGS. 9 and 10 are embedded in the guard groove 21h, and these layers 63 and 64 are left by CMP to form a guard ring pattern 69.

  As described above, the guard ring pattern 69 is provided around the electrode pad 25 to connect the first semiconductor device 1 and the second semiconductor devices 31, 71, 72 of the above embodiment. The connection projection 58 or the bumps 67 and 77 are pressed. At this time, even if a crack is generated in the fourth interlayer insulating film 21 due to the stress applied to the electrode pad 25, the diffusion of the crack is prevented by the guard ring pattern 69. Therefore, damage to the first semiconductor device 1 can be prevented.

(Fifth embodiment)
FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device used in the electronic device according to the fifth embodiment. In FIG. 18, the same reference numerals as those in FIG. 1 denote the same elements.

  In the fourth interlayer insulating film 21 above the silicon substrate 2, as in the first embodiment, the third via plug 22 and the fifth wiring 23 having a dual damascene structure and the fourth damascene structure having a dual damascene structure are provided. A via plug 24 and an electrode pad 25 are formed.

  A third metal barrier insulating film 80 and a fifth interlayer insulating film 81 are sequentially formed on the fifth and sixth wirings 23 and 25 and the fourth interlayer insulating film 21 by the PCVD method. For example, a silicon nitride film is formed as the third metal barrier insulating film 80, and a silicon oxide film is formed as the fifth interlayer insulating film 81.

  A plurality of fifth via plugs 82 are formed in the lower portion of the fifth interlayer insulating film 81 so as to penetrate the third metal barrier insulating layer 80 and reach the fifth wiring 23. A sixth wiring 83 connected to the fifth via plug 82 is formed on the upper portion of the first wiring plug 82. The fifth via plug 82 is formed at a position overlapping the via plug 24 below the electrode pad 25. The fifth via plug 82 and the sixth wiring 83 have a dual damascene structure, like the third via plug 22 and the fifth wiring 23.

  A sixth via plug 84 that penetrates the third metal barrier insulating layer 80 and reaches the electrode pad 25 is formed in the lower portion of the fifth interlayer insulating film 81, and further, the upper portion in the fifth interlayer insulating film 81 is formed. The upper electrode pad 85 connected to the sixth via plug 84 is formed. The sixth via plug 84 and the upper electrode pad 85 have a dual damascene structure, similar to the fourth via plug 24 and the electrode pad 25 illustrated in FIG.

Further, an opening 85 a penetrating in the vertical direction is formed on a region of the upper electrode pad 85 sandwiched between the plurality of sixth via plugs 84. Further, a lattice-like internal space 81 a connected to the opening 85 a of the upper electrode pad 85 is formed on the electrode pad 25 and around the sixth via plug 84. Note that the guard ring described in the fourth embodiment may also be formed around the upper electrode pad 85.

  In the first semiconductor device 1 in the present embodiment as described above, the upper electrode pad 85 having the same structure or a similar structure is formed on the electrode pad 25 so as to overlap. As a result, the space of the electrode pad region is widened by the openings 25a and 85a and the internal spaces 81a and 21a of the electrode pad 25 and the upper electrode pad 85, so that the capacity for receiving the connection protrusion 58 or the bumps 67 and 77 of the above embodiment. Will increase.

  Similarly to the first to fourth embodiments, when the connection protrusion 58 and the upper electrode pad 85 are joined, the connection protrusion 58 and the like enter the openings 25a and 85a even if a slight deviation occurs. This increases the bonding strength in the horizontal direction. Furthermore, even if the bumps 67 and 77 or the protrusions 58 for connection are large, the protrusion to the side can be prevented by entering the internal spaces 21a and 81a.

  By the way, in each of the above embodiments, the second semiconductor devices 31, 71, 72 have been described as devices connected to the first semiconductor device 1. However, a printed circuit board provided with a protruding electrode on the printed circuit board is referred to as an electrode pad 25, 85 may be joined. In addition, at least one opening 25a, 85a of the electrode pads 25, 85 in each of the above embodiments is sufficient.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, an embodiment is appended.
(Appendix 1) A first insulating film formed above a semiconductor substrate, a conductive pattern formed in the first insulating film, a second insulating film formed on the first insulating film, and the first A via plug formed in the insulating film and connected to the conductive pattern; an electrode pad connected to the via plug and having an opening; and an interior formed around the via plug in the second insulating film. And a semiconductor device.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the via plug and the electrode pad are integrally formed.
(Additional remark 3) The semiconductor device of Additional remark 1 or 2 which has a guard ring formed at intervals around the said electrode pad.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, including a lower electrode pad formed between the electrode pad and the conductive pattern and having an opening.
(Supplementary Note 5) A first insulating film formed above the first substrate, a conductive pattern formed in the first insulating film, and formed above the first insulating film and electrically connected to the conductive pattern And an electrode pad having an opening, and a protruding electrode formed on either the upper side or the lower side of the second substrate and bonded to the upper surface of the electrode pad and the opening.
(Appendix 6) A second insulating film formed on the first insulating film, a via plug formed in the second insulating film and connected to the lower surface side of the electrode pad and the conductive pattern, and the second The electronic device according to appendix 5, further comprising an internal space formed around the via plug in the insulating film.
(Additional remark 7) The electronic device of Additional remark 6 which has a structure where the said protruding electrode penetrates in the said interior space.
(Supplementary note 8) The electronic device according to any one of supplementary notes 5 to 7, wherein the protruding electrode is a bump.
(Supplementary Note 9) A step of causing an electrode pad formed above the first substrate and having an opening to face a protruding electrode formed on either the upper side or the lower side of the second substrate, the first substrate, Pressing the second substrate in a direction approaching each other and bonding the protruding electrode to the electrode pad.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Silicon substrate 5 N-type MOS transistor 8, 9 Contact plug 7, 11, 15, 21 Interlayer insulating film 21a Internal space 14, 20 Metal barrier insulating film 12, 13, 18, 19, 23 Wirings 16, 17, 22, 24 Via plug 25 Electrode pad 25a Opening 31 Semiconductor device 32 Silicon substrate 35 N-type MOS transistor 38, 39 Contact plugs 37, 41, 45, 51, 81 Interlayer insulating films 44, 50, 80 Metal barrier insulating films 42, 43 48, 49, 54, 55, 83 Wiring 46, 47, 52, 53, 82, 84 Via plug 58, 85 Protruding electrode 67, 77 Bump 69 Guard ring pattern

Claims (4)

A first insulating film formed above a semiconductor substrate,
A conductive pattern formed in the first insulating film;
A second insulating film formed on said first insulating film,
It is formed on the second insulating lining, and a via plug that connects to the conductive pattern,
An electrode pad formed on the via plug, connected to the via plug and having an opening;
An internal space formed around the via plug in the second insulating film under the electrode pad ;
A semiconductor device. A first insulating film formed over the first substrate,
A conductive pattern formed in the first insulating film;
A second insulating film formed on the first insulating film;
A via plug formed in the second insulating film and connected to the conductive pattern;
An electrode pad formed on the via plug, connected to the via plug and having an opening;
An internal space formed around the via plug in the second insulating film under the electrode pad;
Is formed in either the upper and lower second substrate, and the projecting electrodes you joined in an upper surface and the opening of the electrode pad,
An electronic device.   The electronic device according to claim 2, wherein the protruding electrode enters the internal space and joins the electrode pad. Forming a first insulating film on the first substrate;
Forming a conductive pattern on the first insulating film;
Forming a second insulating film on the first insulating film;
Forming a via plug connected to the conductive pattern and an electrode pad connected to the via plug and having an opening in the second insulating film;
After the step of forming the via plug and the electrode pad, removing the second insulating film under the electrode pad to form an internal space around the via plug; and
A step of making the electrode pad face a protruding electrode formed on either the upper side or the lower side of the second substrate;
Pressing the first substrate and the second substrate toward each other, and bonding the protruding electrode to the electrode pad; and
Manufacturing method of electronic device having

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