JP5597679B2 - COMMUNICATION SYSTEM, MASTER DEVICE, SLAVE DEVICE, AND CLOCK SIGNAL QUALITY MONITORING METHOD - Google Patents

Description

  The present invention relates to a clock in a synchronous communication network that distributes or receives clock information, which is timing information output from a high-quality clock signal source, among a plurality of node devices, and performs communication by synchronizing communication frequencies. The present invention relates to a means for monitoring normality of information distribution and reception.

  In mobile backhaul, which is a communication network that connects between base stations of mobile communication systems such as 3G (3rd Generation) and 4G (4th Generation) and transfers traffic between base stations or between a base station and a core network It is necessary to synchronize the operating frequencies of the connected base stations with high accuracy. As one of the representative means for realizing this operation frequency synchronization, by distributing clock information from a highly accurate clock signal source to each node device constituting the communication network via the communication network, A network synchronization method for synchronizing the operating frequencies of the node devices is used.

  For example, in the master-slave method (ITU-T G.810 of Non-Patent Document 1) among the network synchronization methods, the master node includes a high-performance clock signal source (PRC: Primary Reference Clock). Then, slave nodes in the network are directly subordinate to and synchronized with the clock information by connecting directly to the master node. Alternatively, the slave nodes in the network are further subordinately synchronized with the clock information by connecting to the master node via a multi-stage node. In this way, clock information can be supplied by following the communication path from the PRC to each node that requires synchronization. Further, in this Master-Slave system, clock quality levels are hierarchically defined according to the number of connection stages from the PRC.

ITU-T G. 810, Definitions and termination for synchronization networks. ITU-T G. 781, Synchronization layer functions. ITU-T G. 704, Synchronous frame structures used at 1544, 6312, 2048, 8448 and 44736 kbit / s hierarchical levels.

  In actual operation of a synchronous communication network, it is necessary to constantly monitor whether the clock information is supplied with the expected quality in order to ensure the continuity of normal communication.

  As a technique for quality control of clock information transmitted in a frequency-synchronous network using the Master-Slave method, ITU-T G. 781 determines the synchronization quality level defined in 781, and each ITU-T G. There is a mechanism for notifying a lower-level node subordinate to each slave device of a synchronization quality level by SSM (Synchronous Status Message) defined in 704.

  However, in this method, in order for the slave device to determine the synchronization quality level, it is necessary to prepare a reference clock signal source having a performance corresponding to the synchronization quality level to be determined separately from the master device side on the slave device side. There is. For example, a method of mounting a high-accuracy clock signal oscillation device for quality determination on the slave device side is conceivable. However, since an oscillation device is generally expensive depending on accuracy, mounting a transmission device in each of a large number of slave devices in the communication network causes a significant increase in the cost of the communication network.

  In addition, ITU-T G.I. The SSM defined by 704 is means for notifying the quality level from the master device side to the slave device side of the clock signal transmitted from the master device side to the slave device side. Then, in order to notify the reception status on the slave device side from the slave device side to the master device side, a control message transmission means in the return direction and the same are realized by using a monitoring control network of the communication network. It is necessary to implement the control function. For this reason, there is a problem that the method of performing quality monitoring using SSM transmission / reception is not suitable for a large-scale synchronous network in which a large number of slave devices exist.

  Therefore, in order to solve the above-described problem, the present invention simplifies the implementation of a large number of slave devices in a communication system that adopts the Master-Slave method, realizes monitoring of synchronization quality while suppressing the device cost, and The object is to realize a technology that does not consume data transfer bandwidth.

  In order to achieve the above object, the slave device receives and extracts the clock information superimposed on the physical signal from the master device, and transmits the return clock information superimposed on the physical signal to the master device. Then, the master device receives and extracts the return clock information superimposed on the physical signal from the slave device, and measures and compares the quality of the transmitted clock information and the quality of the received and extracted return clock information. It is confirmed whether or not the transmitted clock information is normally supplied to the slave device, and whether or not the transmitted clock information is normally extracted in the slave device.

  The present invention includes a master device and a slave device that performs clock synchronization with the master device, wherein the master device generates a master clock signal that is a reference clock signal for clock synchronization, and transmits the master clock signal to the slave The slave device receives the master clock signal from the master device, generates a slave clock signal that is a synchronous clock signal synchronized with the master clock signal, and sends the slave clock signal to the master device. In the communication system, the master device transmits the return signal, the master device receives the slave clock signal from the slave device by return, and measures and compares the quality of the master clock signal and the slave clock signal.

  Further, the present invention provides a master clock signal generation unit that generates a master clock signal that is a reference clock signal for clock synchronization between the own device and a slave device, and the master clock signal generated by the master clock signal generation unit A master clock signal transmission unit that transmits to a slave device, and a slave clock signal reception unit that receives a slave clock signal that is a synchronous clock signal synchronized with the master clock signal transmitted by the master clock signal transmission unit from the slave device by return. And a clock signal quality comparison unit that measures and compares the quality of the master clock signal transmitted by the master clock signal transmission unit and the slave clock signal received by the slave clock signal reception unit in a loopback. Trout It is over apparatus.

  Further, the present invention provides a master clock signal generation step in which the master device generates a master clock signal that is a reference clock signal for clock synchronization when clock synchronization is achieved between the master device and the slave device, and the master device A master clock signal transmission step for transmitting the master clock signal generated in the master clock signal generation step to the slave device, and the slave device transmits the master clock signal transmitted in the master clock signal transmission step to the slave device. A master clock signal receiving step received from a master device; and a slave device that generates a slave clock signal that is a synchronous clock signal synchronized with the master clock signal received in the master clock signal receiving step. A clock signal generation step, a slave clock signal transmission step in which the slave device transmits the slave clock signal generated in the slave clock signal generation step by return to the master device, and the master device transmits the slave clock signal. A slave clock signal receiving step for receiving the slave clock signal transmitted in a loop from the slave device, and a master clock signal and the slave clock signal receiving step transmitted by the master device in the master clock signal transmitting step A clock signal quality monitoring method comprising: a clock signal quality comparison step for measuring and comparing the quality of a slave clock signal received by loopback in order.

  According to this configuration, in a communication system that adopts the Master-Slave system, a technology that simplifies the implementation of a large number of slave devices, realizes monitoring of synchronization quality while suppressing the device cost, and does not consume client data transfer bandwidth Can be realized.

  In the present invention, the master device measures the evaluation index of the quality of the transmitted master clock signal and the slave clock signal received by loopback, and receives the loopback with reference to the quality of the transmitted master clock signal. Measuring the quality degradation index of the slave clock signal, and generating information indicating a quality abnormality of the slave clock signal when it is determined that the quality degradation index generated by the measurement exceeds a threshold of the quality degradation index It is the communication system characterized by this.

  In the present invention, the clock signal quality comparison unit measures an evaluation index of the quality of the master clock signal transmitted by the master clock signal transmission unit and the slave clock signal received by the slave clock signal reception unit in return. Then, using the quality of the master clock signal transmitted by the master clock signal transmission unit as a reference, the slave clock signal reception unit measures a deterioration indicator of the quality of the slave clock signal received in return, and the quality generated by the measurement When it is determined that the deterioration index exceeds the threshold value of the quality deterioration index, the master device generates information indicating a quality abnormality of the slave clock signal.

  According to this configuration, the slave device can be prohibited from transferring the clock signal to the lower device according to the degree of deterioration of the quality of the clock signal during transmission on the communication path and extraction at the slave device. It is possible to prevent the abnormal state of clock synchronization from propagating.

  In the present invention, the master device measures the evaluation index of the quality of the transmitted master clock signal and the slave clock signal received by loopback, and receives the loopback with reference to the quality of the transmitted master clock signal. The slave clock signal quality degradation index is measured, and the slave clock signal quality degradation index received in return is used to determine the slave clock signal quality degradation in the upstream communication path from the slave device to the master device. The communication system is characterized in that when the index is excluded, and it is determined that the quality degradation index generated by the exclusion exceeds the threshold of the quality degradation index, information indicating a quality abnormality of the slave clock signal is generated.

  In the present invention, the clock signal quality comparison unit measures an evaluation index of the quality of the master clock signal transmitted by the master clock signal transmission unit and the slave clock signal received by the slave clock signal reception unit in return. The slave clock signal receiving unit measures the deterioration indicator of the quality of the slave clock signal received by the loop based on the quality of the master clock signal transmitted by the master clock signal transmitting unit, and receives the slave clock signal. The quality degradation index generated by excluding the slave clock signal quality degradation index in the upstream communication path from the slave device to the own device is excluded from the quality degradation index of the slave clock signal received by the unit in a loopback Decided to exceed the threshold of quality degradation index Kiniwa a master unit and generates information indicating a quality abnormality of the slave clock signal.

  According to this configuration, the slave device can be prohibited from transferring the clock signal to the lower device according to the degree of deterioration of the quality of the clock signal during transmission on the communication path and extraction at the slave device. It is possible to prevent the abnormal state of clock synchronization from propagating. In evaluating the quality degradation of the clock signal, the downstream communication path from the master apparatus to the slave apparatus is excluded from the influence of the quality degradation of the clock signal during transmission on the upstream communication path from the slave apparatus to the master apparatus. Only the influence of quality degradation of the clock signal at the time of transmission in the network and at the time of extraction by the slave device can be considered.

  The present invention simplifies the implementation of a large number of slave devices in a communication system that adopts the Master-Slave method, realizes a technique for monitoring the synchronization quality while suppressing the device cost and not consuming the client data transfer bandwidth. can do.

It is a figure which shows the clock signal quality monitoring method of Embodiment 1. FIG. FIG. 10 is a diagram illustrating another clock signal quality monitoring method according to the first embodiment. FIG. 10 is a diagram illustrating another clock signal quality monitoring method according to the first embodiment. FIG. 10 is a diagram illustrating another clock signal quality monitoring method according to the first embodiment. It is a figure which shows the clock signal quality monitoring method of Embodiment 2. It is a figure which shows the other clock signal quality monitoring method of Embodiment 2. FIG. It is a figure which shows the clock signal quality monitoring method of Embodiment 3.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
The first embodiment provides means for confirming in the master device that the clock information supplied from the master device to the slave device is normally supplied to the slave device and that the slave device has been extracted normally. This is realized by returning clock information from the slave device to the master device.

  The clock signal quality monitoring method of the first embodiment is shown in FIG. The communication network according to the first embodiment includes a master device 1, a slave device 2, a downlink communication path 3, and an uplink communication path 4.

  The master device 1 has a function of supplying clock information, which is timing information, to the slave device 2 via the downlink communication path 3, and receives return clock information from the slave device 2 via the uplink communication path 4. And a function of determining the quality level of the return clock information. The master device 1 has a client data transfer function.

  The slave device 2 receives clock information, which is timing information, from the master device 1 via the downlink communication path 3, and sends back clock information to the master device 1 via the uplink communication path 4. The function to supply The slave device 2 has a client data transfer function.

  The master device 1 and the slave device 2 are connected by a downstream communication path 3 and an upstream communication path 4, and through these, clock information and client data can be transmitted and received.

  Note that client data may be transferred together with clock information as physical signals in the downlink communication path 3 and the uplink communication path 4. Further, at the timing when the client data is not transferred, only the clock information may be transferred as a physical signal in the downlink communication path 3 and the uplink communication path 4 by superimposing clock information on the physical signal in the idle state.

  Further, as the downlink communication path 3 and the uplink communication path 4, an optical fiber, a twisted pair cable, a coaxial cable, radio, or the like can be used, and a specific frequency channel and a polarization channel (optical fiber) in these communication paths. In the case of).

  The master device 1 includes a control function unit 11, a receiver 12, a transmitter 13, a receiver 14, a transmitter 15, a clock signal source 16, a clock extraction function unit 17, and a clock quality determination unit 18.

  The control function unit 11 is a function unit that controls each function unit of the master device 1. The receiver 12 is a functional unit that receives a physical signal on which client data is superimposed from a higher-level device via a communication path. The transmitter 13 is a functional unit that transmits a physical signal on which the client data and the clock information supplied from the clock signal source 16 are superimposed via the downstream communication path 3 to the slave device 2. The receiver 14 is a functional unit that receives a physical signal on which the clock information supplied from the client data and the synchronization functional unit 27 is superimposed via the upstream communication path 4 from the slave device 2. The transmitter 15 is a functional unit that transmits a physical signal on which client data is superimposed to a higher-level device via a communication path.

  The clock signal source 16 is a source of clock information supplied to the slave device 2. The clock extraction function unit 17 is a function unit that extracts clock information from the physical signal received by the receiver 14. The clock quality determination unit 18 uses the index specified by the control function unit 11 to compare and determine the quality of the clock information transmitted and received by the transmitter 13 and the receiver 14, and notifies the control function unit 11 and the like of the determination result Part.

  The slave device 2 includes a control function unit 21, a receiver 22, a transmitter 23, a receiver 24, a transmitter 25, a clock extraction function unit 26, and a synchronization function unit 27.

  The control function unit 21 is a function unit that controls each function unit of the slave device 2. The receiver 22 is a functional unit that receives the physical signal on which the client data and the clock information supplied from the clock signal source 16 are superimposed via the downlink communication path 3 from the master device 1. The transmitter 23 is a functional unit that transmits a physical signal on which the client data and the clock information supplied from the synchronization functional unit 27 are superimposed to a lower-level device via a communication path. The receiver 24 is a functional unit that receives a physical signal on which client data is superimposed from a lower-level device via a communication path. The transmitter 25 is a functional unit that transmits a physical signal on which the client data and the clock information supplied from the synchronization functional unit 27 are superimposed to the master device 1 via the upstream communication path 4.

  The clock extraction function unit 26 is a function unit that extracts clock information from the physical signal received by the receiver 22. The synchronization function unit 27 is a function unit that generates clock information synchronized with the clock information extracted by the clock extraction function unit 26.

  In the master device 1, the clock signal source 16 supplies clock information to the transmitter 13 and the clock quality determination unit 18. The clock information supplied to the transmitter 13 is returned to the master device 1 via the slave device 2 through the following path.

1) The transmitter 13 of the master device 1 superimposes the clock information supplied from the clock signal source 16 on the physical signal transmitted to the downlink communication path 3.
2) In the receiver 22 of the slave device 2, the physical signal on which the clock information supplied from the clock signal source 16 is superimposed is received from the downlink communication path 3.
3) The clock extraction function unit 26 of the slave device 2 extracts clock information from the physical signal on which the clock information supplied from the clock signal source 16 is superimposed.
4) The synchronization function unit 27 of the slave device 2 generates clock information synchronized with the clock information supplied from the clock extraction function unit 26.
5) The transmitter 25 of the slave device 2 superimposes the clock information supplied from the synchronization function unit 27 on the physical signal transmitted to the upstream communication path 4.
6) The receiver 14 of the master device 1 receives the physical signal on which the clock information supplied from the synchronization function unit 27 is superimposed from the upstream communication path 4.
7) The clock extraction function unit 17 of the master device 1 extracts clock information from the physical signal on which the clock information supplied from the synchronization function unit 27 is superimposed.
8) The clock quality determination unit 18 of the master device 1 performs quality determination on the clock information supplied from the clock extraction function unit 17.

  In the master device 1, the clock quality determination unit 18 sets a monitoring function corresponding to the quality evaluation index to be applied by the control function unit 11 before starting the quality monitoring. The clock quality determination unit 18 compares the clock information supplied from the clock signal source 16 and the clock extraction function unit 1 using the quality evaluation index set by the control function unit 11. When the clock quality determination unit 18 determines that the quality evaluation index difference (that is, the quality degradation index) exceeds the quality evaluation index difference threshold (that is, the quality degradation index threshold), the slave device 2 extracts and outputs Information indicating the quality abnormality of the clock signal is notified to the control function unit 11 and the like.

  The quality degradation of the clock information occurs due to the following factors. As a first factor, there is quality degradation caused by the downlink communication path 3 and the uplink communication path 4. For example, when transmitting via an optical communication path, there are chromatic dispersion, polarization dispersion, and phase fluctuation accompanying environmental temperature change. As a second factor, there is quality degradation caused by the synchronization performance of the synchronization function unit 27 of the slave device 2.

  The quality degradation index of the clock information measured in the first embodiment takes into account quality degradation due to the synchronization performance of the downlink communication path 3, the looped uplink communication path 4, and the synchronization function unit 27 of the slave device 2. However, the quality degradation index of the clock information that should be measured inherently should take into account the quality degradation due to the synchronization performance of the synchronization function unit 27 of the downstream communication path 3 and the slave device 2, and return uplink communication Quality degradation due to the path 4 should not be considered.

  Therefore, as a modification of the first embodiment, the clock quality determination unit 18 uses the quality evaluation index set by the control function unit 11 for the clock information supplied from the clock signal source 16 and the clock extraction function unit 17. In comparison, the quality degradation index (that is, the surplus quality degradation index) caused by the uplink communication path 4 may be subtracted from the difference between the quality evaluation indices (that is, the virtual quality degradation index). As a modification of the first embodiment, the clock quality determination unit 18 determines that the subtraction value of the quality evaluation index (that is, the original quality deterioration index) is the threshold value of the subtraction value of the quality evaluation index (that is, the original quality deterioration index When it is determined that the threshold value) is exceeded, information indicating the quality abnormality of the clock signal extracted and output by the slave device 2 may be notified to the control function unit 11 or the like.

  Further, as shown in FIGS. 2 and 3, in the master device 1, instead of mounting the clock signal source 16, a synchronization function unit 19 that can be synchronized with clock information supplied from another device may be mounted. Thus, clock information synchronized with the external clock can be generated.

  Another clock signal quality monitoring method of the first embodiment is shown in FIG. The master device 1 includes a synchronization function unit 19 and receives supply of clock information from the external clock signal source 5. The synchronization function unit 19 generates clock information synchronized with the clock information supplied from the external clock signal source 5, and the clock quality determination unit 18 inputs the clock information supplied from the external clock signal source 5. The processing method after the clock information is supplied to the transmitter 13 is the same as in FIG.

  Another clock signal quality monitoring method of the first embodiment is shown in FIG. The master device 1 includes a synchronization function unit 19 and receives supply of clock information from a host device. The synchronization function unit 19 generates clock information synchronized with the clock information supplied from the host device, and the clock quality determination unit 18 inputs the clock information supplied from the synchronization function unit 19. The processing method after the clock information is supplied to the transmitter 13 is the same as in FIG.

  FIG. 4 shows another clock signal quality monitoring method according to the first embodiment. The master device 1 includes a synchronization function unit 19 and generates clock information with an internal clock signal source 20. The synchronization function unit 19 generates clock information synchronized with the clock information supplied from the internal clock signal source 20, and the clock quality determination unit 18 inputs the clock information supplied from the internal clock signal source 20. The processing method after the clock information is supplied to the transmitter 13 is the same as in FIG.

  The master device 1 includes the synchronization function unit 19 and includes all of the clock signal supplies shown in FIGS. 2 to 4, and is used from the external clock signal source 5, the host device, and the internal clock signal source 20. A clock signal source can also be selected.

  Embodiment 1 has the following effects. As a first effect, the quality monitoring function of a large-scale frequency synchronization network can be realized with a low-cost apparatus configuration. As a second effect, the quality of the clock information can be monitored without consuming the user's bandwidth. As a third effect, even when a device that requires quality determination (for example, the slave device 2) does not have a reliable reference for quality comparison, another device (for example, a master that has a reliable reference for quality comparison). In the device 1), the quality of the clock information supplied to the desired device (for example, the slave device 2) can be determined. As a fourth effect, in a specific location (communication equipment building, etc.) equipped with a highly reliable clock as an existing equipment for the purpose of other communication services, etc., the quality of the clock information is judged by effectively utilizing the existing equipment. Can do.

(Embodiment 2)
In the second embodiment, the master device includes a PLL (Phase Lock Loop) circuit as a synchronization function unit, and is an SNI- that is a connection interface for data transmission / reception with an external clock signal source, an internal clock signal source, or another device. It synchronizes with the clock information extracted from the IF (Service Network Interface). Further, Ethernet (registered trademark) is applied to communication of physical signals and data signals.

  FIG. 5 shows a clock signal quality monitoring method according to the second embodiment. The communication network according to the second embodiment includes a terminal station device 6, a control package 61 of the terminal device 6, a termination device 7, a control package 71 of the termination device 7, an optical fiber 8, an external clock signal source 9, and an OSS 10.

  The master device is realized by the terminal device 6 and the control package 61. The slave device is realized by the termination device 7 and the control package 71. The control packages 61 and 71 of the terminal station device 6 and the terminal device 7 are connected by an optical fiber 8. In addition, the control packages 61 and 71 of the terminal station device 6 and the terminal device 7 are connected by a control link via an upper operation support system (OSS) 10 capable of exchanging control messages.

  In addition, depending on the type of SNI-IF, optical service unit interface (OSU-IF) described later, optical network unit interface (ONU-IF) described later, and optical network interface (UNI-IF) 8 described later according to the type of fiber. Instead, a twisted pair cable may be used as the communication path. Further, as the optical fiber 8, another fiber may be used in both directions, or the same fiber may be used in both directions (that is, single-core communication may be used).

  The terminal device 6 includes an SNI-IF 62, an OSU-IF 63, PHY termination units 64 and 65, a logic circuit 66, an oscillator 67, and a PLL circuit 68.

  The SNI-IF 62 is an IF function unit for connecting to another node device, and is connected to an optical fiber. It realizes a physical termination function, a transmitter function, and a receiver function of an Ethernet (registered trademark) physical signal, and is mounted for each connection destination. For example, pluggable transceivers such as MSA standards such as SFP, XFP, SFP +, CFP, and QSFP can be used.

  The OSU-IF 63 is an IF function unit for connecting to the termination device 7, and is connected to the optical fiber 8. It realizes a physical termination function, a transmitter function, and a receiver function of an Ethernet (registered trademark) physical signal, and is mounted for each connection destination. For example, pluggable transceivers such as MSA standards such as SFP, XFP, SFP +, CFP, and QSFP can be used.

  The PHY termination units 64 and 65 are device units that realize a logical termination function of an Ethernet (registered trademark) signal transmitted through a communication path, and have a transmitter function and a receiver function. It is realized by an IC (Integrated Circuit) that realizes an Ethernet (registered trademark) PHY function defined by IEEE 802.3. It is mounted for each optical fiber route to be connected. In the PHY terminator 65 mounted on the path on the terminal device 7 side, the clock information supplied from the PLL circuit 68 is superimposed on the transmission signal, and the clock is generated from the Ethernet (registered trademark) signal received from the terminal device 7. Extract information.

  The logic circuit 66 is a logic circuit that implements a logic that compares a plurality of clock information and determines a difference in quality according to an index specified by the control package 61. This is realized by an FPGA (Field Programmable Gate Array) or the like. Clock information supplied from the PHY terminator 65 connected to the terminator 7 and clock information supplied from the external clock signal source 9 are input.

  The oscillator 67 is an oscillator such as a TCXO (Temperature Compensated Crystal Oscillator) or an OCXO (Oven Controlled Crystal Oscillator).

  The PLL circuit 68 is a circuit unit that outputs timing information (clock information) synchronized with input timing information (clock information). An input unit for inputting timing information (clock information) from the oscillator 67 or the external clock signal source 9 is provided, and a supply source clock signal source to be synchronized can be selected from the oscillator 67 and the external clock signal source 9. .

  The control package 61 is a functional unit that includes a CPU (Central Processing Unit) and a storage device, and controls the terminal station device 6 using installed software. An evaluation index for determining the deterioration state of the clock information returned from the termination device 7 is set for the logic circuit 66. In the case where quality is continuously measured over time, an observation time interval is set for the logic circuit 66. In addition, it has a function of generating a control message and also has a function of transmitting a control message to another node through a communication path.

  The termination device 7 includes an ONU-IF 72, a UNI-IF 73, PHY termination units 74 and 75, a logic circuit 76, and a PLL circuit 77.

  The ONU-IF 72 is an IF function unit for connecting to the terminal device 6, and is connected to the optical fiber 8. It realizes a physical termination function, a transmitter function, and a receiver function of an Ethernet (registered trademark) physical signal, and is mounted for each connection destination. For example, pluggable transceivers such as MSA standards such as SFP, XFP, SFP +, CFP, and QSFP can be used.

  The UNI-IF 73 is an IF function unit for connecting to a lower apparatus, and is connected to an optical fiber. It realizes a physical termination function, a transmitter function, and a receiver function of an Ethernet (registered trademark) physical signal, and is mounted for each connection destination. For example, pluggable transceivers such as MSA standards such as SFP, XFP, SFP +, CFP, and QSFP can be used.

  The PHY termination units 74 and 75 are device units that realize a logical termination function of an Ethernet (registered trademark) signal transmitted through a communication path, and have a transmitter function and a receiver function. It is realized by an IC that realizes the Ethernet (registered trademark) PHY standard defined in IEEE 802.3. It is mounted for each optical fiber route to be connected. In the PHY termination unit 74 mounted on the route on the terminal station device 6 side, clock information is extracted from the Ethernet (registered trademark) signal received from the terminal device 6 and supplied from the PLL circuit 77. Is superimposed on the transmission signal.

  The logic circuit 76 is a functional unit that manages and controls the device of the termination device 7 according to the index specified by the control package 71. This is realized by an FPGA or the like.

  The PLL circuit 77 is a circuit unit that outputs timing information (clock information) synchronized with input timing information (clock information). Timing information (clock information) synchronized with the timing information (clock information) supplied from the PHY termination unit 74 is generated, and the generated timing information (clock information) is supplied to the PHY termination unit 74.

  The control package 71 includes a CPU and a storage device, and is a functional unit that controls the termination device 7 using installed software. It is determined whether or not to transfer the clock information received from the terminal device 6 side to the UNI-IF 73 side, triggered by reception of a message from another device. When the clock quality abnormality notification from the terminal device 6 side is received via the host OSS 10, the clock information received from the terminal device 6 side is not transferred to the UNI-IF 73 side.

  The clock information is returned to the terminal device 6 via the terminal device 7 through the following path.

1) The PLL circuit 68 of the terminal station device 6 generates clock information synchronized with the external reference clock supplied from the external clock signal source 9.
2) In the PHY terminator 65 of the terminal device 6, the physical signal on which the clock information supplied from the PLL circuit 68 is superimposed is transmitted to the ONU-IF 72 of the terminator 7 via the OSU-IF 63 and the optical fiber 8. To do. At this time, logical data such as an Ethernet (registered trademark) frame may be transmitted together with the clock information.
3) The PHY termination unit 74 of the termination device 7 extracts clock information supplied from the PLL circuit 68 from the physical signal input from the ONU-IF 72.
4) In the PLL circuit 77 of the termination device 7, clock information synchronized with the clock information supplied from the PHY termination unit 74 is generated.
5) In the PHY termination unit 74 of the termination device 7, the physical signal on which the clock information supplied from the PLL circuit 77 is superimposed is transmitted to the OSU-IF 63 of the terminal station device 6 via the ONU-IF 72 and the optical fiber 8. To do. At this time, logical data such as an Ethernet (registered trademark) frame may be transmitted together with the clock information.
6) In the PHY termination unit 65 of the terminal device 6, the clock information supplied from the PLL circuit 77 is extracted from the physical signal input from the OSU-IF 63.
7) The logic circuit 66 of the terminal device 6 performs quality judgment on the clock information supplied from the PHY termination unit 65.

  Based on the setting by the OSS 10, the control package 61 uses, for example, wander, jitter, or the like as a quality evaluation index for the clock information supplied from the PHY termination unit 65, based on the clock information supplied from the external clock signal source 9. The following quality evaluation indexes 1) to 6) related to the frequency are designated. The control package 61 also designates the quality evaluation index observation time and the quality degradation index threshold value for determining whether to output a clock quality abnormality notification based on the setting by the OSS 10.

1) Time Interval Error (TIE)
2) Allan Deviation (ADEV)
3) Modified Allan Deviation (MDEV)
4) Time Deviation (TDEV)
5) Maximum Time Interval Error (MTIE)
6) Fractional Frequency Offset (FFO)

  Here, the control package 61 is based on the dispersion characteristic of the optical fiber 8 connecting the terminal station device 6 and the terminal device 7 and the error characteristic of the PLL circuit 77 mounted on the terminal device 7 based on the setting by the OSS 10. It is also possible to set an expected quality deterioration value unique to the communication system. And the control package 61 can also set the threshold value of the quality degradation index | exponent from which the quality degradation expectation value peculiar to the communication system was deducted beforehand based on the setting by OSS10. In addition, the control package 61 receives a notification of quality abnormality of the return clock information from the logic circuit 66 and notifies the OSS 10 via the control link.

  As an example, a case where the above-mentioned 6) FFO is designated as a quality evaluation index will be described. The OSS 10 designates FFO as a quality evaluation index, designates 1 second as an observation time, and designates 3 ppm as a threshold value in the control package 61 by a control message. The control package 61 causes the logic circuit 66 to measure the FFO as a quality evaluation index for the clock information returned from the termination device 7.

  The logic circuit 66 measures the frequency f0 based on the clock information supplied from the external clock signal source 9, measures the frequency f1 based on the clock information returned from the termination device 7, and sets the FFO as the quality evaluation index to | f0. -F1 | / f0 is calculated.

  Then, the logic circuit 66 measures the frequencies f0 and f1 for one second, which is the designated observation time, and determines that the FFO as the quality evaluation index has exceeded the designated threshold value of 3 ppm, the control package 61 To that effect.

  However, when 0.5 ppm is set as the expected value of the FFO unique to the communication system, the logic circuit 66 determines that the FFO as the quality evaluation index has exceeded the threshold value of 3.5 ppm before subtraction. When this happens, the control package 61 is notified to that effect.

  As another example, a case where the above-described 5) MTIE is specified as a quality evaluation index will be described. The OSS 10 designates MTIE as the quality evaluation index, 30 seconds as the observation time, and wander tolerance (ITU-T G.812) as the threshold value in the control package 61 by the control message. The control package 61 causes the logic circuit 66 to measure MTIE as a quality evaluation index for the clock information returned from the termination device 7. When the logic circuit 66 measures the MTIE for the designated observation time of 30 seconds and determines that the MTIE as the quality evaluation index exceeds the designated wander tolerance, which is the designated threshold value, the logic circuit 66 informs the control package 61 to that effect. Notification of. It should be noted that a plurality of the above-mentioned indices 1) to 6) can be specified simultaneously as quality evaluation indices.

  The control package 61 is capable of generating a control message including the result of the quality determination, and has an interface for notifying other nodes through the control link. A control message including an abnormal result of the quality determination is notified to another device such as the termination device 7 through a management device such as the OSS 10 or a control monitoring network, so that the device control according to the abnormal state of the clock information is performed. This is possible in other devices such as 7. For example, even if the terminal device 7 receives the clock information supplied from the terminal device 6 from the terminal device 6 in the ONU-IF 72, the terminal device 7 does not transmit it to the other device in the UNI-IF 73. Prevent propagation to

  FIG. 6 shows another clock signal quality monitoring method according to the second embodiment. The PHY terminator 64 connected to the host device extracts clock information from the physical signal received by the SNI-IF 62. The PLL circuit 68 generates clock information synchronized with the clock information extracted by the PHY termination unit 64. The PHY terminator 65 connected to the terminator 7 superimposes the clock information generated by the PLL circuit 68 on the physical signal. The processing method after the physical signal on which the clock information is superimposed is supplied to the OSU-IF 63 is the same as in FIG.

(Embodiment 3)
In the third embodiment, as shown in FIG. 7, the terminal device 6 is provided with communication packages 6-1, 6-2,... ,..., 7-N, and in the control package 61 common to the communication packages 6-1, 6-2,..., 6-N, the PLL circuit 611, the clock distribution function unit 612, and the logic circuit 613 is implemented.

  In the first and second embodiments, each line individually acquires a reference clock. In the third embodiment, the PLL circuit 611 of the control package 61 acquires a reference clock as a representative, and each line shares the output of the PLL circuit 611 of the control package 61.

  In the first and second embodiments, each line owns a logic circuit for quality determination. In the third embodiment, each line shares a logic circuit for quality determination. In this way, by sharing the functional unit with a plurality of lines, it is possible to reduce the system cost when providing a plurality of lines.

  The logic circuit 613 of the control package 61 inputs the clock information supplied from the external clock signal source 9 and also transmits the communication packages 6-1 from the termination devices 7-1, 7-2,..., 7-N. , 6-2,..., 6-N are input.

  The storage device (not shown) of the control package 61 stores the clock information returned by each line in association with the identifiers of the communication packages 6-1, 6-2,. ing. The logic circuit 613 of the control package 61 compares the clock information returned from each line with the clock information supplied from the external clock signal source 9, and performs quality determination.

  The OSS 10 sets a threshold value for a quality evaluation index and a quality deterioration index for each line. The logic circuit 613 of the control package 61 monitors the quality of the clock information for each line.

  In the following description, the configuration and processing will be described for a line including the communication package 6-M and the termination device 7-M, where M is an integer from 1 to N.

  The communication package 6-M includes an SNI-IF 62-M, an OSU-IF 63-M, a PHY termination unit 64-M, 65-M, and a logic circuit 66-M.

  The termination device 7-M includes an ONU-IF 72-M, a UNI-IF 73-M, a PHY termination unit 74-M, 75-M, a logic circuit 76-M, and a PLL circuit 77-M.

  The communication package 6-M and the termination device 7-M are connected via an optical fiber 8-M.

  The clock information is returned to the communication packages 6-1, 6-2,..., 6-N via the terminating devices 7-1, 7-2,. It is.

1) In the PLL circuit 611 of the control package 61, clock information synchronized with the external reference clock supplied from the external clock signal source 9 is generated.
2) The clock distribution function unit 612 of the control package 61 distributes the clock information supplied from the PLL circuit 611 to the PHY termination unit 65-M of the communication package 6-M.
3) In the PHY termination unit 65-M of the communication package 6-M, the physical signal on which the clock information supplied from the PLL circuit 611 is superimposed is transmitted to the termination device via the OSU-IF 63-M and the optical fiber 8-M. Send to 7-M ONU-IF72-M.
4) In the PHY termination unit 74-M of the termination device 7-M, the clock information supplied from the PLL circuit 611 is extracted from the physical signal input from the ONU-IF 72-1.
5) In the PLL circuit 77-M of the termination device 7-M, clock information synchronized with the clock information supplied from the PHY termination unit 74-M is generated.
6) In the PHY termination unit 74-M of the termination device 7-M, the physical signal on which the clock information supplied from the PLL circuit 77-M is superimposed is transmitted via the ONU-IF 72-M and the optical fiber 8-M. It transmits to OSU-IF63-M of communication package 6-M.
7) In the PHY termination unit 65-M of the communication package 6-M, the clock information supplied from the PLL circuit 77-M is extracted from the physical signal input from the OSU-IF 63-M, and the logic circuit of the control package 61 To 613.
8) The logic circuit 613 of the control package 61 performs quality determination on the clock information supplied from the PHY termination unit 65-M.

  The quality monitoring of the clock information is performed in the same manner as in the first and second embodiments, even in the third embodiment, except that it is performed based on the quality evaluation index for each line and the threshold value of the quality degradation index.

  The communication system, the master device, the slave device, and the clock signal quality monitoring method according to the present invention simplify the implementation of a large number of slave devices in a large-scale frequency synchronization network adopting the Master-Slave method, and suppress the device cost. Thus, the synchronization quality can be monitored, and a technology that does not consume the client data transfer bandwidth can be realized.

1: Master device 11: Control function unit 12: Receiver 13: Transmitter 14: Receiver 15: Transmitter 16: Clock signal source 17: Clock extraction function unit 18: Clock quality determination unit 19: Synchronization function unit 20: Internal clock signal source 2 : Slave device 21: Control function section 22: Receiver 23: Transmitter 24: Receiver 25: Transmitter 26: Clock extraction function section 27: Synchronization function section 3: Downlink communication path 4: Uplink communication path 5: External clock signal source 6: End Station devices 6-1, 6-2, 6-N: communication package 61: control packages 62, 62-1, 62-2, 62-N: SNI-IF
63, 63-1, 63-2, 63-N: OSU-IF
64, 64-1, 64-2, 64-N: PHY termination units 65, 65-1, 65-2, 65-N: PHY termination units 66, 66-1, 66-2, 66-N: logic circuits 67: Oscillator 68: PLL circuit 611: PLL circuit 612: Clock distribution function unit 613: Logic circuits 7, 7-1, 7-2, 7-N: Termination device 71: Control packages 72, 72-1, 72-2 , 72-N: ONU-IF
73, 73-1, 73-2, 73-N: UNI-IF
74, 74-1, 74-2, 74-N: PHY terminators 75, 75-1, 75-2, 75-N: PHY terminators 76, 76-1, 76-2, 76-N: logic circuits 77, 77-1, 77-2, 77-N: PLL circuits 8, 8-1, 8-2, 8-N: optical fiber 9: external clock signal source 10: OSS

Claims (7)

A master device, and a slave device for clock synchronization with the master device,
The master device generates a master clock signal that is a reference clock signal for clock synchronization, transmits the master clock signal to the slave device,
The slave device receives the master clock signal from the master device, generates a slave clock signal that is a synchronous clock signal synchronized with the master clock signal, transmits the slave clock signal to the master device in a loopback,
The master device receives the slave clock signal by return from the slave device, and measures and compares the quality of the master clock signal and the slave clock signal. The master device measures the evaluation index of the quality of the transmitted master clock signal and the slave clock signal received by loopback, and uses the quality of the transmitted master clock signal as a reference for the slave clock signal received by loopback. The quality degradation index is measured, and when it is determined that the quality degradation index generated by the measurement exceeds a threshold of the quality degradation index, information indicating a quality abnormality of the slave clock signal is generated. The communication system according to 1. The master device measures the evaluation index of the quality of the transmitted master clock signal and the slave clock signal received by loopback, and uses the quality of the transmitted master clock signal as a reference for the slave clock signal received by loopback. Measure the quality degradation index and exclude the slave clock signal quality degradation index in the upstream communication path from the slave device to the master device from the quality degradation index of the slave clock signal received in return 2. The communication system according to claim 1, wherein when it is determined that the quality degradation index generated by the step exceeds a threshold of the quality degradation index, information indicating a quality abnormality of the slave clock signal is generated. A master clock signal generation unit that generates a master clock signal that is a reference clock signal for clock synchronization between the own device and the slave device;
A master clock signal transmitter that transmits the master clock signal generated by the master clock signal generator to the slave device;
A slave clock signal receiving unit for receiving a slave clock signal that is a synchronous clock signal synchronized with the master clock signal transmitted by the master clock signal transmitting unit from the slave device;
A clock signal quality comparison unit that measures and compares the quality of the master clock signal transmitted by the master clock signal transmission unit and the slave clock signal received by the slave clock signal reception unit in a loopback;
A master device comprising: The clock signal quality comparison unit measures an evaluation index of the quality of the master clock signal transmitted from the master clock signal transmission unit and the quality of the slave clock signal received by the slave clock signal reception unit, and the master clock signal Based on the quality of the master clock signal transmitted by the transmission unit, the slave clock signal reception unit measures the quality degradation index of the slave clock signal received in return, and the quality degradation index generated by the measurement is the quality 5. The master device according to claim 4, wherein when it is determined that a deterioration index threshold is exceeded, information indicating an abnormality in quality of the slave clock signal is generated. The clock signal quality comparison unit measures an evaluation index of the quality of the master clock signal transmitted from the master clock signal transmission unit and the quality of the slave clock signal received by the slave clock signal reception unit, and the master clock signal Based on the quality of the master clock signal transmitted by the transmission unit, the slave clock signal reception unit measures the deterioration index of the quality of the slave clock signal received by the return, and the slave clock signal reception unit receives the return by the return From the degradation index of the quality of the slave clock signal, the degradation index of the quality of the slave clock signal in the upstream communication path from the slave device to its own device is excluded, and the quality degradation index generated by the exclusion is the quality degradation index. When it is determined that the threshold is exceeded, the scan The master device of claim 4, characterized in that to generate the information indicating the quality abnormality Bukurokku signal. When synchronizing the clock between the master device and the slave device,
A master clock signal generating step in which the master device generates a master clock signal that is a reference clock signal for clock synchronization;
A master clock signal transmitting step in which the master device transmits the master clock signal generated in the master clock signal generating step to the slave device;
A master clock signal receiving step in which the slave device receives the master clock signal transmitted in the master clock signal transmitting step from the master device;
A slave clock signal generating step in which the slave device generates a slave clock signal that is a synchronous clock signal synchronized with the master clock signal received in the master clock signal receiving step;
A slave clock signal transmission step in which the slave device transmits the slave clock signal generated in the slave clock signal generation step in a folded manner to the master device;
A slave clock signal receiving step in which the master device receives the slave clock signal transmitted in the slave clock signal transmission step in a return manner from the slave device;
A clock signal quality comparison step in which the master device measures and compares the quality of the master clock signal transmitted in the master clock signal transmission step and the slave clock signal received in the return in the slave clock signal reception step;
Are sequentially provided. A clock signal quality monitoring method comprising:

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