JP5598129B2 - Information equipment - Google Patents

Description

  The present invention relates to a communication unit and an information device.

  PCI Express, which is a standard for local IO for PCs, has a data transfer band close to a GB / sec order memory bus band by replacing a conventional parallel interface with a high-speed serial interface. Furthermore, with the spread of the PCI Express standard, a technology using a PCI Express compatible communication protocol is also being used for high-speed data transfer between more distant devices, from a connection form in which an option card is directly inserted into a PC slot.

  As a typical example, a cable adapter conforming to the PCI Express cable standard, a PCI Express standard for connection to a PC, and a bridge chip on the cable adapter, the cable transmission unit uses GigaEthernet (registered trademark), FibreChannel. PCI Express compatible cable adapter cards that convert the protocol to a communication protocol different from PCI Express, such as InfiniBand, GigaChanne, and ExpressEther, are provided.

  Each of these cable transmission technologies employs a high-speed serial communication method, and a plurality of cables can be used depending on the band of one cable. For example, in PCI Express, one set of high-speed serial communication path (differential signal, transmission / reception) is defined as one lane, and generally the communication band can be expanded to 16 lanes using a maximum of 16 cables. In this way, the host PC and the cable adapter card are connected by the PCI Express communication standard with a bandwidth (number of connection lanes) that exceeds the bandwidth required for data transfer, and the number of cables connected to the cable adapter card is determined by the PCI on the host PC side. There is known a PCI Express compatible cable adapter card that secures a cable transmission band with a host PC by adjusting the number according to the Express connection band.

  Patent Document 1 proposes a cable adapter card that is connected to an expansion interface of a plurality of PCs in order to provide a system that can use an expansion interface of a computer system as a network and related devices. The cable adapter card includes a PCI Express (× 8) card edge connector, a PCI Express (× 8) cable connector, a PCI Express switch, and a transmission / reception buffer. Bidirectional high-speed communication is realized by connecting the PC and the expansion interface with a cable.

  However, the conventional cable adapter card has a problem that the data transfer efficiency may decrease. For example, a host PC having an MCH (Memory Control Hub) that responds by dividing data transfer for a large size memory read request packet into a plurality of small size packets in accordance with the CPU cache line size (for example, 64 bytes) Consider the case of using for communication. In such a case, in the conventional cable adapter card, the data packet protocol overhead (decrease in the ratio of the data payload to the total packet size) is large, so that the data transfer efficiency is lowered.

  The present invention has been made in view of the above, and an object of the present invention is to provide a communication unit and an information device that can suppress a decrease in data transfer efficiency.

The present invention is an information device including a substrate and a communication unit , the information device including a substrate and a communication unit, wherein the substrate includes a storage unit for storing data, and the communication unit is in a waiting state. If not, the data is read out from the storage unit with a predetermined first size and transmitted to the communication unit. When the communication unit is in a waiting state, a plurality of data of the first size are combined and the first A storage control unit that generates data of a second size larger than the size and transmits the data of the second size to the communication unit after the waiting state is resolved, and the communication unit is connected to the substrate I am, first and connectors capable of transmitting and receiving data to and from the substrate, is connected to the cable, a second connector capable of transmitting and receiving data through the cable, before It is connected to a second connector, which is connected to the first connector in greater bandwidth than the bandwidth between the second connector and relays data between the second connector and the first connector It comprises a relay unit, and characterized and this.

  According to the present invention, it is possible to suppress a decrease in data transfer efficiency.

FIG. 1 is a block diagram showing a configuration example of a PCI Express cable adapter card according to the prior art. FIG. 2 is a transfer timing chart of the read request packet and the read data packet. FIG. 3 is a schematic configuration diagram of the print system according to the present embodiment. FIG. 4 is a diagram for explaining a transmission path between the server and the printer. FIG. 5 is a block diagram illustrating a configuration example of the cable adapter according to the present embodiment. FIG. 6 is a plan view illustrating an example of a hardware configuration of the cable adapter according to the present embodiment. FIG. 7 is a block diagram illustrating a configuration example of the PCI Express switch. FIG. 8 is a diagram for explaining an operation example of the cable adapter. FIG. 9 is a transfer timing chart of the read request packet and the read data packet. FIG. 10 is a diagram for explaining a difference in data transfer efficiency between the conventional cable adapter and the cable adapter according to the present embodiment. FIG. 11 is a diagram for explaining a difference in data transfer efficiency between the conventional cable adapter and the cable adapter according to the present embodiment. FIG. 12 is a diagram for explaining a difference in data transfer efficiency between the conventional cable adapter and the cable adapter according to the present embodiment. FIG. 13 is a diagram for explaining the difference between the results of actual measurement of the data transfer efficiency of the conventional cable adapter and the cable adapter of the present embodiment.

  Exemplary embodiments of a communication unit and an information device according to the present invention will be explained below in detail with reference to the accompanying drawings. Hereinafter, a print system including a server and a printer as information devices including a communication unit will be described as an example. Note that applicable apparatuses (systems) are not limited to these.

  First, a specific example of the above problem will be described. Some chip sets have a large payload size packet transfer (Max Payload Size, Max Read Request Size in the PCI Express standard) via the PCI Express interface, and the IO port of the data transfer destination is crowded. As long as it is not in a waiting state, a data packet for a read request is divided into CPU cache line size of 64 bytes and responds.

  In the PCI Express protocol, the header size of the read data packet is defined as 20 bytes, and the effective transfer efficiency is 76% as a theoretical limit. Further, when the packet is divided, the number of link layer control packets such as ACK packets and flow control packets increases, so that the data transfer efficiency is further reduced to about 70% of the actually measured value.

  If the required bandwidth is slightly insufficient for a certain number of cables (for example, one) due to poor data transfer efficiency, the number of cables is further doubled (or two if one is insufficient) It must be increased. Whether the transmission cable is a copper wire or an optical cable, the cost is higher as the transmission cable has a high-speed transmission band and enables long-distance communication. In particular, when an optical cable is used, the cost of the transceiver and the receiver is very high, and the cost of the entire adapter card jumps several times by the cost of only one additional cable.

  Next, as an example of a conventional PCI Express cable adapter card, the configuration and problems of the cable adapter card disclosed in Patent Document 1 will be described.

  The cable adapter card of Patent Document 1 includes a PCI Express (× 8) card edge connector, a PCI Express (× 8) cable connector, a PCI Express switch, and a transmission / reception buffer. By connecting a PC and an expansion interface with a cable, A configuration for realizing bidirectional high-speed communication is employed (FIG. 3 of Patent Document 1).

  The card edge connector is connected to an expansion slot of the host PC. A PCI Express cable is connected to the cable connector. A general cable adapter card is configured such that the band on the cable side and the connection band with the host PC are the same. In the configuration example of Patent Document 1, both have a band of x8 lanes.

  FIG. 1 is a block diagram showing a configuration example of a PCI Express cable adapter card according to the prior art.

  As shown in FIG. 1, conventionally, two host PCs (motherboards 10a and 10b) are connected with cables via cable adapters 20a and 20b. FIG. 1 shows a configuration example of a band of × 4 lanes. Since the MCH 13 of the motherboards 10a and 10b establishes a link with the cable adapters 20a and 20b with a band of x4 lanes, a band for x4 lanes is allocated to the internal bus band of the chipset.

  When a memory read request packet (hereinafter abbreviated as a read request) indicated by an arrow 41 is issued from the motherboards 10a and 10b, via the PCI Express switch 21, the cable connector 22 and the PCI Express cable 30 of the cable adapters 20b and 20a, The read request packet is transferred to the MCH 13 on the motherboard 10a side.

  The MCH 13 of the motherboard 10a reads data of the requested size from the memory 12, and responds with a read data packet indicated by an arrow 42. At this time, the MCH 13 acquires data by dividing the data in accordance with the cache line size of the CPU 11. For example, if the cache line size is 64 bytes, even if the requested request size is 128 bytes or 256 bytes, data is obtained by dividing every 64 bytes, and read data packets are responded sequentially.

  FIG. 2 is a transfer timing chart of a read request packet (128B Rd) and a read data packet (64B Cpl: Cpl is an abbreviation for Completion of the PCI Express standard) when four 128-byte read requests are consecutive.

  When four 128-byte requests are issued from the motherboard 10b, the MCH 13 of the motherboard 10b transfers the 64-byte data packet divided into eight. The PCI Express read data packet includes 20-byte header information (including physical layer frame data) and a memory read data payload.

Data transfer efficiency is calculated as follows. In other words, a transfer state in which a loss of about 24% is a theoretical limit.
Packet size = header 20 bytes + data 64 bytes = 84 bytes
Data transfer efficiency = data size / packet size = 64/84 = 76.1%

  This embodiment increases protocol overhead even when used for communication with a device such as a host PC having an MCH (MCH 13 in FIG. 1) that transfers data by dividing it into a plurality of small-sized packets. Prevent data transfer efficiency.

  FIG. 3 is a schematic configuration diagram of the printing system 100 according to the present embodiment. The print system 100 according to the present embodiment includes a server 200, a printer 400, an optical active cable 500, a plurality of terminals 800, a network 900, and the like.

  The server 200 is a so-called print server, and is connected to a plurality of terminals (for example, PCs) 800 via a network 900.

  As shown in FIG. 4, the server 200 has a socket (PCI Express socket 410) that conforms to the PCI Express standard on its motherboard. A cable adapter 300 is attached to each PCI Express socket 410.

  As shown in FIG. 2, the printer 400 has a socket (PCI Express socket 410) that conforms to the PCI Express standard on its motherboard. A cable adapter 300 is attached to each PCI Express socket.

  Each cable adapter 300 is attached with an optical transceiver 600.

  The server-side optical transceiver 600 and the printer-side optical transceiver 600 are individually connected by an optical active cable 500. Here, in the present embodiment, the optical transceiver 600 has a function of converting an electric signal and an optical signal.

  Here, image information (black image information, cyan image information, magenta image information, and yellow image information) is transmitted from the server 200 to the printer 400 in the form of lossless compression data of a raster image.

  The printer 400 forms a color image according to the received image information.

  FIG. 5 is a block diagram illustrating a configuration example of the cable adapter 300 as a communication unit according to the present embodiment. As illustrated in FIG. 5, the cable adapter 300 includes a PCI Express (× 8) card edge connector 323, a cable connector 322 that is a connector conforming to the QSFP standard of 4 Ch, and a PCI Express switch 321. The cable adapter 300 realizes bidirectional high-speed communication by connecting the extension interfaces of PCs with the optical active cable 500, for example.

  The card edge connector 323 is connected to an expansion slot (for example, a PCI Express socket 410 of the motherboard 10) of a host device (for example, the server 200, the printer 400). The cable connector 322 is a connector to which the optical active cable 500 is connected.

  The conventional cable adapter card has a configuration in which the band on the cable side and the connection band with the host PC are the same. On the other hand, in the present embodiment, the band on the card edge side is wider than the band on the cable side. FIG. 5 shows a configuration example in which the bandwidth on the cable side is 4 Ch (corresponding to 4 lanes) and the card edge side is × 8 lanes. In this example, the bandwidth for each lane is the same (for example, 5 Gbps). When the bandwidth for each lane is 5 Gbps, the bandwidth on the cable side is 20 Gbps (4 × 5 Gbps), and the bandwidth on the card edge side is 40 Gbps (8 × 5 Gbps). The number of lanes and the bandwidth for each lane are not limited to this, and can be any value as long as the bandwidth on the card edge side is larger than the bandwidth on the cable side.

  Instead of using the cable connector 322 and the optical active cable 500, a copper wire cable compliant with the PCI Express cable standard, a cable capable of transmitting other high-speed differential signals, and a cable connector corresponding to the cable may be used. It doesn't matter.

  For example, an inexpensive PCI Express copper wire cable can be used for a short distance. When using a PCI Express copper cable, not only data signals but also reference clock, reset, and power control sideband signals can be used.

  FIG. 6 is a plan view illustrating an example of a hardware configuration of the cable adapter 300 according to the present embodiment.

  In the cable adapter 300, a cable connector 322, a connector 311, a connector 316, a PCI Express switch 321 and the like are mounted on a board 310.

  In addition, card edge connectors 323 are formed on both sides near one end of the board 310. Here, for the sake of convenience, the surface on which the cable connector 322 is mounted is referred to as A surface, and the surface on the opposite side is referred to as B surface. In addition, the codes | symbols L11 and L12 in FIG. 6 are 105 mm and 130 mm, for example.

  In FIG. 6, the area where the serial signal lines on the board 310 are wired with the highest priority is indicated by hatching. The serial signal line is a PCI Express transmission line, specifically, a wiring between the card edge connector 323 and the PCI Express switch 321 and between the PCI Express switch 321 and the cable connector 322. . Note that a region on the B surface side corresponding to the wiring region is also a wiring region.

  The connector 311 is connected to the sideband signal terminal of the card edge connector 323. As a result, a sideband signal that does not need to be transmitted at such a high speed can be transmitted via a transmission medium (for example, a cable that complies with the IEEE 802.3 standard) different from the serial signal. As a result, cost reduction can be achieved.

  The connector 311 is connected to a terminal for + 3.3V of the card edge connector 323. Thereby, it is possible to know whether or not the cable adapter 300 is attached to the counterpart device. Further, the two terminals of the connector 311 are looped on the board 310. Thereby, it is possible to know whether or not the cable adapter 300 is attached to the device on its own side.

  The connector 316 is a connector for supplying electric power to the cooling fan when the cooling fan is attached. The power is supplied from the server 200 or the printer 400 via the card edge connector 323.

  The PCI Express switch 321 functions as a switch (relay unit) compliant with the PCI Express standard that relays data between the card edge connector 323 and the cable connector 322.

  Next, an example of the configuration of the PCI Express switch 321 will be described. FIG. 7 is a block diagram illustrating a configuration example of the PCI Express switch 321. As shown in FIG. 7, the PCI Express switch 321 includes reception ports (RX) 350a and 350b and transmission ports (TX) 360a and 360b. The reception port 350a and the transmission port 360a are x8 communication ports. The reception port 350b and the transmission port 360b are × 4 communication ports.

  The reception ports 350a and 350b include reception buffers 351a and 351b, respectively. The transmission ports 360a and 360b include a retransmission buffer 361a and a transmission buffer 362a, and a retransmission buffer 361b and a transmission buffer 362b, respectively.

  The reception buffers 351a and 351b are buffers that store received data. The transmission buffers 362a and 362b are buffers that store data to be transmitted. The retransmission buffers 361a and 361b are buffers that store the transmitted data so that the data can be retransmitted when an error occurs in the transmitted data.

  Each buffer has a buffer area of 32 stages of header areas and a data area of 4096 bytes. Each of the reception buffers 351a and 351b, the transmission buffer 362b, and the retransmission buffer 361b can store 32 read request packets.

The number of read data packets stored is as follows.
(1) When a read data packet divided every 64 bytes is returned in response to a 128-byte request, 32 read data packets can be stored in the reception buffer, transmission buffer, and retransmission buffer of each port.
Header: 32 stages (= header buffer size 32 stages)
Data: 64 bytes × 32 = 2048 bytes (<data buffer size 4096 bytes)
(2) When a 128-byte read data packet is returned in response to a 128-byte request, 32 read data requests can be stored in the reception buffer, transmission buffer, and retransmission buffer of each port.
Header: 32 steps (= header buffer size 32 steps)
Data: 128 bytes × 32 = 4096 bytes (= data buffer size 4096 bytes)
(3) When a 256-byte read data packet is returned in response to a 256-byte request, 16 read data requests can be stored in the reception buffer, transmission buffer, and retransmission buffer of each port.
Header: 16 steps (<Header buffer size 32 steps)
Data: 256 bytes × 16 = 4096 bytes (= data buffer size 4096 bytes)

  Note that the buffer size in FIG. 7 is an example, and other buffer sizes may be used. Further, the configuration may be such that the reception buffer size <the transmission buffer size, or the reception buffer size> the transmission buffer size.

  FIG. 8 is a diagram for explaining an operation example of the cable adapter 300. FIG. 8 shows a configuration example in which the motherboard 10a and the motherboard 10b of two host devices (for example, the server 200 and the printer 400) are connected by the optical active cable 500 via the cable adapters 300a and 300b. Each of the cable adapters 300a and 300b has the same configuration as that of the cable adapter 300. The configuration of FIG. 1 is that the band on the card edge side is 4 Ch (corresponding to 4 lanes) with respect to x8 lanes so that the band on the card edge side is wider than the band on the cable side. Is different.

  Since both the motherboard 10a and the MCH 13 of the motherboard 10b establish a link with the cable adapter in a band of x8 lanes, a band for x8 lanes is allocated to the internal bus band of the chipset.

  When a memory read request packet (hereinafter abbreviated as a read request) indicated by an arrow 341 is issued from the motherboard 10b, it is sent to the MCH 13 on the motherboard 10a side via the PCI Express switch 321 and the optical active cable 500 of the cable adapters 300b and 300a. A read request packet is transferred.

  The MCH 13 of the motherboard 10a reads data of the requested size from the memory 12, and responds with a read data packet indicated by an arrow 342. At this time, the MCH 13 acquires data by dividing the data in accordance with the cache line size of the CPU 11. For example, if the cache line size is 64 bytes, even if the requested request size is 128 bytes or 256 bytes, data is obtained by dividing every 64 bytes, and read data packets are responded sequentially.

  In the present embodiment, the cable band (× 4) of the cable adapter 300 is narrower than the internal bus band (× 8) of the MCH 13. For this reason, after the PCI Express switch 321 reception buffer (reception buffer 351 in FIG. 7) of the cable adapter 300 has a shortage of remaining capacity in a packet waiting for transmission to the optical active cable 500, read data packet transmission from the MCH 13 is performed. There is a waiting time. When 64 bytes of data for the next read request arrives during the waiting time, the MCH 13 combines the waiting 64 bytes of data with the 64 bytes of data that arrived later to generate a new 128 bytes packet. The MCH 13 transmits a 128-byte data packet to the cable adapter after the waiting state is resolved.

  The waiting state can be detected by a flow control packet notified from the reception flow control unit 361 of the PCI Express switch 321 when the remaining capacity of the reception buffer 351 becomes a predetermined value or less, for example. Similarly, the release of the waiting state can be detected by the flow control packet notified from the reception flow control unit 361.

  FIG. 9 shows a transfer timing chart of the read request packet (128B Rd) and the read data packet (128B Cpl) when four 128-byte read requests are consecutive.

When four 128-byte requests are issued from the motherboard 10b, when a waiting time occurs in the read data packet transmission, the MCH 13 of the motherboard 10a responds with a 128-byte data packet. A PCI Express read data packet includes 20-byte header information (including physical layer frame data) and a memory read data payload. For this reason, the data transfer efficiency is calculated as follows.
Packet size = header 20 bytes + data 128 bytes = 148 bytes
Data transfer efficiency = data size / packet size = 128/148 = 86.5%

  As described above, according to the present embodiment, the data transfer efficiency is improved to about 86.5% as compared with about 76% of the related art.

  FIG. 10 is a diagram for explaining a difference in data transfer efficiency between a conventional cable adapter (for example, the cable adapters 20a and 20b in FIG. 1) and the cable adapter 300 of the present embodiment in 128-byte read data transfer.

  FIG. 10 is a diagram comparing the timing chart at the time of data transfer of the conventional cable adapter shown in FIG. 2 and the timing chart at the time of data transfer of the cable adapter 300 of the present embodiment shown in FIG. In 128B (Byte) read data transfer, the protocol loss of 24%, which is the conventional theoretical limit, is improved to about 14% by the configuration of the present embodiment.

  FIG. 11 is a diagram for explaining a difference in data transfer efficiency in 256-byte read data transfer between the conventional cable adapter and the cable adapter 300 of the present embodiment.

  FIG. 11 is a diagram comparing the timing chart at the time of data transfer of the conventional cable adapter and the timing chart at the time of data transfer of the present embodiment in the 256B read data transfer in which the read request size is further increased.

When four 256B requests are issued from the motherboard 10b, the MCH 13 of the motherboard 10a responds with a 256-byte data packet when a waiting time occurs in the read data packet transmission. The data transfer efficiency in this case is calculated as follows.
Packet size = header 20 bytes + data 256 bytes = 276 bytes
Data transfer efficiency = data size / packet size = 256/276 = 92.8%

  Thus, the data transfer efficiency is further improved as the read request size increases. That is, the protocol loss of 24%, which is the conventional theoretical limit, is improved to about 7% in the example of FIG.

  FIG. 12 is a diagram for explaining a difference in data transfer efficiency for each read request size between the conventional cable adapter and the cable adapter 300 of the present embodiment.

  When the read request size is 64 bytes, which is the same as the cache line size of the MCH 13, there is no difference in data transfer efficiency between the cable adapter 300 of the prior art and the cable adapter 300 of the present embodiment, but the larger the request size, It turns out that a high effect is acquired.

  Note that, according to the maximum payload size of the MCH 13 and the PCI Express switch 321 (the values of the Max Payload Size and the Max Read Request Size in the PCI Express standard), the cable adapter 300 according to the present embodiment uses the maximum 4 KB request for the PCI Express standard. The data transfer efficiency can be improved up to 99.5%.

Data transfer efficiency in the case of a 4 KByte request is calculated as follows.
Packet size = header 20 bytes + data 4096 bytes = 4116 bytes
Data transfer efficiency = data size / packet size = 4096/4116 = 99.5%

  FIG. 13 is a diagram for explaining the difference between the results of actual measurement of data transfer efficiency in the read data transfer of 128 bytes request size between the conventional cable adapter and the cable adapter 300 of the present embodiment.

  FIG. 12 compares the calculation results of the theoretical limit value of the protocol loss. In the prior art, in actual data transfer, in addition to protocol loss due to the ratio of packet size to data size, data link layer packets (ACK, NAK, Fupdate-FC packets, etc. in the PCI Express standard) ) Increase.

  For this reason, the difference in data transfer efficiency with respect to the present embodiment is further larger than the calculated value. In the actual measurement results of FIG. 13, the data transfer efficiency of the cable adapter according to the conventional technique was 68%, and the data transfer efficiency of the cable adapter 300 of the present embodiment was 85% close to the theoretical limit value. It can be seen that even in 128-byte read data transfer, the loss of data transfer efficiency can be improved from 32% to 15%.

  In the above, an example using the PCI Express switch 321 that uses the PCI Express protocol as it is for cable transmission has been described. However, a bridge chip that converts the protocol from PCI Express to another communication protocol for cable transmission is used. It may be configured. If the PCI Express switch 321 is used, a conversion process is not required and the configuration can be made at low cost.

  In addition, by increasing the number of lanes (for example, 8) on the card edge connector 323 side from the number of lanes (for example, 4) on the cable connector 322 side, the bandwidth on the card edge connector 323 side is made larger than that on the cable connector 322 side. Explained in the example. The method of increasing the bandwidth on the card edge connector 323 side than the cable connector 322 side is not limited to this.

  For example, the number of lanes may be the same, and the bandwidth for each lane of the lane on the cable connector 322 side may be configured to increase the bandwidth for each lane of the lane on the card edge connector 323 side. That is, for example, the number of lanes may be 8 lanes, the bandwidth for each lane on the cable connector 322 side may be 2.5 Gbps, and the bandwidth for each lane on the card edge connector 323 side may be 5 Gbps. .

  Further, for example, the band on the card edge connector 323 side may be made larger than the cable connector 322 side by making the sizes of the reception buffer 351 and the transmission buffer 352 different.

  When the number of lanes is different, the lane to be used may be designated among the actually connected lanes by changing the setting of the PCI Express switch 321 or the like. For example, two cable connectors 322 for connecting to a 4ch (4 lane) cable are provided, and the PCI Express switch 321 and the two cable connectors 322 are connected in 8 lanes. Then, when the bandwidth is slightly insufficient, the setting of the PCI Express switch 321 is changed so that only four lanes with any one of the cable connectors 322 can be used.

  As described above, in the present embodiment, the band of the card edge connector that connects the PCI Express switch port of the cable adapter to the data transfer source device is the cable connector side to which the data transfer destination cable is connected. It is set as the structure which becomes wider than this band. As a result, a read data response acceptance waiting state can always be generated at the MCH interface of the data transfer source device. Therefore, even when data transfer for a large size memory read request packet is used for communication with a device having an MCH that responds by dividing it into a plurality of small size packets in accordance with the cache line size of the CPU. The read data packet can be controlled so as not to be divided into CPU cache line sizes. As a result, an increase in protocol overhead can be prevented and a decrease in data transfer efficiency can be suppressed.

10a, 10b Motherboard 11 CPU
12 memory 13 MCH
DESCRIPTION OF SYMBOLS 100 Print system 200 Server 300a, 300b Cable adapter 321 PCI Express switch 322 Cable connector 323 Card edge connector 400 Printer 500 Optical active cable 600 Optical transceiver 800 Terminal 900 Network

JP 2009-94778 A

Claims (6)

An information device comprising a substrate and a communication unit,
The substrate is
A storage unit for storing data;
When the communication unit is not in a waiting state, data is read from the storage unit with a predetermined first size and transmitted to the communication unit, and when the communication unit is in a waiting state, a plurality of data of the first size is received. In addition, a storage control unit that generates data of a second size larger than the first size and transmits the data of the second size to the communication unit after the waiting state is resolved,
The communication unit is
A first connector connected to the board and capable of transmitting and receiving data to and from the board ;
A second connector connected to the cable and capable of transmitting and receiving data via the cable ;
Connected to the second connector, connected to the first connector in a band greater than the band between the second connector, and relays data between the first connector and the second connector comprising a relay unit for, a,
Information equipment that characterized a call. In the relay unit, the number of lanes connected to the first connector is larger than the number of lanes connected to the second connector, and the bandwidth of each lane connected to the first connector is the second band. Be the same as the lane connected to the connector,
The information device according to claim 1. In the relay unit, the number of lanes connected to the first connector is the same as the number of lanes connected to the second connector, and the bandwidth for each lane of the lane connected to the first connector is the first lane. Larger than the lane connected to the connector of 2,
The information device according to claim 1. The relay unit relays protocol data conforming to the PCI Express standard without converting the data to other protocol data;
The information device according to claim 1. The second connector can be connected to a cable conforming to the QSFP standard;
The information device according to claim 1. The second connector can be connected to a copper cable compliant with the PCI Express standard;
The information device according to claim 1.

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