JP5599591B2 - Driving device, display device, and driving method of display device - Google Patents

Description

  The present invention relates to a drive unit and a display device having the drive unit, and more particularly to a drive unit capable of reducing power consumption and a display device having the drive unit.

  In general, the liquid crystal display device includes a color filter substrate, an array substrate coupled to the color filter substrate, and a liquid crystal layer interposed between the color filter substrate and the array substrate. The color filter substrate includes a color filter layer and a common electrode, and the array substrate includes a pixel electrode facing the common electrode.

  Here, a common voltage is applied to the common electrode, and a data voltage is applied to the pixel electrode. Accordingly, an electric field is formed between the pixel electrode and the common electrode due to a potential difference between the data voltage and the common voltage. The liquid crystal molecules contained in the liquid crystal layer are aligned by the electric field, and as a result, the liquid crystal display device can display an image by adjusting the light transmittance of the liquid crystal layer.

  However, when data voltages having the same polarity are continuously applied with respect to the common voltage for each frame, the liquid crystal molecules included in the liquid crystal layer are deteriorated. Therefore, recent liquid crystal display devices employ an inversion driving method in order to prevent such liquid crystal deterioration.

  The inversion driving method includes a frame inversion driving method and a line inversion driving method. The frame inversion driving method reverses the polarity of the data voltage for each frame with respect to the DC common voltage, and the line inversion driving method sets the polarity of the data voltage to one or more lines with respect to the AC common voltage. This is a method of reversing in units.

  By driving the liquid crystal display device in the inversion driving method, the current state of liquid crystal deterioration is removed. However, if the polarity of the data voltage is reversed on a line basis, the transition time of the data voltage becomes longer and the current consumption increases.

Korean Patent Publication No. 2008-0017988

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a drive unit for reducing power consumption.

  Another object of the present invention is to provide a display device employing the drive unit.

  Another object of the present invention is to provide a method applied to drive the display device.

  To achieve the above object, the driving unit according to the present invention includes a timing controller, a data driver, and a gate driver. The timing controller outputs video data, a data control signal, a gate control signal, and a switching signal. The data driver includes a data processing unit and a switching circuit. The data processing unit converts the video data into a data voltage based on the data control signal and outputs the data voltage, and the switching circuit receives the data voltage and a common voltage that swings at a predetermined cycle, and is common in response to the switching signal. One of the voltage and the data voltage is output.

  The gate driver outputs a gate voltage in response to the gate control signal.

  The timing controller outputs a switching signal at a specific point in the initial 1/2 period of the common voltage transition period. The switching circuit outputs a common voltage at the specific time in response to the switching signal.

  The display device according to the present invention includes a timing controller, a data driver, a gate driver, and a display panel. The timing controller outputs video data, a data control signal, a gate control signal, and a switching signal. The data driver includes a data processing unit and a switching circuit. The data processing unit converts the video data into a data voltage based on the data control signal and outputs the data voltage, and the switching circuit receives the data voltage and a common voltage that swings at a predetermined cycle, and responds to the switching signal with the common voltage. One of the data voltage and the data voltage is selected and output. The gate driver outputs a gate voltage in response to the gate control signal. The display panel receives one of the data voltage and the common voltage output from the switching circuit in response to the gate voltage, charges the pixel, and displays an image.

  The timing controller outputs a switching signal at a specific point in the initial 1/2 period of the common voltage transition period. The switching circuit outputs a common voltage at the specific time in response to the switching signal to precharge the pixel.

  The display device driving method according to the present invention generates video data, a data control signal, a gate control signal, and a switching signal, converts the video data into a data voltage based on the data control signal, and The data voltage is output in response to the switching signal, the common voltage is output at a specific time in the initial 1/2 period of the common voltage transition period that swings in a predetermined cycle in response to the switching signal in the second state, and the gate Outputting a gate signal in response to the control signal, precharging the pixel with a common voltage, and applying a data voltage to the pixel in response to the gate signal to display an image corresponding to the data voltage.

  According to the driving unit and the display device having the driving unit, the timing controller outputs the switching signal at a specific time close to the voltage level of the next data voltage output from the data processing unit in the transition period of the common voltage. The switching circuit provided in the data driver outputs the common voltage temporarily at the specific time in response to the switching signal.

  Therefore, the transition time of the data voltage can be shortened, and as a result, the current consumption of the drive unit can be reduced.

FIG. 3 is a block diagram illustrating a driving unit of a liquid crystal display panel according to an embodiment of the present invention. FIG. 2 is a waveform diagram showing a common voltage and a data voltage of the drive unit shown in FIG. 1. FIG. 2 is a block diagram of a switching signal generation unit of the drive unit shown in FIG. 1. It is a figure which shows the gradation of the present video data and the following video data of the switching signal generation unit shown in FIG. It is a figure which shows the transition area of the common voltage corresponding to 64 gradations. It is a circuit diagram of the switching circuit of the drive unit shown in FIG. It is a block diagram of the liquid crystal display device by other embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a driving unit of a liquid crystal display panel according to an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating a common voltage and a data voltage of the driving unit illustrated in FIG.

  Referring to FIG. 1, the driving unit 250 includes a timing controller 100, a data driver 230, and a gate driver 240.

  The timing controller 100 receives a data enable signal DE, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and video data I-data from an external device. The timing controller 100 converts the video data I-data into red, green, and blue data RGB-data and provides the converted data to the data driver 230. The timing controller 100 generates a data control signal and a gate control signal by using the data enable signal DE, the main clock signal MCLK, the vertical synchronization signal Vsync, and the horizontal synchronization signal Hsync, and the data driver 230 and the gate driver. And 240 respectively. The timing controller 100 also includes a switching signal generation unit 150 that generates the first and second switching signals S1 and S2 and provides them to the data driver 230. The switching signal generation unit 150 will be specifically described with reference to FIG.

  The data driver 230 includes a data processing unit 210 and a switching circuit 220. The data processing unit 210 receives a data control signal and red, green, and blue data RGB-data from the timing controller 100 and outputs a plurality of data voltages Vdata1 to Vdata. Here, the data control signal includes a horizontal start signal STH, an inverted signal REV, and an output start signal TP. The horizontal start signal STH is a signal for starting the operation of the data driver 230, the inverted signal REV is a signal for inverting the polarity of the data voltages Vdata1 to Vdata, and the output start signal TP is sent from the data processing unit 210 to the data voltage. It is a signal that determines the timing at which Vdata1 to Vdata are output.

  Data voltages Vdata 1 to Vdata output from the data processing unit 210 are provided to the switching circuit 220. The switching circuit 220 receives the common voltage Vcom and receives the first and second switching signals S <b> 1 and S <b> 2 from the timing controller 100. The switching circuit 220 is connected to the output terminals OT1 to OTm of the data driver 230.

  The switching circuit 220 selects and outputs one of the data voltages Vdata1 to Vdata and the common voltage Vcom to the output terminals OT1 to OTm in response to the first and second switching signals S1 and S2. As shown in FIG. 2, the common voltage Vcom is an alternating voltage that swings at a predetermined period. FIG. 2 shows only the waveform of the first data voltage Vdata1 as an example among the plurality of data voltages Vdata1 to Vdata. However, the remaining data voltages have a similar form.

  Referring to FIG. 2, the common voltage Vcom has a first amplitude w1, and the first data voltage Vdata1 has a second amplitude w2 smaller than the first amplitude w1. In particular, the first data voltage Vdada1 swings within the swing range of the common voltage Vcom.

  One cycle of the common voltage Vcom includes a voltage maintaining section H1 that maintains a predetermined voltage level and a transition section T1 that changes to a different voltage level. The first data voltage Vdata1 swings in a phase opposite to that of the common voltage Vcom, and the polarity of the first data voltage Vdata1 with respect to the common voltage Vcom is inverted in units of a half cycle of the common voltage Vcom. The half cycle of the common voltage Vcom is the same as one horizontal scanning section, and one horizontal scanning section can be defined as a high section of each gate signal described later.

  Here, the data voltage output during the high period of the current gate signal is defined as the current data voltage Vdata (i), and the data voltage output during the high period of the next gate signal is defined as the next data voltage Vdata (i). Define as 1). Here, the polarity of the current data voltage Vdata (i) and the polarity of the next data voltage Vdata (i + 1) are opposite to each other as shown in FIG.

  Since the current data voltage Vdata (i) and the next data voltage Vdata (i + 1) have different polarities, a predetermined time is required for transition. The current consumption of the drive unit 250 increases as the required time becomes longer.

  Therefore, the switching circuit 220 outputs the current data voltage Vdata (i) in the voltage maintaining period H1, and in the transition period T1 in which the polarity of the common voltage Vcom is inverted, the initial ½ period of the transition period T1. A switching operation is performed so as to output a common voltage Vcom having a voltage level corresponding to a predetermined time. In order to reduce the transition time of the data voltage, the switching circuit 220 at the time point P1 (see FIG. 2) of the transition period T1 where the voltage level of the common voltage Vcom is closest to the next data voltage Vdata (i + 1). The common voltage Vcom is selected instead of the current data voltage Vdata (i) and is output to the first output terminal OT1 of the data driver 230.

  As shown in FIG. 2, the common voltage Vcom has a phase opposite to that of the first data voltage Vdata1, and in the transition period T1, the next data in the first 1/2 period from the latter 1/2 period. It has a voltage level closer to the voltage Vdata (i + 1). Accordingly, by outputting the common voltage Vcom instead of the current data voltage Vdata (i) at a predetermined time point P1, the current data voltage Vdata (i) transitions to the next data voltage Vdata (i + 1). As a result, the current consumption in the drive unit 250 can be reduced.

  Referring to FIG. 1, the gate driver 240 sequentially outputs a plurality of gate signals GS1 to GSn in response to the gate control signal. The gate control signal includes a vertical start signal STV and first and second clock signals CKV and CKVB. The vertical start signal STV is a signal for starting the operation of the gate driver 240, and the first and second clock signals CKV and CKVB determine the timing at which the gate signals GS1 to GSn are sequentially output from the gate driver 240. Signal.

  3 is a block diagram of the switching signal generation unit shown in FIG. 1, and FIG. 4 is a diagram showing the gray levels of the current video data and the next video data shown in FIG.

  Referring to FIG. 3, the switching signal generation unit 150 includes an inversion unit 110, a comparison unit 120, and a signal generation unit 130.

  Inversion unit 110 includes an inverter 111. The inversion unit 110 receives the current video data data (i) from the timing controller 100, inverts the current video data data (i) using the inverter 111, and converts the inverted data to the next video data data. Output as inverted video data for predicting (i + 1).

  Referring to FIG. 4, 64 gradations, that is, 0 to 63 gradations are displayed, and although not shown, there is a voltage corresponding to the gradation. Each of the 64 gradations has a different voltage level due to a plurality of resistors 270 connected in series. A switching element 260 is connected to each of the 64 gradations, and the switching element 260 is turned on / off according to each bit state of 6-bit video data supplied from the outside. For example, when video data of “101011” is input, the switching element 260 corresponding to each bit is turned on, and a voltage corresponding to the 43rd gradation among 63 gradations is output as a data voltage.

  As an example of the present invention, it is assumed that the current video data data (i) corresponds to the 43rd gradation, and the current video data data (i) has a positive polarity with respect to the common voltage Vcom. The inverted video data data (i + 1) has a polarity different from that of the current video data data (i). However, assuming that the inverted video data data (i + 1) is displayed in the same gradation, the inverted video data data (i + 1) is This corresponds to the 20th gradation.

  Therefore, when the current video data “data (i)” of “101101” is input to the inversion unit 110, the inversion unit 110 outputs the inverted video data “data (i + 1)” of “010100”.

  Inverted video data data (i + 1), that is, the next video data data (i + 1) is generated by the inversion unit 110 even if it does not display the same gradation as the current video data data (i). Since the inverted video data data (i + 1) has the same polarity as the next video data, the voltage corresponding to the reverse video data data (i + 1) reaches the voltage corresponding to the next video data. The time required for this is substantially reduced. As a result, power consumption can be reduced.

  Meanwhile, the comparison unit 120 receives the inverted video data data (i + 1) and the common voltage Vcom, and counts the transition period T1 of the common voltage Vcom using a predetermined reference clock RCLK. The comparison unit 120 outputs the comparison signal COM1 when the count value matches the gradation value of the inverted video data data (i + 1) output from the inversion unit 110.

  FIG. 5 is a diagram illustrating a transition period of a common voltage corresponding to 64 gradations.

  As shown in FIG. 5, the transition interval T1 of the common voltage Vcom includes the first interval a1 from the time corresponding to the minimum common voltage level Vcom-min to the time corresponding to the minimum data voltage level Vdata-min, and the maximum data. A second interval a2 from the voltage level Vdata-max to a time corresponding to the maximum common voltage level Vcom-max and a sharing interval c1 existing between the first and second intervals a1 and a2 are included.

  Here, the sharing interval c1 is divided into intervals corresponding to gradations (for example, 64 gradations “000000” to “111111”) that the data voltage can express.

  Of the transition interval T1, the initial 1/2 interval includes a part of the sharing interval c1. In the sharing interval c1 included in the initial 1/2 interval, the common voltage Vcom may have a voltage level that matches the next data voltage Vdata (i + 1) at a predetermined time. If the charging of the common voltage Vcom and the charging of the current data voltage Vdata (i) are shared at the predetermined time point, the current data voltage Vdata (i) reaches the next data voltage Vdata (i + 1). Time can be shortened.

  On the other hand, in order to calculate the predetermined time point, the comparison unit 120 compares whether the count value of the sharing period c1 matches the gradation value corresponding to the next data voltage Vdata (i + 1). The comparison unit 120 outputs the comparison signal COM1 when the count value matches the gradation value corresponding to the next data voltage Vdata (i + 1) (for example, when the gradation value is “010100”). .

  Referring to FIG. 3 again, the signal generator 130 generates the first and second switching signals S1 and S2 based on the comparison signal COM1, and the generated first and second switching signals S1 and S2 are data. The switching circuit 220 provided in the driver 230 is provided. Here, the first and second switching signals S1 and S2 are 1-bit signals and have values inverted from each other.

  The first switching signal S1 has a high state 1 in the voltage maintaining period H1, and maintains the high state 1 in most of the transition period T1. The first switching signal S1 is responsive to the comparison signal COM1 provided from the comparison unit 120 in a period where the count value of the sharing period c1 matches the gradation value corresponding to the next data voltage Vdata (i + 1). Has a low state 0. On the other hand, since the second switching signal S2 has a state in which the first switching signal S1 is inverted, the second switching signal S2 has a count value in the sharing period c1 corresponding to the next data voltage Vdata (i + 1). It has a high state 1 only in a section that matches the gradation value.

  FIG. 6 is a circuit diagram of the switching circuit shown in FIG. Referring to FIG. 6, the switching circuit 220 includes a plurality of first switching elements ST11 to ST1m and a plurality of second switching elements ST21 to ST2m.

  The plurality of first switching elements ST11 to ST1m receive the plurality of data voltages Vdata1 to Vdata output from the data processing unit 210 of the data driver 230, respectively, and are connected to the plurality of output terminals OT1 to OTm of the data driver 230, respectively. Is done. Specifically, each of the plurality of first switching elements ST11 to ST1m receives an input electrode that receives a corresponding data voltage, an output electrode that is connected to the corresponding output terminal OT1 to OTm, and the first switching signal S1. A control electrode.

  The plurality of second switching elements ST21 to ST2m receive the common voltage Vcom and are connected to the plurality of output terminals OT1 to OTm, respectively. Specifically, each of the plurality of second switching elements ST21 to ST2m receives an input electrode that receives the common voltage Vcom, an output electrode that is connected to the corresponding output terminals OT1 to OTm, and a second switching signal S2. And a control electrode.

  As shown in FIG. 3, the first and second switching signals S <b> 1 and S <b> 2 are generated by the signal generator 130 and have phases inverted from each other.

  The plurality of second switching elements ST21 to ST2m responds to the second switching signal S2 in the sharing interval c1 in the interval in which the count value matches the grayscale value corresponding to the next data voltage Vdata (i + 1). Turn on. Therefore, the common voltage Vcom is temporarily output to the output terminals OT1 to OTm of the data driver 230 instead of the data voltages Vdata1 to Vdata. Here, the plurality of first switching elements ST11 to ST1m are turned off by the first switching signal S1, and the data voltages Vdata1 to Vdata are not provided to the output terminals OT1 to OTm.

  When the first switching signal S1 is switched to the high state, the plurality of first switching elements ST11 to ST1m are turned on by the first switching signal S1, and the data voltage Vdata1 is applied to the output terminals OT1 to OTm of the data driver 230. ~ Vdatam is output.

  Thus, when the polarity of the data voltage is inverted in units of one horizontal scanning interval, the current data voltage is shared by sharing the charge of the common voltage close to the next data voltage and the current data voltage. Can shorten the time required for transition to the next data voltage, and as a result, current consumption can be reduced.

  FIG. 7 is a block diagram of a liquid crystal display device according to another embodiment of the present invention. However, among the constituent elements shown in FIG. 7, the same constituent elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  Referring to FIG. 7, the liquid crystal display device 400 includes a liquid crystal display panel 300 that displays an image, and a drive unit 250 (shown in FIG. 1) that drives the liquid crystal display panel 300. Since the drive unit 250 has the same configuration as that of FIG. 1, the description of the drive unit 250 is omitted.

  The liquid crystal display panel 300 includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn. The plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn are insulated from each other and intersect to define a plurality of pixel regions in the liquid crystal display panel 300. Each pixel region includes a pixel formed of a thin film transistor TFT, a liquid crystal capacitor Clc, and a storage capacitor Cst. The thin film transistor TFT has a source electrode connected to a corresponding data line, a gate electrode connected to a corresponding gate line, and a drain electrode connected to a pixel electrode which is a lower electrode of the liquid crystal capacitor Clc. The liquid crystal capacitor Clc and the storage capacitor Cst are connected in parallel to the drain electrode.

  The common electrode, which is the upper electrode of the liquid crystal capacitor Clc, faces the pixel electrode with the liquid crystal layer therebetween, and receives the common voltage Vcom. As shown in FIG. 7, the common voltage Vcom provided to the common electrode is also provided to the switching circuit 220 of the data driver 230.

  The data driver 230 is electrically connected to the plurality of data lines DL1 to DLm included in the liquid crystal display panel 300, and the gate driver 240 is electrically connected to the plurality of gate lines GL1 to GLn included in the liquid crystal display panel 300. Connected to.

  In response to the second switching signal S2, the data driver 230 temporarily outputs the common voltage Vcom when the common voltage Vcom has a voltage level corresponding to the next data voltage, and the first switching is performed in the remaining period. In response to the signal S1, the data voltages Vdata1 to Vdata are output.

  Accordingly, when the polarity of the data voltage is inverted for each gate line unit, the common voltage Vcom is output when the common voltage Vcom has a voltage level close to the next data voltage in the transition period of the common voltage Vcom. As a result, the next data lines DL1 to DLm are precharged to the common voltage Vcom. Accordingly, it is possible to shorten the time for the current data voltage charged in each pixel to transit to the next data voltage, and as a result, it is possible to reduce current consumption.

  The gate driver 240 sequentially outputs a plurality of gate signals and applies them to the plurality of gate lines GL1 to GLn. Accordingly, the pixels provided in the liquid crystal display panel 300 and connected to the gate lines are sequentially turned on in units of pixel rows, and the turned-on pixels receive the data voltages Vdata1 to Vdata from the data driver 230 and display a desired image. indicate.

  According to the driving unit and the display device having the driving unit, the timing controller outputs the switching signal at a specific time close to the voltage level of the next data voltage output from the data processing unit in the transition period of the common voltage. The switching circuit provided in the data driver outputs the common voltage temporarily at the specific time in response to the switching signal.

  Therefore, the data voltage transition time can be shortened, and as a result, the current consumption can be reduced.

  Although the present invention has been described above with reference to the embodiments, those skilled in the art can make various modifications to the present invention without departing from the spirit and scope of the present invention described in the following claims. It can be understood that modifications and changes can be made.

100 timing controller 150 switching signal generation unit 210 data processing unit 220 switching circuit 230 data driver 240 gate driver 250 drive unit

Claims (6)

A timing controller that outputs video data, a data control signal, a gate control signal, and a switching signal;
A data processing unit that converts the video data into a data voltage based on the data control signal and outputs the data voltage, and receives the data voltage and a common voltage that swings at a predetermined period, and receives the common signal in response to the switching signal. A data driver including a switching circuit that outputs one of a voltage and the data voltage;
Anda gate driver outputs a gate signal in response to the gate control signal,
The timing controller outputs the switching signal at a specific time in an initial 1/2 period among the transition period of the common voltage,
The switching circuit outputs the common voltage in response to the switching signal at the specific time point ,
The common voltage has an amplitude greater than the data voltage;
The transition period of the common voltage includes a first period from a time corresponding to the minimum common voltage level to a time corresponding to the minimum data voltage level, and a time corresponding to the maximum common voltage level from the time corresponding to the maximum data voltage level. A second section up to and a sharing section existing between the first and second sections,
The specific time point is included in the sharing section of the initial 1/2 section,
The sharing interval is divided into intervals corresponding to gradations represented by the data voltage, and the specific time point indicates a gradation level of a voltage obtained by inverting the data voltage corresponding to the current data line. A driving device characterized by being at a point of time . A timing controller that outputs video data, a data control signal, a gate control signal, and a switching signal;
A data processing unit that converts the video data into a data voltage based on the data control signal and outputs the data voltage, and receives the data voltage and a common voltage that swings at a predetermined period, and receives the common signal in response to the switching signal. A data driver including a switching circuit that outputs one of a voltage and the data voltage;
A gate driver that outputs a gate signal in response to the gate control signal,
The timing controller outputs the switching signal at a specific time in an initial 1/2 period among the transition period of the common voltage,
The switching circuit outputs the common voltage in response to the switching signal at the specific time point,
The switching circuit is
A first switching element for providing the data voltage to an output terminal of the data driver based on the first switching signal among the switching signals;
A second switching element for providing the common voltage to the output terminal based on a second switching signal having an inverted phase with respect to the first switching signal;
The timing controller includes a switching signal generation unit that generates the first and second switching signals and provides them to the switching circuit,
The switching signal generation unit includes:
An inverting unit for inverting the first video data corresponding to the current data line of the timing controller and outputting the second video data;
The voltage level corresponding to the second video data is compared with the voltage level of the common voltage, and the common voltage has a voltage level corresponding to the second video data in the transition section of the common voltage. A comparator for outputting a comparison signal;
And a signal generator that provides the second switching signal to the second switching element based on the comparison signal . The comparison unit counts the transition period of the common voltage using a predetermined reference clock, and outputs the comparison signal to the signal generation unit when the count value corresponds to the gradation value of the second video data. The drive device according to claim 2 , wherein: A driving device according to any one of claims 1 to 3,
A display panel that receives the data voltage output from the switching circuit in response to the gate signal and charges the pixels to display an image ; and
Before SL switching circuit, a display apparatus characterized by precharging the data line to output the common voltage in response to the switching signal at the particular point in time. A timing controller that outputs video data, a data control signal, a gate control signal, and a switching signal ;
A data processing unit that converts the video data into a data voltage based on the data control signal and outputs the data voltage, a common voltage that swings with the data voltage and a predetermined period, and receives the common voltage in response to the switching signal. A data driver including a switching circuit that outputs one of the data voltages ;
A gate driver that outputs a gate signal in response to the gate control signal ;
A display panel that receives the data voltage output from the switching circuit in response to the gate signal and charges a pixel to display an image;
A display device driving method including:
The switching circuit selects and outputs the data voltage in response to the switching signal in a first state ;
Said switching circuit, and the pre-charge the data lines by outputting the common voltage at a particular point in the initial 1/2 section of the transition section of the common voltage in response to the switching signal of the second state,
The switching circuit selects and outputs the data voltage in response to the switching signal in the first state;
The gate driver outputs a gate signal in response to the gate control signal;
The display panel is displaying an image corresponding to the data voltage is applied to the data voltage to the pixels in response to the gate signal, only including,
The common voltage has an amplitude greater than the data voltage;
The transition period of the common voltage includes a first period from a time corresponding to the minimum common voltage level to a time corresponding to the minimum data voltage level, and a time corresponding to the maximum common voltage level from the time corresponding to the maximum data voltage level. A second section up to and a sharing section existing between the first and second sections,
The specific time point is included in the sharing section of the initial 1/2 section,
The sharing interval is divided into intervals corresponding to gradations represented by the data voltage, and the specific time point indicates a gradation level of a voltage obtained by inverting the data voltage corresponding to the current data line. A display device driving method, comprising: A timing controller that outputs video data, a data control signal, a gate control signal, and a switching signal;
A data processing unit that converts the video data into a data voltage based on the data control signal and outputs the data voltage, a common voltage that swings with the data voltage and a predetermined period, and receives the common voltage in response to the switching signal. A data driver including a switching circuit that outputs one of the data voltages;
A gate driver that outputs a gate signal in response to the gate control signal;
A display panel that receives the data voltage output from the switching circuit in response to the gate signal and charges a pixel to display an image;
Including
The switching circuit is
A first switching element for providing the data voltage to an output terminal of the data driver based on the first switching signal among the switching signals;
A second switching element for providing the common voltage to the output terminal based on a second switching signal having an inverted phase with respect to the first switching signal;
The timing controller is a driving method of a display device including a switching signal generation unit that generates the first and second switching signals and provides the first and second switching signals to the switching circuit,
The first switching element provides the data voltage to the output terminal;
The switching signal generating unit is
Inverting the first video data corresponding to the current data line of the timing controller and outputting the second video data;
The voltage level corresponding to the second video data is compared with the voltage level of the common voltage, and the common voltage has a voltage level corresponding to the second video data in the transition section of the common voltage. Output a comparison signal
Providing the second switching signal to the second switching element based on the comparison signal;
The second switching element provides the common voltage to the output terminal based on the second switching signal to precharge a data line;
The first switching element provides the data voltage to the output terminal;
A display device driving method, wherein the display panel applies the data voltage to the pixel in response to the gate signal to display an image corresponding to the data voltage.

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