JP5637664B2 - Liquid crystal display device and electronic device - Google Patents

Description

  The present invention relates to a liquid crystal display device in which a common electrode constituting a pixel is divided into a plurality of parts, and an electronic device including the liquid crystal display device.

Conventionally, liquid crystal display devices have been widely used as display devices for displaying images. The liquid crystal display device includes an element substrate, a counter substrate disposed opposite to the element substrate, and a liquid crystal provided between the element substrate and the counter substrate.
As such a liquid crystal display device, a control circuit for alternately supplying a voltage VCOML and a voltage VCOMH to a common electrode, a scanning line driving circuit for sequentially supplying a selection voltage to a plurality of scanning lines, and when a scanning line is selected And a data line driving circuit that alternately supplies a positive image signal having a higher potential than the voltage VCOML and a negative image signal having a lower potential than the voltage VCOMH to a plurality of data lines. (For example, refer to Patent Document 1).
Here, so-called common electrode division driving (COM division driving) is performed in which the common electrode is divided for each horizontal line and the voltage VCOML or the voltage VCOMH is supplied from the control circuit to each common electrode. By adopting this COM division driving, it is possible to suppress the deterioration of display quality.

JP 2008-33298 A

The control circuit in the liquid crystal display device described in Patent Literature 1 includes any one of a switch that connects the common electrode and the voltage supply line of the voltage VCOMH, and a switch that connects the common electrode and the voltage supply line of the voltage VCOML. One of them is always turned on. Therefore, either the voltage VCOML or the voltage VCOMH is always supplied to the common electrode.
By the way, when the COM division driving is adopted, a control circuit as a voltage supply source is arranged at both ends of the common electrode due to a crosstalk countermeasure or the like. In this case, the same potential must be applied to both ends of the common electrode. However, the potentials at both ends may differ during an unstable period until the circuit starts to be driven, such as when the power is turned on. Then, an abnormal inrush current flows into the common electrode.
Therefore, an object of the present invention is to provide a liquid crystal display device and an electronic apparatus that can prevent the common electrode from having an abnormal potential when performing COM division driving.

In order to solve the above problems, a liquid crystal display device according to the present invention, supply and a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, the image data to the data line a drive circuit for, a liquid crystal display device comprising a display panel having a pixel of the multiple, the common electrode and the pixel electrode for driving a pair of substrates facing each other across the liquid crystal layer, the liquid crystal molecules of the liquid crystal layer If, in the configuration, common electrode is divided into multiples corresponding to the scanning lines, either co the first voltage and the second voltage higher potential than the first voltage in response to the polarity signal a voltage supply state for supplying to the passing electrodes, and the voltage blocking state in which a common electrode in a high impedance state, the switchable control circuit is arranged respectively on both end sides of the respective common electrodes divided, the control circuit, Scanning one stage before the scanning line corresponding to the control circuit And a selection signal that outputs an H level during a period in which the common electrode is in a high impedance state, and the scanning signal supplied to the previous scanning line becomes H level. During the period until the selection signal becomes L level, the common electrode is set in a voltage cutoff state immediately before the voltage supplied to the common electrode is switched between the first voltage and the second voltage .
In this way, the common electrode is divided into a plurality of parts, and the COM divided drive for supplying the first voltage or the second voltage for each common electrode is adopted. For example, the first voltage and the second voltage are divided for each horizontal line. While being alternately supplied to the common electrode, a positive-polarity image signal and a negative-polarity image signal can be alternately supplied for each horizontal line with respect to the voltage of the common electrode. As a result, the flicker between pixels can be offset and the deterioration of display quality can be suppressed.

Furthermore, the circuit is unstable because the control circuit can be switched between a voltage supply state for supplying the first voltage or the second voltage for each common electrode and a voltage cutoff state for setting the common electrode to a high impedance state. In such a case, the common electrode can be prevented from having an abnormal potential by setting the voltage cutoff state.
Also, by making the voltage blocking state such as when the circuit is in an unstable state, due to the mutually different potentials from a control circuit disposed on both end sides of the common electrode is applied, abnormal common electrode Inrush current can be suppressed. Therefore, adverse effects on the liquid crystal due to the inrush current can be avoided.
Furthermore, since the common electrode is placed in a high impedance state when the voltage supplied to the common electrode is inverted, it is possible to prevent the potentials at both ends of the common electrode from being different due to a delay due to a characteristic difference between the switching elements of the control circuit. can do. As a result, the through current generated due to the delay can be suppressed.

Further, the liquid crystal display device according to the present invention, in the above, the control circuit includes a first switch connected between the voltage supply source of the common electrode and the first voltage, the common electrode and the second voltage and a second switch connected between the voltage supply, either the first switch及beauty second switch by the oN state, the voltage supply state, the first switch及beauty second by the oFF state switches simultaneously, it may be a voltage cut-off state.
Thereby, it is possible to switch between the voltage supply state and the voltage cutoff state with a relatively simple circuit configuration.

Furthermore, the liquid crystal display device according to the present invention, in the above, the control circuit, during a predetermined period and power-off after power may be a voltage cut-off state.
Thus, the common electrode can be in a high impedance state during a period until the circuit starts to be driven after power-on or during power-off, which is likely to cause the potentials at both ends of the common electrode to be different. Therefore, abnormal operation can be effectively avoided .

Et al is, an electronic apparatus according to the present invention, Ru comprise any liquid crystal display device described above.
Thereby, it can be set as the electronic device which implement | achieved suppression of the display quality fall and suppression of the potential abnormality of a common electrode.

It is a block diagram which shows the structure of the liquid crystal display device in this embodiment. It is a figure which shows the specific structure of the latch circuit LQ of the common electrode drive circuit 40B. It is a figure which shows the specific structure of the selection circuit LR of the common electrode drive circuit 40B. It is a timing chart explaining operation in a 1st embodiment. It is a figure which shows the structure of the unit control circuit in a common common electrode drive circuit. It is a figure which shows the structure of the unit control circuit LP in 2nd Embodiment. It is a timing chart explaining operation in a 2nd embodiment. It is a timing chart at the time of using a common common electrode drive circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 10 according to the first embodiment.
The liquid crystal display device 10 includes a liquid crystal panel using an active matrix thin film transistor (TFT). As shown in FIG. 1, the liquid crystal display device 10 has a display area 100. Around the display area 100, a scanning line driving circuit 20, a data line driving circuit 30, and common electrode driving circuits 40A and 40B. Is arranged.
Although not particularly shown, the liquid crystal panel has a configuration in which an element substrate and a counter substrate are bonded to each other while maintaining a certain gap, and liquid crystal is sealed in the gap.

In the display region 100 of the liquid crystal panel, a plurality of scanning lines 112 are provided so as to extend in the row (X) direction, and a plurality of data lines 114 are extended in the column (Y) direction. In addition, each scanning line 112 is provided so as to be electrically insulated from each other. The pixels 110 are arranged corresponding to the intersections between the scanning lines 112 and the data lines 114, respectively.
Each pixel 110 includes an n-channel thin film transistor (hereinafter referred to as TFT) 116 that functions as a pixel switching element, a pixel electrode 118, a common electrode 108 provided opposite to the pixel electrode 118, and a storage capacitor 130. And have.
Since each pixel 110 has the same configuration, the pixel 110 of n rows and m columns is connected to the scanning line 112 of the n row in the pixel 110 of the n rows and m columns. On the other hand, the source electrode is connected to the m-th column data line 114, and the drain electrode is connected to the pixel electrode 118.

Further, the common electrode 108 is divided for each horizontal line corresponding to the scanning line 112. The plurality of common electrodes 108 divided for each horizontal line are made of a transparent conductive material such as ITO (Indium Tin Oxide), and are provided along the scanning lines 112. The common electrode 108 has a voltage VCOML (first voltage) from the common electrode drive circuits 40A and 40B and a voltage VCOMH (second voltage) having a higher potential than the voltage VCOML alternately as a common signal Z. It comes to be supplied. The method of supplying the voltage VCOML or the voltage VCOMH from the common electrode driving circuits 40A and 40B for each common electrode 108 in this way is hereinafter referred to as a COM division driving method.
Since the common electrode 108 is made of a transparent conductive material such as ITO (Indium Tin Oxide), a common electrode wiring made of the same material as the scanning line 112 is divided into a plurality of divided common electrodes 108 in order to reduce resistance. And may be connected.

The common electrode drive circuits 40A and 40B are arranged on both the left and right sides of the display area 100 in FIG. 1 (both ends of the common electrode 108) in order to prevent crosstalk. When the common signal Z is supplied to the common electrode 108, the common signal Z having the same potential is output from the common electrode driving circuits 40A and 40B.
The pixel capacitor 120 has a configuration in which a liquid crystal which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108 and holds a differential voltage between the pixel electrode 118 and the common electrode 108. In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage.
In the present embodiment, the pixel electrode 118 and the common electrode 108 are formed on the same substrate (element substrate), and the liquid crystal of the liquid crystal display device 10 operates in an FFS (Fringe Field Switching) mode of a lateral electric field drive system. And

Although not particularly shown, the scanning line driving circuit 20 includes a shift register, an output control circuit, and a buffer. The scanning line driving circuit 20 outputs the scanning signals Y1, Y2, Y3,..., Y320 over the period of one frame in accordance with the vertical start signal STV and the vertical clock signals CKV1, CKV2, respectively 1, 2, 3,. This is supplied to the scanning line 112 in the 320th row. That is, the scanning line driving circuit 20 selects the scanning lines 112 in the order of the first, second, third,..., And 320th rows, and sets all the TFTs 116 connected to the selected scanning lines 112 to the on state (conductive state). To do.
In addition, the data line driving circuit 30 outputs data signals X1, X2, X3,..., X240, which are voltages corresponding to the display gradations of the pixels 110 located on the scanning line 112 selected by the scanning line driving circuit 30, as 1 , 2,..., 240 are supplied to the data lines 114 in the 240th column.

Here, the data line driving circuit 30 supplies a positive data signal having a higher potential than the voltage of the common electrode 108 to the data line 114 and writes an image voltage based on the positive data signal to the pixel electrode 118. Positive polarity writing and negative polarity writing in which a negative polarity data signal having a potential lower than the voltage of the common electrode 108 is supplied to the data line 114 and an image voltage based on the negative polarity data signal is written to the pixel electrode 118. Are alternately performed for each horizontal line.
The basic operation of the liquid crystal display device 10 configured as described above is as follows.
In the present embodiment, the common signal Zn is supplied to the n-th common electrode 108 before the scanning signal Yn is supplied to the n-th scanning line 112.
First, the voltage VCOML or the voltage VCOMH is selectively supplied as the common signal Z from the common electrode driving circuits 40A and 40B to the common electrode 108.

Specifically, the voltage VCOML and the voltage VCOMH are alternately supplied to each common electrode 108 every frame period. For example, when the voltage VCOML is supplied to the common electrode 108n in the n-th row (n is an integer satisfying 1 ≦ n ≦ 320) in one frame period, the voltage VCOMH is applied to the common electrode 108n in the next one frame period. Supply.
Further, different voltages are supplied to adjacent common electrodes 108. For example, when the voltage VCOML is supplied to the common electrode 108n in one frame period, the common electrode 108 (n-1) in the (n-1) th row and the (n + 1) th row are common in the same one frame period. A voltage VCOMH is supplied to the electrode 108 (n + 1).

Next, the scanning signals Y1 to Y320 are sequentially supplied from the scanning line driving circuit 20 to the 320 scanning lines 112, so that all the TFTs 116 connected to the scanning lines 112 are sequentially turned on, and the scanning lines 112 are sequentially turned on. All the pixels 110 related to are sequentially selected.
Next, in synchronization with the selection of these pixels 110, a positive image signal and a negative image signal are transferred from the data line driving circuit 30 to the data line 114 according to the voltage of the common electrode 108 by one horizontal line. Supply alternately every time.
Specifically, when the voltage VCOML is supplied to the common electrode 108 n of the selected pixel 110 among the 320 common electrodes 108, a positive image signal is supplied to the data line 114. On the other hand, when the voltage VCOMH is supplied to the common electrode 108 n of the selected pixel 110 among the 320 common electrodes 108, a negative image signal is supplied to the data line 114.

Then, an image signal is supplied to all the pixels 110 selected by the scanning line driving circuit 20 from the data line driving circuit 30 via the data line 114 and the on-state TFT 116, and an image voltage based on this image signal is applied to the pixel electrode. 118 is written. As a result, a potential difference is generated between the pixel electrode 118 and the common electrode 108, and a driving voltage is applied to the liquid crystal.
The scanning line driving circuit 20 and the data line driving circuit 30 correspond to the driving circuit, and the common electrode driving circuits 40A and 40B correspond to the control circuit.

(Configuration of common electrode drive circuit)
Next, the configuration of the common electrode drive circuits 40A and 40B will be described.
The common electrode drive circuits 40A and 40B include 320 unit control circuits P1 to P320 corresponding to the 320 rows of common electrodes 108, respectively. Each unit control circuit P includes a latch circuit Q and a selection circuit R, respectively.

The unit control circuit P is supplied with a voltage VCOML, a voltage VCOMH, and a polarity signal POL for selecting the voltage VCOML or the voltage VCOMH. The latch circuit Q holds the polarity signal POL, and the selection circuit R selectively outputs the voltage VCOML or the voltage VCOMH according to the polarity signal POL held by the latch circuit Q. Furthermore, the selection circuit R is configured to be able to switch between a voltage supply state in which the voltage VCOML or the voltage VCOMH is selectively output and a voltage cutoff state in which neither the voltage VCOML nor the voltage VCOMH is output.
Hereinafter, a unit control circuit of the common electrode driving circuit 40A arranged on the right side in FIG. Similarly, a unit control circuit of the common electrode driving circuit 40B arranged on the left side in FIG. 1 is denoted by a symbol LP, a latch circuit is denoted by a symbol LQ, and a selection circuit is denoted by a symbol LR.

(Latch circuit configuration)
Next, the configuration of the latch circuit Q will be specifically described.
FIG. 2 is a diagram showing a specific configuration of the latch circuit LQ of the common electrode driving circuit 40B.
The latch circuit LQ corresponds to each of the first latch circuits LQ1 and LQ320 provided corresponding to the first scanning line 112 and the last scanning line 112, and the other scanning lines 112, respectively. Second latch circuits LQ2 to LQ319 provided.
First, the second latch circuits LQ2 to LQ319 will be described.
Here, description will be made using the second latch circuit LQ (b) provided corresponding to the scanning line 112 (b) in the b-th row (b is an integer satisfying 2 ≦ b ≦ 319). The second latch circuit LQ (b) includes a NOR circuit (hereinafter referred to as a NOR circuit) U1, a first inverter U2, a second inverter U3, a first clocked inverter U4, and a second clock. The inverter U5 is provided.

In the second latch circuit LQ corresponding to the scanning line 112 (b) in the b-th row, one of the two input terminals of the NOR circuit U1 is adjacent to the (b-1) th row on the first row. The other input terminal is connected to the scanning line 112 (b + 1) in the (b + 1) -th row adjacent to the first scanning line 112 (b-1). The output terminal of the NOR circuit U1 is connected to the input terminal of the first inverter U2, the inverting input control terminal of the first clocked inverter U4, and the non-inverting input control terminal of the second clocked inverter U5. ing.
The output terminal of the first inverter U2 is connected to the non-inverting input control terminal of the first clocked inverter U4 and the inverting input control terminal of the second clocked inverter U5.
The polarity signal POL is input to the input terminal of the first clocked inverter U4, and the output terminal of the first clocked inverter U4 is connected to the input terminal of the second inverter U3.

The input terminal of the second inverter U3 is connected to the output terminal of the first clocked inverter U4 and the output terminal of the second clocked inverter U5, and the output terminal of the second inverter U3 is connected to the b-th row. The latch signal LAT (b) in the second latch circuit LQ is output and connected to the input terminal of the second clocked inverter U5.
A latch signal / LAT (b) is output from the connection point between the output terminal of the first clocked inverter U4 and the output terminal of the second clocked inverter U5. The latch signal LAT is a positive logic signal, and the latch signal / LAT (LAT bar) is a negative logic signal.
The second latch circuit LQ (b) in the b-th row configured as described above operates as follows.

That is, when an H level signal is supplied as a selection voltage to at least one of the scanning lines 112 (b-1) and 112 (b + 1), the NOR circuit U1 outputs an L level signal. For this reason, the first clocked inverter U4 is in an ON state in which a negative operation is permitted, so that the logic level of the polarity signal POL is inverted and output. The signal output with the logic level inverted by the first clocked inverter U4 is inverted again by the second inverter U3 and returned to the polarity signal POL. Therefore, the latch signal LAT (b) It has the same logic level as the signal POL.
On the other hand, when an L level signal is supplied as a non-selection voltage to both the scanning line 112 (b-1) and the scanning line 112 (b + 1), the NOR circuit U1 outputs an H level signal. At this time, the first clocked inverter U4 is in an off state in which a negative operation is prohibited, and the second clocked inverter U5 is in an on state in which a negative operation is permitted.

Therefore, the latch signal LAT (b) is latched by the second inverter U3 and the second clocked inverter U5.
As described above, when the selection voltage is supplied to at least one of the scanning line 112 (b-1) or the scanning line 112 (b + 1), the second latch circuit LQ (b) in the b-th row outputs the polarity signal. When POL is fetched and a latch signal LAT (b) having the same logic level as that of the polarity signal POL is output, and a non-selection voltage is supplied to both the scanning line 112 (b-1) and the scanning line 112 (b + 1), The latch signal LAT (b) is output while being held by the second inverter U3 and the second clocked inverter U5.

Next, the first latch circuits LQ1 and LQ320 will be described.
Compared with the second latch circuits LQ2 to LQ319, the first latch circuits LQ1 and LQ320 eliminate the NOR circuit U1, input terminals of the first inverter U2, and inverted input control terminals of the first clocked inverter U4. The non-inverting input control terminal of the second clocked inverter U5 is fixed to the voltage VLL corresponding to the L level. The voltage VLL is substantially equal to the non-selection voltage and is a voltage-referenced zero potential.
The first latch circuits LQ1 and LQ320 configured as described above operate in the same manner as when the NOR circuit U1 becomes L level in the second latch circuits LQ2 to LQ319. That is, the first latch circuits LQ1 and LQ320 always take the polarity signal POL and output the latch signals LAT1 and LAT320 having the same logic level as the polarity signal POL.
Note that the latch circuit RQ of the common electrode drive circuit 40A also has the same configuration as the latch circuit LQ of the common electrode drive circuit 40B shown in FIG.

(Configuration of selection circuit)
Next, the configuration of the selection circuit R will be specifically described.
FIG. 3 is a diagram showing a specific configuration of the selection circuit LR of the common electrode driving circuit 40B.
The selection circuit LR includes a voltage supply circuit LRa and a Hi-Z selection circuit LRb.
The voltage supply circuit LRa includes n-type transistors Tr1 and Tr2 and inverters 41 to 44. The Hi-Z selection circuit LRb includes n-type transistors Tr3 and Tr4 and resistors R1 and R2.
The gate electrode of the transistor Tr1 is connected to the drain electrode of the transistor Tr3 via the inverters 41 and 42. The source electrode of the transistor Tr1 is connected to the voltage supply line of the voltage VCOMH or the voltage VCOML, and the drain electrode is connected to the common electrode 108.

Here, the source electrode of the transistor Tr1 of the voltage supply circuit LRa provided corresponding to the even-numbered row is connected to the voltage supply line of the voltage VCOMH, and the voltage supply circuit LRa provided corresponding to the odd-numbered row. The source electrode of the transistor Tr1 is connected to the voltage supply line of the voltage VCOML.
The gate electrode of the transistor Tr2 is connected to the drain electrode of the transistor Tr4 via the inverters 43 and 44. The source electrode of the transistor Tr2 is connected to the voltage supply line of the voltage VCOMH or the voltage VCOML, and the drain electrode is connected to the common electrode 108.
Here, the source electrode of the transistor Tr2 of the voltage supply circuit LRa provided corresponding to the even-numbered row is connected to the voltage supply line of the voltage VCOML, and the voltage supply circuit LRa provided corresponding to the odd-numbered row. A source electrode of the transistor Tr2 is connected to a voltage supply line of the voltage VCOMH.

A selection signal INT is applied to the gate electrodes of the transistors Tr3 and Tr4. The latch signal LAT from the latch circuit RQ is applied to the source electrode of the transistor Tr3, and the latch signal / LAT from the latch circuit RQ is applied to the source electrode of the transistor Tr4.
Here, as shown in FIG. 4, the selection signal INT is a signal that becomes L level during a predetermined period after power-on or when the power is turned off (when power is shut off), and becomes H level during other periods.
The resistors R1 and R2 are connected in series between the drain electrode of the transistor Tr3 and the drain electrode of the transistor Tr4. The connection node between the resistor R1 and the resistor R2 is grounded.

When the selection signal INT is at the L level, the transistors Tr3 and Tr4 are turned off, and accordingly, the transistors Tr1 and Tr2 are turned off. Therefore, each common electrode 108 is in a state where it is electrically disconnected from the common electrode drive circuit 40B and the voltage supply is cut off, that is, a so-called Hi-Z state (high impedance state).
On the other hand, when the selection signal INT is at the H level, the transistors Tr3 and Tr4 are turned on. Therefore, one of the transistors Tr1 and Tr2 is turned on according to the latch signals LAT and / LAT from the latch circuit LQ, and the voltage VCOMH or the voltage VCOML is supplied to the common electrode 108. Become.

That is, the selection circuit LR provided corresponding to the even-numbered rows supplies the voltage VCOMH as the common signal Z to the common electrode 108 when the latch signal LAT is at the H level, and when the latch signal LAT is at the L level. The voltage VCOML is supplied to the common electrode 108 as the common signal Z.
On the other hand, if the latch signal LAT is at the H level, the selection circuit LR provided corresponding to the odd-numbered row supplies the common electrode 108 with the voltage VCOML as the common signal Z, and if the latch signal LAT is at the L level. The voltage VCOMH is supplied to the common electrode 108 as the common signal Z.
In FIG. 3, the transistor Tr1 corresponds to the first switch, and the transistor Tr2 corresponds to the second switch.
Note that the selection circuit RR of the common electrode drive circuit 40A has the same configuration as the selection circuit LR of the common electrode drive circuit 40B shown in FIG.

Next, the operation of the common electrode drive circuit 40 will be described.
First, the operation of the common electrode drive circuit 40 during stable operation will be described.
During this stable operation, the selection signal INT is set to H level. Accordingly, the transistors Tr3 and Tr4 of each selection circuit R are turned on.
If the polarity signal POL is at the H level, the latch circuits RQ1, LQ1 and RQ320, LQ320 in the first row and the 320th row take in the polarity signal POL at the H level and the latch signals LAT and L level at the H level. A latch signal / LAT is output. Therefore, the selection circuits RR1 and LR1 in the first row output the voltage VCOML as the common signal Z1, and the selection circuits RR320 and LR320 in the 320th row output the voltage VCOMH as the common signal Z320. As a result, the potential of the common electrode 108 in the first row becomes VCOML, and the potential of the common electrode 108 in the 320th row becomes VCOMH.

In this state, when the scanning signal Y1 becomes H level, the latch circuits RQ2 and LQ2 in the second row output a latch signal LAT2 that becomes H level. Then, the selection circuits RR2 and LR2 in the second row output the voltage VCOMH as the common signal Z2. As a result, the potential of the common electrode 108 in the second row becomes VCOMH.
Thereafter, when the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level, the latch circuits RQ2 and LQ2 in the second row hold and output the latch signal LAT2 at H level. Therefore, the potential of the common electrode 108 in the second row is kept at VCOMH.
At this time, the latch circuits RQ3 and LQ3 in the third row output a latch signal LAT3 that becomes H level. Then, the selection circuits RR3 and LR3 in the third row output the voltage VCOML as the common signal Z3. As a result, the potential of the common electrode 108 in the third row becomes VCOML.

  In this way, the common electrode drive circuit 40 supplies the voltage VCOMH to the common electrode 108 in the second row in synchronization with the supply of the scanning signal Y1 that is at the H level to the scanning line 112 in the first row. That is, in the same one frame period, the common electrode 108 in the p-th row (p is an even number satisfying 1 ≦ p ≦ 320) is synchronized with the supply of the H level scanning signal Y (p−1). Thus, the voltage VCOMH is supplied. Thereafter, the potential of the common electrode 108 in the p-th row is held at the voltage VCOMH until the H-level scanning signal Y (p−1) is supplied again in the next frame period.

Further, in the same one frame period, the common electrode 108 in the q-th row (q is an odd number satisfying 1 ≦ q ≦ 320) is synchronized with the supply of the H-level scanning signal Y (q−1). Thus, the voltage VCOML is supplied. Thereafter, the potential of the common electrode 108 in the q-th row is held at the voltage VCOML until the H-level scanning signal Y (q−1) is supplied again in the period of the next frame.
As described above, the potential of the common electrode 108 is changed from one of the voltage VCOMH and the voltage VCOML before the timing at which the H level scanning signal is applied to the corresponding scanning line 112 (here, one horizontal scanning period). It is configured to switch to the other.

Next, the operation of the common electrode drive circuit 40 during unstable operation will be described.
Assume that the liquid crystal display device 1 is not turned on. At this time, since the selection signal INT is at the L level, the transistors Tr3 and Tr4 of each selection circuit R are in the off state. Therefore, each common electrode 108 is in a Hi-Z state.
When the power is turned on at time t1 in FIG. 4, the selection signal INT becomes H level at time t2 when a predetermined time has elapsed since the power was turned on. Here, the predetermined time is set to a period from when the power is turned on until each circuit starts to be driven stably.
When the selection signal INT becomes H level, the transistors Tr3 and Tr4 of each selection circuit R are turned on. Thereby, after that, the operation at the stable operation described above is performed.

Thereafter, when the power is turned off at time t3, the selection signal INT becomes L level. As a result, the common electrode 108 transitions to the Hi-Z state again.
As described above, the selection circuit R in the present embodiment is configured to be able to switch between the voltage supply state in which the voltage VCOMH or the voltage VCOML is selected and output, and the voltage cutoff state in which the common electrode 108 is disconnected to be in the Hi-Z state. Yes.
By the way, the general selection circuit R is configured to have only a function of setting a voltage supply state.

FIG. 5 is a diagram showing a configuration of a unit control circuit LP in a general common electrode driving circuit.
The unit control circuit LP shown in FIG. 5 is different from the selection circuit LR shown in FIG. 3 in the configuration of the selection circuit LR. Here, the unit control circuit LP provided corresponding to the odd-numbered rows is shown.
The selection circuit LR includes a p-type transistor Tr5 and an n-type transistor Tr6. A latch signal LAT from the latch circuit LQ is applied to the gate electrodes of the transistors Tr5 and Tr6.
The source electrode of the transistor Tr5 is connected to the voltage supply line of the voltage VCOMH, and the drain electrode is connected to the common electrode 108. The source electrode of the transistor Tr6 is connected to the voltage supply line of the voltage VCOML, and the drain electrode is connected to the common electrode 108.

On the other hand, although not shown here, in the unit control circuit LP provided corresponding to the even-numbered rows, the source electrode of the transistor Tr5 is connected to the voltage supply line of the voltage VCOML, and the source electrode of the transistor Tr6 is connected to the voltage VCOMH. Connect to the supply line.
As described above, in the general common electrode driving circuit 40, either one of the transistors Tr5 and Tr6 is always turned on in response to the latch signal LAT, and the voltage VCOMH or the voltage VCOML is always output.
When the common electrode drive circuit 40 is disposed on both ends of the common electrode 108, the common signal Z having the same potential must be supplied from both ends. However, during a period when the operation of the circuit becomes unstable after the power is turned on or when the power is shut off, a common signal Z having a different potential is supplied from both ends of the common electrode 108 due to a switching defect in the common electrode drive circuit 40 or the like. There is a risk. Then, an abnormal inrush current flows into the common electrode 108.

On the other hand, in the first embodiment, the selection circuit R of the common electrode driving circuit 40 is set to the voltage supply circuit Ra that selectively outputs the voltage VCOMH or the voltage VCOML, and the common electrode 108 is set to the Hi-Z state. And a Hi-Z selection circuit Rb. Then, the common electrode 108 is set to the Hi-Z state (voltage cutoff state) during a predetermined period after the power is turned on or during an unstable state such as during power cutoff. As a result, the common electrode 108 can be prevented from having an abnormal potential.
In addition, since the common electrode driving circuit 40 is disposed on both ends of the common electrode 108, in the voltage supply state, the common signal Z having the same potential is supplied from both ends of the common electrode 108, so that the COM division that takes measures against crosstalk is provided. It can be driven.

Further, by setting the voltage cutoff state in the unstable state, it is possible to suppress an abnormal inrush current from flowing into the common electrode 108 due to the potentials at both ends of the common electrode 108 being different. Therefore, adverse effects on the liquid crystal due to the inrush current can be avoided.
Further, the Hi-Z selection circuit Rb includes a transistor Tr1 connected between the common electrode 108 and the voltage supply source of the voltage VCOMH (or VCOML), a voltage supply source of the common electrode 108 and the voltage VCOML (or VCOMH), And a transistor Tr2 connected between the two transistors. Then, by turning off the transistor Tr1 and the transistor Tr2 at the same time, the common electrode 108 is set in the Hi-Z state. Therefore, it is possible to switch between the voltage supply state and the voltage cutoff state with a relatively simple circuit configuration.

  The Hi-Z selection circuit Rb includes transistors Tr3 and Tr4 that block signals applied to the gate electrodes of the transistors Tr1 and Tr2, and resistors R1 and R2 for pulling down the potentials of the gate electrodes of the transistors Tr1 and Tr2. including. Then, the transistors Tr1 and Tr2 are simultaneously turned off by controlling the transistors Tr3 and Tr4 to be turned off by the selection signal INT. Therefore, the voltage cutoff state can be reliably achieved with a relatively simple circuit configuration.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
In the second embodiment, the Hi-Z state is selected in the indefinite state such as when the power is turned on in the first embodiment, whereas the voltage of the common electrode 108 is changed from VCOMH to VCOML (or vice versa). The Hi-Z state is selected at the timing of inversion.
FIG. 6 is a diagram illustrating a configuration of the unit control circuit LP in the second embodiment. Here, the unit control circuit LP provided corresponding to the odd-numbered rows is shown.
The latch circuit LQ in FIG. 6 has the same configuration as the latch circuit LQ in the first embodiment shown in FIG. The selection circuit LR is the same as the selection circuit LR in FIG. 3 except that a NAND circuit 45 (NAND circuit) 45 is added to the selection circuit LR in the first embodiment shown in FIG. It has a configuration.

Of the two input terminals of the NAND circuit 45 in the selection circuit LR (n) provided corresponding to the scanning line 112 in the n-th row, the selection signal INT is input to one input terminal, and the other input terminal is connected to the other input terminal. Is input with the scanning signal Yn supplied to the scanning line 112 of the (n−1) th row before.
Here, the selection signal INT is a signal that is at the H level only during the period in which the common electrode 108 is in the Hi-Z state, and is at the L level in other periods. In the present embodiment, the selection signal INT is set to the H level at the timing of inverting the voltage of each common electrode 108 from the voltage VCOMH to the voltage VCOML (or vice versa).

Next, the operation in the second embodiment will be described.
FIG. 7 is a timing chart for explaining the operation in the second embodiment.
When the scanning signal Y (n-1) in the (n-1) th row changes from the H level to the L level at time t11 in FIG. 7, the selection signal INT changes to H level at time t12, and at time t13 immediately thereafter, n The scanning signal Yn in the row is switched from the L level to the H level. Then, the output signal of the NAND circuit 45 in the selection circuits RR (n + 1) and LR (n + 1) in the (n + 1) th row becomes L level, and the transistors Tr3 and Tr4 of the selection circuits RR (n + 1) and LR (n + 1) are turned off simultaneously. It becomes a state. As a result, the common electrode 108 in the (n + 1) th row is in the Hi-Z state.

Thereafter, when the selection signal INT becomes L level at time t14, the output signal of the NAND circuit 45 in the selection circuits RR (n + 1) and LR (n + 1) becomes H level, and the transistors of the selection circuits RR (n + 1) and LR (n + 1) Tr3 and Tr4 are switched to the on state. Accordingly, at this time, a voltage (here, VCOML) corresponding to the latch signal LAT output from the latch circuits RQ (n + 1) and LQ (n + 1) is supplied to the common electrode 108 in the (n + 1) th row.
Thus, from time t13 when the scanning signal Yn becomes H level to time t14 when the selection signal INT becomes L level, the common electrode 108 in the (n + 1) th row is set to the Hi-Z state, and then the Hi-Z state. The potential of the common electrode 108 in the (n + 1) th row is inverted by switching from the state to the voltage supply state.

FIG. 8 is a timing chart when the general common electrode driving circuit shown in FIG. 5 is used.
As shown in FIG. 8, when the common electrode driving circuit shown in FIG. 5 is used, the potential of the common electrode is inverted with the scanning signal Y one stage before as a trigger. That is, immediately after the scanning signal Y (n−1) in the (n−1) th row changes from the H level to the L level at time t21, the scanning signal Yn in the nth row changes from the L level to the H level at time t22. At this timing, the potential of the common electrode in the (n + 1) th row is inverted from VCOMH to VCOML.
However, in this case, if there is a difference in characteristics between the transistors Tr1 and Tr2 of the common electrode drive circuits 40A and 40B disposed at both ends of the common electrode 108, the inversion of the common electrode potential is delayed, and the potential at both ends of the common electrode 108 is reduced. It may be in a different state.

On the other hand, in the second embodiment, the common electrode 108 is set to the Hi-Z state at the timing when the potential of the common electrode 108 is inverted. Therefore, it is possible to suppress the potentials at both ends of the common electrode 108 from being different due to the delay due to the characteristic difference. As a result, the through current can be prevented from flowing into the common electrode 108.
The Hi-Z selection circuit Rb includes transistors Tr3 and Tr4 that block signals applied to the gate electrodes of the transistors Tr1 and Tr2, and resistors R1 and R2 for pulling down the potentials of the gate electrodes of the transistors Tr1 and Tr2. And a NAND circuit 45 for controlling on / off of the transistors Tr3 and Tr4. Then, the transistors Tr3 and Tr4 are controlled to be turned off by the selection signal INT and the scanning signal Y, so that the transistors Tr1 and Tr2 are turned off at the same time. Therefore, the voltage cutoff state can be reliably achieved with a relatively simple circuit configuration.

Further, since the transistors Tr3 and Tr4 are controlled to be turned off by using the scanning signal Y of the previous stage, the voltage cutoff state can be surely set at the timing when the potential of the common electrode 108 is inverted.
In each of the embodiments described above, a case where the n-type transistors Tr1 and Tr2 are applied as switches for connecting the common electrode 108 and the voltage supply lines of the voltages VCOMH and VCOML in the selection circuit R of the common electrode driving circuit will be described. However, p-type transistors and other switching elements can also be applied.
Further, in each of the above embodiments, the case where the n-type transistors Tr3 and Tr4 are applied as switches for turning off the transistors Tr1 and Tr2 in the selection circuit R of the common electrode driving circuit has been described. Transistors and other switching elements can also be applied.

Further, in each of the above embodiments, the case where the pull-down resistors R1 and R2 are provided in the Hi-Z state selection circuit Rb has been described. For example, the transistors Tr1 and Tr2 are active-low switches such as p-type transistors. In that case, a pull-up resistor may be provided.
Furthermore, in each of the above-described embodiments, the case where the FFS method is adopted as the liquid crystal driving method has been described, but a TN method, an IPS method, or the like can also be adopted.
In each of the above embodiments, the case where the positive polarity writing and the negative polarity writing are alternately performed for each horizontal line has been described. However, the positive polarity writing and the negative polarity writing are performed for each of the plurality of horizontal lines. Can also be performed alternately.

Furthermore, in each of the above-described embodiments, the case where the common electrode 108 is divided for each horizontal line has been described. However, the common electrode 108 may be divided for a plurality of horizontal lines.
Further, the liquid crystal display device of each of the above embodiments can be used as a display device mounted on an electronic device. Specific examples of the electronic device include a monitor, a TV, a notebook computer, a PDA, a digital camera, a video camera, a mobile phone, a mobile photo viewer, a mobile video player, a mobile DVD player, and a mobile audio player.

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 20 ... Scan line drive circuit, 30 ... Data line drive circuit, 40A, 40B ... Common electrode drive circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line 116 ... TFT 118 ... Pixel electrode 120 ... Pixel capacitance 130 ... Storage capacitor P ... Unit control circuit Q ... Latch circuit R ... Selection circuit Ra ... Voltage supply circuit Rb ... Hi-Z selection circuit

Claims (4)

A liquid crystal display device comprising a display panel having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and a drive circuit for supplying image data to the data lines,
The plurality of pixels includes a pair of substrates facing each other with a liquid crystal layer interposed therebetween, and a common electrode and a pixel electrode that drive liquid crystal molecules of the liquid crystal layer,
The common electrode is divided into a plurality corresponding to the scanning lines,
A voltage supply state in which either the first voltage or a second voltage having a higher potential than the first voltage is supplied to the common electrode according to the polarity signal; and a voltage cutoff state in which the common electrode is in a high impedance state. , And a control circuit capable of switching between them are arranged on both ends of each divided common electrode,
The control circuit is configured so that the scanning signal supplied to the scanning line one stage before the scanning line corresponding to the control circuit and the scanning signal supplied to the scanning line two stages before become the L level. A selection signal that rises to H level before the scanning signal supplied to the previous scanning line becomes H level and becomes L level at the timing of switching the voltage supplied to the common electrode between the first voltage and the second voltage. And the selection circuit after the scanning signal supplied to the previous scanning line becomes H level based on the output signal of the arithmetic circuit. The common electrode is set to the voltage cutoff state in a period until the signal becomes L level and immediately before the voltage supplied to the common electrode is switched between the first voltage and the second voltage.
Liquid crystal display device.
The control circuit includes a first switch connected between the common electrode and the voltage supply source of the first voltage, and a second switch connected between the common electrode and the voltage supply source of the second voltage. With a switch,
By turning on one of the first switch and the second switch, the voltage supply state is established. By simultaneously turning off the first switch and the second switch, the voltage cutoff state is obtained. To
The liquid crystal display device according to claim 1. The control circuit is in the voltage cut-off state during a predetermined period after power-on and power-off.
The liquid crystal display device according to claim 1. An electronic apparatus comprising the liquid crystal display device according to claim 1.

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