JP5644337B2 - Display device, drive control method thereof, and electronic apparatus - Google Patents

Description

The present invention, the display device and a drive control method thereof, and an electronic apparatus including the display device.

There has been proposed a technique in which a display device temporarily stores image data of an odd field period and an even field period of interlaced image data in a frame memory, and displays the image data stored in the frame memory by a line sequential method ( For example, see Patent Document 1.)
The even field period is an image delayed in time with respect to the odd field period. For this reason, when the image data stored in the frame memory is displayed in a line sequential manner, an even field period and an odd field period are between the image displayed on the even line and the image displayed on the odd line of the display panel. Deviation based on time difference occurs. Further, the display frequency of such a line sequential method is ½ of the display frequency of the interlace method, and flicker is likely to occur.

  In order to eliminate such inconvenience, this type of display device corrects the time difference between the image displayed on the odd-numbered lines and the image displayed on the even-numbered lines of the display panel, or adds a new frame between the frames. To do.

JP 2003-36056 A

  However, in order to correct the time difference between the image displayed on the odd-numbered lines and the image displayed on the even-numbered lines of the display panel, or to add a new frame between the frames, high-speed image processing is required. Therefore, there is a problem that a circuit capable of performing the above-described operation is required, and the cost is increased accordingly.

The present invention has been made in view of the above circumstances, a good display quality, and, the display device and a driving control method thereof Ru can suppress the cost, as well as, an electronic apparatus having the display device The purpose is to provide.

In order to achieve the above object, a display device according to the first aspect of the present invention provides:
A display device that displays image information according to image data,
A display panel in which pixels having light emitting elements along a plurality of rows and columns are two-dimensionally arranged;
A display driving device for driving the display panel according to the image data and displaying the image information on the display panel;
Have
The image data is an interlaced signal having a plurality of field periods;
The display driving device includes: a first pixel disposed in a specific row among a predetermined number of two or more adjacent rows of the display panel in a period corresponding to each field period of the image data. by images data corresponding to the first pixel, is operated so as to display the luminance gradation corresponding to the gradation value of the image data, the gradation value of the previous outs image data, the light emitting element The gradation value of the image data is reduced except when the first gradation value is non-light emitting and when the second gradation value is the lowest light emitting luminance when the light emitting element is emitting light. The corrected image data corrected so as to be generated is generated, and the second pixels arranged in the rows excluding the specific row among the predetermined number of rows are displayed on the first pixel by the corrected image data. Operate so that the corrected display brightness gradation is lower than the brightness gradation. Characterized in that to obtain Bei the control circuit.

The image data has an odd field period and an even field period,
The control circuit includes:
In a period corresponding to the odd field period,
The display luminance gradation of the pixels arranged in the (2k-1) th row (k: natural number) of the display panel is determined by the first image data corresponding to the (2k-1) th row of the display panel. operated to the first luminance gradation corresponding to the gradation value of the first image data,
The first image data corresponding to the (2k-1) th row of the display panel, with the display luminance gradation of the pixels arranged in one of the 2kth row or the (2k-2) th row of the display panel. the third image data corrected to decrease the tone values corresponding to the gradation value of the third image data, operates to lower than the luminance gradation of the first third luminance gradation Let
In a period corresponding to the even field period,
The display luminance gradation of the pixels arranged in the 2k rows of the display panel, the second image data corresponding to the 2k rows of the display panel, first according to the tone value of the second image data 2 brightness gradations,
The display luminance gradation of the pixels arranged in one of the (2k−1) th row or the (2k + 1) th row of the display panel is set to a level of the second image data corresponding to the 2k row of the display panel. the fourth image data corrected to reduce the tone value, corresponding to the gray scale value of the fourth image data, by operating so as to lower than said second luminance gradation fourth luminance gradation Also good.

The display device includes a data driver that generates a driving signal for driving the pixel and supplies the driving signal to the pixel,
The image data comprises a multi-bit digital signal,
The third luminance gradation and the fourth luminance gradation are respectively set to half the luminance with respect to the first luminance gradation and the second luminance gradation,
The data driver may include an arithmetic circuit that generates ½ image data obtained by shifting the image data to one bit lower.

The data driver includes a latch circuit that latches the image data, and a digital / analog conversion circuit that generates an analog voltage corresponding to a digital signal,
The arithmetic circuit may be provided between the latch circuit and the digital / analog conversion circuit.

The data driver has a data register circuit that captures the image data,
The arithmetic circuit may be connected to an input side of the data register circuit and supplied with the image data.

  The data driver is configured to operate the pixel at the third luminance gradation and the fourth luminance gradation with respect to a gradation voltage having a voltage value corresponding to a gradation value of the image data. You may have a voltage adjustment circuit which produces | generates the correction | amendment gradation voltage which reduced the value.

In order to achieve the above object, an electronic apparatus according to a second aspect of the present invention is characterized in that the display device is mounted.

In order to achieve the above object, a display device drive control method according to a third aspect of the present invention includes:
A display panel in which pixels having light-emitting elements are two-dimensionally arranged along a plurality of rows and a plurality of columns is driven according to image data that is an interlace signal having a plurality of field periods, and the display panel receives the image data A display device drive control method for displaying image information according to
In a period corresponding to each field period of the image data, a first pixel disposed in a specific one of a predetermined number of two or more adjacent rows of the display panel is used as the first pixel. by the corresponding images data, a first display step of operating such a display luminance gradation corresponding to the gradation value of the image data,
In previous gradation value of outs image data, the second gradation value becomes the lowest light emission luminance in the state in which the light emitting element non when emission to become a first gradation value and the light emitting element emits light Except for a certain time, corrected image data corrected so as to reduce the gradation value of the image data is generated, and a second of the predetermined number of rows , excluding the specific row, is disposed in the second row . pixels, by the corrected image data, and a second display step of operating so as to lower correction display luminance gradation than the display luminance gradation of the first pixel,
It is characterized by including.

The image data has an odd field period and an even field period,
The first display step includes
In a period corresponding to the odd field period,
The display luminance gradation of the pixels arranged in the (2k-1) th row (k: natural number) of the display panel is determined by the first image data corresponding to the (2k-1) th row of the display panel. a first luminance gradation display step of operating to the first luminance gradation corresponding to the gradation value of the first image data,
During the period corresponding to the even field period, the display luminance gradation of the pixels arranged in the 2k rows of the display panel, the second image data corresponding to the 2k rows of the display panel, the second A second luminance gradation display step that operates to obtain a second luminance gradation according to the gradation value of the image data,
The second display step includes
In a period corresponding to the odd-numbered field period, the display luminance gradation of the pixel arranged in one of the 2k-th row or the (2k-2) -th row of the display panel is set to the (2k-1) -th display pixel. ) by the third image data corrected to reduce the tone value of the first image data corresponding to the row, according to the gradation value of the third image data, lower than the first luminance gradation first A third luminance gradation display step which is operated to obtain a luminance gradation of 3,
In a period corresponding to the even field period, the display luminance gradation of the pixel arranged in one of the (2k−1) th row or the (2k + 1) th row of the display panel is set to the second kth row of the display panel. corresponding to the fourth image data corrected to reduce the tone value of the second image data, corresponding to the gradation value of the fourth image data, the second fourth lower than the luminance gradation And a fourth luminance gradation display step that operates to obtain luminance gradation.

According to the present invention, the user perceives an image displayed with a low gradation as an afterimage of the image of the field period displayed immediately before. For this reason, the vertical resolution of the display device is good, and the display quality is good.
Further, according to the present invention, the luminance gradation of the image in the odd field period is reduced and displayed on the pixels in the even rows, and the luminance gradation of the image in the even field period is reduced and displayed on the pixels in the odd rows. It can be handled with simple processing. For this reason, a simple configuration can be adopted, and the cost can be suppressed.

It is a block diagram which shows the structure of the display apparatus which concerns on embodiment of this invention. FIG. 2 is a circuit diagram of the pixel shown in FIG. 1. (A) is a figure which shows an example of a structure of the data driver shown in FIG. 1, (b) is a figure which shows an example of a structure of an arithmetic circuit. (A-1) and (a-2) are diagrams for explaining odd field display processing, and (b-1) and (b-2) are diagrams for explaining even field display processing. is there. It is a timing chart of odd field display processing. It is a timing chart of even field display processing. It is a figure for demonstrating the odd number field display process at the time of applying the high level voltage VGH to the gate line GL1. It is a figure for demonstrating the odd number field display process at the time of applying the high level voltage VGH to the gate line GL2. It is a figure for demonstrating the even field display process at the time of applying the high level voltage VGH to the gate line GL1. It is a figure for demonstrating the even-numbered field display process at the time of applying the high level voltage VGH to the gate line GL2. It is a figure which shows an example of the data driver comprised so that the voltage signal supplied from the D / A converter might be halved. It is a figure which shows an example of the data driver comprised so that the image data before inputting into a data register may be halved. It is a figure which shows the structure of the digital camera to which the display apparatus shown in FIG. 1 is applied. It is a figure which shows the structure of the thin-type television to which the display apparatus shown in FIG. 1 is applied. It is a figure which shows the structure of the mobile type personal computer to which the display apparatus shown in FIG. 1 is applied. It is a figure which shows the structure of the mobile telephone to which the display apparatus shown in FIG. 1 is applied.

  A display device 10 according to an embodiment of the present invention will be described below with reference to the drawings.

  The display device 10 is a device that displays an image, and includes a panel unit 101 and a control circuit 102 as shown in FIG.

  The panel unit 101 is an active drive type organic EL display panel, which includes a gate driver (select driver) 1011, a data driver 1012, and a plurality of gate lines GLi (i = 1, 2,..., N) arranged in the row direction. ), A plurality of data lines DLj (j = 1, 2,..., M) arranged in the column direction, and a plurality of pixels P (i, j) (i = 1, 2) arranged in n rows and m columns. , ..., n; j = 1, 2, ..., m).

  As shown in FIG. 2, the pixel P (i, j) includes a transistor T1, a transistor T2, an auxiliary capacitor CS, and an organic EL (Organic Electro-Luminescence) element OEL. The pixel P (i, j) is disposed in the vicinity of the intersection of the gate line GLi and the data line DLj.

The transistor T1 of the pixel P (i, j) is configured by NMOS (Negative channel Metal Oxide Semiconductor). The gate of the transistor T1 is connected to the gate line GLi. The drain of the transistor T1 is connected to the data line DLj. Further, the source of the transistor T1 is connected to the gate of the transistor T2.
The transistor T1 is turned on when a high level signal (VGH) is applied to the gate line GLi, and functions as a transfer gate that applies a voltage signal on the data line DLi to the gate of the transistor T2.

  The transistor T2 of the pixel P (i, j) is configured by a PMOS (Positive channel Metal Oxide Semiconductor). The gate of the transistor T2 is connected to the source of the transistor T1. The source of the transistor T2 is connected to a power supply circuit as an anode. Further, the drain of the transistor T2 is connected to the anode of the organic EL element OEL. Here, the power supply circuit applies a predetermined voltage V_ANODE (V) to the source of the transistor T2.

  When VGH is applied to the gate line GLi and the transistor T1 is turned on, the data driver 1012 sends a voltage signal Vd (i, j) (i = 1, 2,..., N) corresponding to the image data to the data line DLj. j = 1, 2,..., m) is applied. As a result, the voltage signal Vd (i, j) is applied (written) to the gate of the transistor T2 and the auxiliary capacitor CS. A current IEL (i, j) corresponding to the voltage signal Vd (i, j) applied to the gate of the transistor T2 flows to the anode, the transistor T2, the organic EL element OEL, and the cathode, and the organic EL element OEL emits light. . Therefore, the transistor T2 functions as a driving transistor for the organic EL element OEL.

The auxiliary capacitor CS of the pixel P (i, j) is composed of a capacitor. One terminal of the auxiliary capacitor CS is connected to the gate of the transistor T2, and the other terminal is connected to the source of the transistor T2.
When the voltage signal Vd (i, j) is applied to the auxiliary capacitor CS, the auxiliary capacitor CS holds the voltage signal Vd (i, j). Therefore, the current IEL (i, j) corresponding to this voltage signal Vd (i, j) continues to flow to the anode, the transistor T2, the organic EL element OEL, and the cathode.

The organic EL element OEL is a self-luminous display element that emits light by excitons generated by recombination of electrons and holes injected into an organic compound, and emits light at a luminance corresponding to the current value of the supplied current. To do.
The anode of the organic EL element OEL is connected to the drain of the transistor T2. The cathode of the organic EL element OEL is grounded.

  A gate driver 1011 shown in FIG. 1 includes a shift register and the like, and drives the gate lines GL1 to GLn under the control of the control circuit 102. The display device 10 is supplied with interlaced image data, but the gate driver 1011 is similar to the line-sequential display device as shown in FIGS. 5A and 6A. The gate lines GL1 to GLm have a high potential high level voltage VGH (selection level) during the selection period ts, and a low potential low level voltage VGL (non-selection period: light emission period) during the other period (non-selection period: light emission period). The scanning signals at the non-select level are sequentially output.

  On the other hand, the data driver 1012 drives each pixel in direct current under the control of the control circuit 102, and image data composed of m (bit) digital signals is supplied to each pixel, and each image data is converted to an analog voltage. The signal is converted into a signal, and the converted voltage signal is output to the data lines DL1 to DLm. Note that the image data supplied to the data driver 1012 is of an interlace method, but the data driver 1012 generates and outputs a voltage signal even when a pixel in a row to be skipped is selected.

  In order to perform such processing, the data driver 1012 includes a shift register circuit 50, a data register circuit 51, a data latch circuit 52, an arithmetic circuit 53, a digital voltage / analog, as shown in FIG. A voltage conversion circuit (DAC) 54 and an output circuit 55 are included.

  The shift register circuit 50 sequentially shifts the sampling start signal STR supplied from the control circuit 102 for each horizontal scanning period based on the shift clock signal CLK, and supplies the shift signal to the data register circuit 51.

  The data register circuit 51 receives the image data D (i, 1) to D (i, m) (i is 1 to n) for the i-th row at a timing according to the shift signal supplied from the shift register circuit 50. Capture sequentially.

  When the data latch signal STB is supplied, the data latch circuit 52 latches and holds the image data D (i, 1) to D (i, m) for one row captured in the data register circuit 51. To do.

The arithmetic circuit 53 reads the image data D (i, 1) to D (i, m) held in the data latch circuit 52 and directly follows the data control line 102 in accordance with the display control signal supplied from the control circuit 102. Is output as voltage data indicating a voltage to be applied to DLm, or each image data is shifted by 1 bit lower direction, that is, halved, and the voltage to be applied to data lines DL1 to DLm is Output as voltage data.
An example of the configuration of the arithmetic circuit 53 is shown in FIG. The circuit shown in FIG. 3B is a circuit corresponding to one data line DLj. The arithmetic circuit 53 has a configuration in which, for example, a transistor TP and a bit shift circuit 60 are connected in parallel to one data line DLj, and a display control signal is applied to the transistor TP and the bit shift circuit 60 in common. The transistor TP is turned on and conductive when the display control signal is at the inactive level, and is turned off and non-conductive when the display control signal is at the active level. The bit shift circuit 60 is constituted by, for example, a shift register circuit, and does not operate when the display control signal is at the inactive level, operates when the display control signal is at the active level, and when the image data has two or more gradations. , A signal obtained by shifting the image data in the lower direction by 1 bit (hereinafter referred to as 1/2 image data) is output. That is, 1/2 image data has a value of one gradation or more. One gradation is the lowest luminance gradation of the pixel P when the image data is a digital signal. In this configuration, when the display control signal is at the inactive level, the transistor TP is turned on to output the image data as it is to the DAC 54. When the display control signal is at the active level, the transistor TP is turned off and the bit shift circuit 60 is turned on. As a result, the image data is shifted down by 1 bit (LSB is cut and 0 is added to the MSB), and 1/2 image data is output to the DAC 54. That is, the arithmetic circuit 53 operates as a device that outputs the image data by halving in a time division operation according to the display control signal and a device that outputs the image data as it is. The transistor TP is, for example, a Pch transistor. In this case, the active level of the display control signal is high and the inactive level is low. In the bit shift circuit 60, when the image data is lower than 2 gradations, zero gradation or 1 gradation, the most significant bit is all 0 from the second bit, so the image data is shifted down by 1 bit. I can't let you. At this time, the bit shift circuit 60 does not perform the shift operation and outputs the image data as it is.

  The DAC 54 converts the voltage data calculated by the arithmetic circuit 53 into an analog voltage signal.

  The output circuit 55 converts the analog voltage signal supplied from the DAC 54 into a drive system voltage signal and outputs the voltage signal to the data lines DL1 to DLm.

  The control circuit 102 includes, for example, a processor, receives image data including a vertical synchronization signal, a horizontal synchronization signal, and the like, and supplies various control signals to be described later to the gate driver 1011 and the data driver 1012 to perform these operations. The timing is controlled and the display operation of the display device 10 is controlled.

  Next, the operation of the display device 10 according to the present embodiment will be described.

  Here, for easy understanding, one frame consisting of the image data of the odd field period shown in FIG. 4A-1 and the image data of the even field period shown in FIG. 4B-1 is shown. The pixel driving process (odd field display process and even field display process) executed by the display device 10 will be described by taking as an example a case where an image based on image data is displayed on the organic EL panel, that is, the panel unit 101.

In this example, for easy understanding, the number of gate lines GLi of the panel unit 101 is set to 480, the pixels P (i, j) are arranged in 480 rows, and each row is designated as pixel rows PL _{1 to} PL ₄₈₀ . To do. Correspondingly, the image data in the odd field period is 240 rows (OL _{1 to} OL ₂₄₀ ) corresponding to the odd rows of the pixel rows PL _{1 to} PL ₄₈₀ as shown in FIG. Minute image data. The image data in the even field period is composed of 240 rows (EL _{1 to} EL ₂₄₀ ) of image data corresponding to the even rows of the pixel rows PL _{1 to} PL ₄₈₀ as shown in FIG. Is done. Here, FIGS. 4A-1 and 4B-1 show the display states when the panel unit 101 displays the image based on the image data in the odd field period and the image data in the even field period as they are. FIGS. 4A-2 and 4B-2 show display states when an odd field display process and an even field display process described below are executed. Although not shown in FIGS. 4 (a-1) and 4 (b-1), the pixel P (i, j) of the panel unit 101, which is an active drive type organic EL display panel, has an auxiliary function. Since the voltage held in the capacitor CS is held until the next writing is performed, the even-numbered row in FIG. 4A-1 and the odd-numbered row in FIG. An image based on the image data of the period is displayed. For this reason, as described in the background art, an image shift based on the time difference between the even field period and the odd field period occurs.

(Odd field display processing)
The control circuit 102 starts sampling to the shift register circuit 50 at a predetermined timing t ₋₁ after the start of the odd field period, that is, immediately before the supply of the image data of the first row (OL ₁ ) is started. A signal STR is supplied. The shift register circuit 50 takes in the sampling start signal STR, sequentially shifts in response to the shift clock signal CLK, and supplies the shift signal to the data register circuit 51.

On the other hand, the image register D (1,1) to D (1, m) of the first row (OL ₁ ) is serially supplied to the data register circuit 51 in units of pixels as shown in FIG. 5B. Is done. The data register circuit 51 is supplied with image data D (for the pixels P (1,1) to P (1, m) in the first row supplied at a timing corresponding to the shift signal supplied from the shift register circuit 50. 1,1) to D (1, m) are taken in sequentially.

The control circuit 102 supplies a data latch signal STB to the data latch circuit 52 at a timing t1 when all the image data of the first row (OL ₁ ) is stored in the data register circuit 51. In response to the data latch signal STB, the data latch circuit 52 latches the image data D (1, 1) to D (1, m) taken into the data register circuit 51 as shown in FIG. Hold and output in parallel.

  Here, as shown in FIG. 5D, the control circuit 102 outputs an inactive level display control signal. Therefore, in the arithmetic circuit 53, the bit shift circuit 60 does not operate, the transistor TP is turned on, and the image data output from the data latch circuit 52 is output as it is.

  The D / A converter 54 converts the image data output from the arithmetic circuit 53 (= the image data D (1, 1) to D (1, m) output from the data latch circuit 52) into an analog voltage signal. Convert and output in parallel.

  The output circuit 55 performs processing such as level shifting on each analog voltage signal supplied from the D / A converter 54 and converts it into voltage signals Vd (1,1) to Vd (1, m) of the drive system. As shown in FIG. 7, it is applied to the pixels P (1,1) to P (1, m) in the first row via the data lines DL1 to DLm. FIG. 5E shows an example of a waveform of a voltage signal applied to the pixels P (1,1) to P (1, m) in the first row and first column via the data line DL1 in the first column.

  On the other hand, according to the control of the control circuit 102, the gate driver 1011 applies the high-level selection signal VGH to the gate line GL1 of the first row at the timing t1. Therefore, the transistors T1 of the pixels P (1,1) to P (1, m) in the first row are turned on, and the voltage signals Vd (1,1) to Vd (1, m) are applied to the gate of the transistor T2. When applied, transistor T2 is turned on. As a result, the current IEL (corresponding to the voltage signals Vd (1,1) to Vd (1, m) is applied to the organic EL elements OEL of the pixels P (1,1) to P (1, m) in the first row. 1,1) to IEL (1, m) flow. FIG. 5F shows an example of a waveform of a current flowing through the organic EL element OEL of the pixel P (1,1) in the first row and the first column.

Subsequently, when a period ½ of one horizontal scanning period H of the image data, that is, the selection period ts of the gate line GL1 has elapsed and the timing t2, the gate driver 1011 reduces the voltage applied to the gate line GL1 to a low level. The level voltage VGL is applied, and the high level voltage VGH is applied to the gate line GL2 in the second row.
Thereby, the transistors T1 of the pixels P (1,1) to P (1, m) in the first row are turned off. However, the voltage signals Vd (1,1) to Vd (1, m) applied until immediately before are held in the auxiliary capacitor Cs, and the currents IEL (1,1) to IEL ( 1, m) continues to flow as shown in FIG.

Further, the transistors T1 of the pixels P (2,1) to P (2, m) in the second row are turned on.
At this time, the control circuit 102 sets the display control signal to an active level as shown in FIG.
In response to the active level display control signal, the arithmetic circuit 53 turns off the transistor TP, operates the bit shift circuit 60, and outputs the image data D (1, 1) to D output from the data latch circuit 52. D (1, m) is shifted downward by 1 bit, that is, ½ image data halved is output in parallel.
The D / A converter circuit 54 converts the 1/2 image data into an analog voltage signal and applies it to the data lines DL1 to DLm via the output circuit 55 as shown in FIG.
Since the image data output from the data latch circuit 52 is halved by the arithmetic circuit 53, the voltage signals Vd (2,1) to Vd (2, m) applied to the data lines DL1 to DLm are , Approximately half of the voltage applied to the data lines DL1 to DLm immediately before, that is, the signal Vd (1,1) / 2 to Vd (1, m) / 2. For this reason, as shown in FIGS. 5F and 8, the currents IEL (2,1) to IEL () flowing in the EL elements OEL of the pixels P (2,1) to P (2, m) in the second row. 2, m) is approximately half of the currents IEL (1,1) to IEL (1, m) flowing through the EL elements OEL of the pixels P (1,1) to P (1, m) in the first row, That is, IEL (1,1) / 2 to IEL (1, m) / 2.

On the other hand, the image data of the second row (OL ₂ ) in the odd field period is supplied to the data register 51 at the timing t1, and the data register circuit 51 receives the shift signal supplied from the shift register circuit 50 in the same manner as described above. The image data D (3, 1) to D indicating the display gradation of the second row in the supplied odd field period, that is, the pixels P (3, 1) to P (3, m), at the corresponding timing. (3, m) are taken in sequentially.

  All the image data D (3, 1) to D (3, m) are stored in the data register circuit 51, and the data latch signal STB is supplied to the data latch circuit 52 at the timing t3. In response to the data latch signal STB, the data latch circuit 52 receives the image data D (3, 1) to D (3, m) taken in the data register circuit 51 as shown in FIG. Latch and output.

Here, the control circuit 102 outputs an inactive level display control signal. Therefore, in the arithmetic circuit 53, the bit shift circuit 60 does not operate, the transistor TP is turned on, and the image data output from the data latch circuit 52 is output as it is.
The D / A converter 54 converts the image data output from the arithmetic circuit 53 into an analog voltage signal and outputs the analog voltage signal, and the output circuit 55 performs a conversion process such as level shift on the supplied analog voltage signal. And applied to the data lines DL1 to DLm.

At timing t3, the gate driver 1011 sets the voltage applied to the gate line GL2 to the low level voltage VGL, and applies the high level voltage VGH to the gate line GL3 in the third row.
As a result, the transistors T1 of the pixels P (2,1) to P (2, m) in the second row are turned off. However, the voltage signals Vd (1,1) / 2 to Vd (1, m) / 2 applied until immediately before are held in the auxiliary capacitor Cs, and the current IEL (1,1) to each organic EL element OEL is retained. 1) / 2 to IEL (1, m) / 2 continue to flow.
In addition, the transistors T1 of the pixels P (3, 1) to P (3, m) in the third row are turned on.
For this reason, the voltage signals Vd (3,1) to Vd (3, m) applied by the output circuit 55 to the data lines DL1 to DLm are applied to the gate of the transistor T2 via the transistor T1.
Therefore, as illustrated in FIG. 5F, IEL (3, 1) to IEL (3, m) flow through the EL elements OEL of the pixels in the third row.

Subsequently, when a period ½ of one horizontal scanning period H of the image data, that is, the selection period ts of the gate line GL1 has passed and the timing t4 is reached, the gate driver 1011 reduces the voltage applied to the gate line GL3 to a low level. The level voltage VGL is applied, and the high level voltage VGH is applied to the gate line GL4 in the fourth row.
As a result, the transistors T1 of the pixels P (3, 1) to P (3, m) in the third row are turned off. However, the voltage signals Vd (3,1) to Vd (3, m) applied until immediately before are held in the auxiliary capacitor Cs, and the currents IEL (3,1) to IEL ( 3, m) continues to flow.
In addition, the transistors T1 of the pixels P (4, 1) to P (4, m) in the fourth row are turned on.
Further, as shown in FIG. 5D, the control circuit 102 sets the display control signal to an active level.
Therefore, the arithmetic circuit 53 turns off the transistor TP, operates the bit shift circuit 60, and outputs the image data D (1,1) to D (1, m) output from the data latch circuit 52 to 1 / Then, the D / A converter circuit 54 converts the 1/2 image data into an analog voltage signal and applies it to the data lines DL1 to DLm via the output circuit 55.
Since the image data output from the data latch circuit 52 is halved by the arithmetic circuit 53, the voltage signals Vd (4,1) to Vd (4, m) applied to the data lines DL1 to DLm are , Approximately half of the voltage applied to the data lines DL1 to DLm immediately before, that is, the signal Vd (3,1) / 2 to Vd (3, m) / 2. Therefore, as shown in the example of FIG. 5F, currents IEL (4,1) to IEL (4, m) flowing through the EL elements OEL of the pixels P (4,1) to P (4, m) in the fourth row. ) Is approximately half of the currents IEL (3,1) to IEL (3, m) flowing through the EL elements OEL of the pixels P (3,1) to P (3, m) in the third row, that is, IEL (3, 1) / 2 to IEL (3, m) / 2.
By repeating such an operation, an image based on the image data in one odd field period is displayed.
That is, in the odd field period, the current IEL (2i-1, j) corresponding to the image data flows through the organic EL element OEL of the pixel P (2i-1, j), and the organic EL of the pixel P (2i, j). A current IEL (2i−1, j) / 2 flows through the element OEL.

Accordingly, for example, as shown in FIG. 4A-2, an image based on the image data in the odd field period is transferred to the odd-numbered pixel rows PL ₁ , PL ₃ ,. Is displayed with a light emission luminance (display luminance gradation, first luminance gradation) corresponding to the above, while the same image has a panel luminance of 50% emission luminance (corrected luminance gradation, third luminance gradation). 101 are displayed in even-numbered pixel rows PL ₂ , PL ₄ ,.

(Even field display processing)
In the even field period, basically, the same operation as that in the odd field period is performed.
That is, in synchronization with the supply of the image data of the first row (EL ₁ ) in the even field period, the shift register circuit 50 is supplied with the sampling start signal STR, and the shift register circuit 50 converts the sampling start signal into The shift signal is sequentially shifted based on the shift clock signal CLK, and the shift signal is supplied to the data register circuit 51.

  As shown in FIG. 6B, the data register circuit 51 receives the pixels P (2i, 1) to P (2i) in the even-numbered rows supplied at a timing corresponding to the shift signal supplied from the shift register circuit 50. , M) sequentially captures image data D (2i, 1) to D (2i, m) instructing the display gradation.

  When the image data for one column is stored in the data register circuit 51, the data latch signal STB is supplied to the data latch circuit 52. As shown in FIG. The image data D (2i, 1) to D (2i, m) for one row captured in 51 are latched and held, and output in parallel.

Here, as shown in FIG. 6D, the control circuit 102 supplies an active level display control signal. In response to this, the arithmetic circuit 53 outputs 1/2 image data obtained by halving the image data output from the data latch circuit 52.
The D / A converter 54 converts the half image data output from the arithmetic circuit 53 into an analog voltage signal and outputs the analog voltage signal.
The output circuit 55 performs conversion processing such as level shift on the supplied analog voltage signals and applies them to the data lines DL1 to DLm as shown in FIG. Since the arithmetic circuit 53 halves the image data, the voltage signals Vd (1,1) to Vd (1, m) applied to the data lines DL1 to DLm at this time are in the second row to be described later. 1/2 of voltage signals Vd (2,1) to Vd (2, m) when driving the pixels P (2,1) to P (2, m), that is, Vd (2,1) / 2. Vd (2, m) / 2. FIG. 6E shows an example of the waveform of a voltage signal applied to the pixels P (1,1) to P (1, n) in the first row and the first column via the data line DL1 in the first column.

  On the other hand, according to the control of the control circuit, the gate driver 1011 applies the selection signal VGH to the gate line GL1 of the first row at the timing t1. Therefore, the transistors T1 of the pixels P (1,1) to P (1, m) in the first row are turned on, and the voltage signals Vd (1,1) to Vd (1, m) on the data lines DL1 to DLm are turned on. Is applied to the corresponding transistor T2, and the currents IEL (1,1) to IEL (1, m) are applied to the organic EL elements OEL of the pixels P (1,1) to P (1, m) in the first row. Flows. Since the arithmetic circuit 53 halves the image data, the current that flows at this time is a current IEL that flows through the organic EL elements OEL of the pixels P (2,1) to P (2, m) in the second row described later. 1/2 of (2,1) to IEL (2, m), that is, IEL (2,1) / 2 to IEL (2, m) / 2. FIG. 6F shows an example of a waveform of a current flowing through the organic EL element OEL of the pixel P (1,1) in the first row and the first column.

Here, when a half period of one horizontal period H of the image data, that is, when the selection period ts of the gate line GL1 has passed and the timing t2, the control circuit 102, as shown in FIG. The display control signal is set to the inactive level.
In response to the inactive level display control signal, the arithmetic circuit 53 outputs each image data output from the data latch circuit 52 as it is.
The D / A converter circuit 54 converts this data into an analog voltage signal and applies it to the data lines DL1 to DLm via the output circuit 55 as shown in FIG.
Since the image data is output as it is, the voltage signals Vd (2,1) to Vd (2, m) applied to the data lines DL1 to DLm are voltages applied to the data lines DL1 to DLm immediately before. Vd (1,1) to Vd (1, m) is almost twice as large.
At timing t2, the voltage applied to the gate line GL2 of the second row becomes the high level VGH, so that the transistors T1 of the pixels P (2,1) to P (2, m) of the second row are turned on, and the data The voltage signals Vd (2,1) to Vd (2, m) on the lines DL1 to DLm are applied to the corresponding transistor T2, and the pixels P (2,1) to P (2, m) in the second row Currents IEL (2, 1) to IEL (2, m) flow through the organic EL element OEL. At this time, as shown in FIG. 10, the current is almost twice the current flowing through the organic EL elements OEL of the pixels P (1,1) to P (1, m) in the first row.
By repeating such an operation, an image for one even field period is displayed.
That is, in the even field period, the current IEL (2i, j) corresponding to the image data flows through the organic EL element OEL of the pixel P (2i, j), and the organic EL element OEL of the pixel P (2i-1, j). Current IEL (2i, j) / 2 flows.

Thereby, for example, as shown in FIG. 4B-2, an image based on the image data in the even field period is transferred to the even-numbered pixel rows PL ₂ , PL ₄ ,. Is displayed with the light emission luminance (display luminance gradation, second luminance gradation) corresponding to the above, while the same image has a panel luminance of 50% emission luminance (corrected luminance gradation, fourth luminance gradation). 101 are displayed in odd-numbered pixel rows PL ₁ , PL ₃ ,.

As described above, according to the present embodiment, the user perceives an image displayed with a low gradation (luminance) as an afterimage of an image displayed in the previous field period. For this reason, the vertical resolution of the display device is good, and the display quality is good.
In addition, it is possible to cope with a simple process in which the luminance gradation of the image in the odd field period is reduced and displayed on the pixels in the even rows, and the luminance gradation of the image in the even field period is reduced and displayed on the pixels in the odd rows. A simple configuration can be adopted, and the cost can be reduced.

The present invention is not limited to the above embodiments, and various modifications and applications are possible. For example, the configuration and operation of the hardware shown in the above description are examples, and the present invention is not limited to these, and can be changed and applied as appropriate.
For example, as illustrated in FIG. 11, a configuration may be provided that includes a voltage adjustment circuit 56 that switches the analog voltage after DA conversion to the voltage as it is and to the voltage that is halved according to the display control signal. Alternatively, the output circuit 55 may be configured to switch the output voltage between the voltage as it is and the voltage that is halved according to the display control signal. In these cases, if the voltage value of the halved voltage is smaller than the lower limit value of the voltage value that can be output by the voltage adjustment circuit 56 or the output circuit 55, the voltage adjustment circuit 56 or In the output circuit 55, the operation of reducing the voltage to ½ is not performed. Here, the luminance gradation set in the pixel P in accordance with the lower limit value of the voltage value that can be output by the voltage adjustment circuit 56 or the output circuit 55 is the lowest luminance gradation in the pixel P, and it emits light slightly rather than no light emission. It is in the state.
Also, as shown in FIG. 12, an arithmetic circuit 53 is arranged at the input stage of the data register circuit 51, and the image data supplied to the data register circuit 51 is left as it is or in accordance with the display control signal. It may be switched whether the image data is shifted to 1 bit lower to be halved. However, in this case, it is necessary to supply image data to the data register circuit 51 for each field period.

Further, for example, an image of the k-th row (k: natural number) in the odd-numbered field period is displayed in the luminance gradation (first luminance gradation) as it is on the (2k-1) -th pixel row of the display device, The example in which the image in the k-th row in the odd field period is displayed on the second k pixel row of the display device with a lower luminance gradation (third luminance gradation) than the first luminance gradation has been shown. The image of the k-th row (k: natural number) in the odd field period may be displayed on the pixel row of the (2k-2) -th row of the display device with a gradation lower than the first luminance gradation. Further, the first luminance gradation is not the luminance gradation itself indicated by the image data, and may be corrected by increasing / decreasing by an arbitrary multiple or adding a predetermined bias value, for example. Similarly, the i-th row (i: natural number) image in the even-numbered field period is displayed at the second luminance gradation on the second i-th pixel row of the display device, and the i-th row (i: natural number) in the even-numbered field period. ) Is displayed on the pixel row of the (2i-1) th row of the display device with a luminance gradation lower than the second gradation (fourth luminance gradation). The image of i rows (i: natural number) may be displayed on the (2i + 1) th pixel row of the display device at a gradation lower than the second luminance gradation. Further, the second luminance gradation is not the luminance gradation itself indicated by the image data, but may be corrected by increasing / decreasing by an arbitrary multiple or adding a predetermined bias value.
The degree and method of reducing the first luminance gradation and the second luminance gradation are also arbitrary, and are not limited to ½ (1-bit lower shift), but are 70% and 25% (2-bit shift). Etc.
In the above-described embodiment, interlaced image data having two field periods of an odd field period and an even field period is supplied to the display device 10 as image data, and the panel unit 101 is driven based on the image data. For example, the image data may have three or more field periods, and the same operation as described above may be performed in each field period.
In the above-described embodiment, in each field period, pixels in one of the two adjacent rows of the panel unit 101 have luminance gradations corresponding to image data, and pixels in the other row have lower luminance gradations. However, for example, with respect to pixels in a predetermined number of three or more adjacent rows of the panel unit 101, pixels in one row out of the predetermined number of rows correspond to the image data. The configuration may be such that the luminance gradation is set and the remaining pixels in the other rows are driven to have a lower luminance gradation.
<Application examples of electronic devices>
Next, an electronic apparatus to which the display device 10 according to the present invention is applied will be described with reference to the drawings.
The display device 10 as described above can be favorably applied as a display device of various electronic devices such as a digital camera, a thin television, a mobile personal computer, and a mobile phone.
FIG. 13 is a perspective view illustrating a configuration example of a digital camera to which the display device according to the present invention is applied, and FIG. 14 is a perspective view illustrating a configuration example of a thin television to which the display device according to the present invention is applied. 15 is a perspective view showing a configuration example of a mobile personal computer to which the display device according to the present invention is applied. FIG. 16 is a diagram showing a configuration example of a mobile phone to which the display device according to the present invention is applied. It is.
In FIG. 13, the digital camera 210 roughly includes a main body portion 211, a lens portion 212, an operation portion 213, a display portion 214 to which the display device 10 described above is applied, and a shutter button 215. According to this, relatively good display quality can be obtained in the display unit 214 of the digital camera 210, and the cost of the digital camera 210 can be suppressed.
In FIG. 14, the thin television 220 includes a main body 221, a display unit 222 to which the display device 10 described above is applied, and an operation controller (remote controller) 223. According to this, a relatively good display quality can be obtained in the display unit 222 of the thin television 220, and the cost of the thin television 220 can be suppressed.
In FIG. 15, the personal computer 230 roughly includes a main body 231, a keyboard 232, and a display unit 233 to which the display device 10 described above is applied. Even in this case, relatively good display quality can be obtained in the display unit 233 of the personal computer 230, and the cost of the personal computer 230 can be reduced.
In FIG. 16, the mobile phone 240 roughly includes an operation unit 241, an earpiece 242, a mouthpiece 243, and a display unit 244 to which the above-described display device 10 is applied. Even in this case, relatively good display quality can be obtained in the display unit 244 of the mobile phone 240, and the cost of the mobile phone 240 can be reduced.

DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 50 ... Shift register circuit, 51 ... Data register circuit, 52 ... Data latch circuit, 53 ... Operation circuit, 54 ... D / A converter (DAC), 55 ... Output circuit, 56 ... Voltage adjustment circuit, 60 DESCRIPTION OF SYMBOLS ... Bit shift circuit, PL ... Pixel row of panel part, 101 ... Panel part, 102 ... Control circuit, 210 ... Digital camera, 211 ... Main body part, 212 ... Lens part, 213 ... Operation part, 214 ... Display part, 215 ... Shutter button, 220 ... thin television, 221 ... main body, 222 ... display, 223 ... operation controller (remote controller), 230 ... personal computer, 231 ... main body, 232 ... keyboard, 233 ... display, 240 ... mobile Telephone, 241 ... operation section, 242 ... earpiece, 243 ... mouthpiece, 244 ... display section, 1011 ... gate driver, 1 12 ... data driver

Claims (9)

A display device that displays image information according to image data,
A display panel in which pixels having light emitting elements along a plurality of rows and columns are two-dimensionally arranged;
A display driving device for driving the display panel according to the image data and displaying the image information on the display panel;
Have
The image data is an interlaced signal having a plurality of field periods;
The display driving device includes: a first pixel disposed in a specific row among a predetermined number of two or more adjacent rows of the display panel in a period corresponding to each field period of the image data. by images data corresponding to the first pixel, is operated so as to display the luminance gradation corresponding to the gradation value of the image data, the gradation value of the previous outs image data, the light emitting element The gradation value of the image data is reduced except when the first gradation value is non-light emitting and when the second gradation value is the lowest light emitting luminance when the light emitting element is emitting light. The corrected image data corrected so as to be generated is generated, and the second pixels arranged in the rows excluding the specific row among the predetermined number of rows are displayed on the first pixel by the corrected image data. Operate so that the corrected display brightness gradation is lower than the brightness gradation. Display device characterized by obtaining Bei the control circuit. The image data has an odd field period and an even field period,
The control circuit includes:
In a period corresponding to the odd field period,
The display luminance gradation of the pixels arranged in the (2k-1) th row (k: natural number) of the display panel is determined by the first image data corresponding to the (2k-1) th row of the display panel. operated to the first luminance gradation corresponding to the gradation value of the first image data,
The first image data corresponding to the (2k-1) th row of the display panel, with the display luminance gradation of the pixels arranged in one of the 2kth row or the (2k-2) th row of the display panel. the third image data corrected to decrease the tone values corresponding to the gradation value of the third image data, operates to lower than the luminance gradation of the first third luminance gradation Let
In a period corresponding to the even field period,
The display luminance gradation of the pixels arranged in the 2k rows of the display panel, the second image data corresponding to the 2k rows of the display panel, first according to the tone value of the second image data 2 brightness gradations,
The display luminance gradation of the pixels arranged in one of the (2k−1) th row or the (2k + 1) th row of the display panel is set to a level of the second image data corresponding to the 2k row of the display panel. the fourth image data corrected to reduce the tone value, corresponding to the gray scale value of the fourth image data, be operated so as to lower than said second luminance gradation fourth luminance gradation The display device according to claim 1 . A data driver that generates a driving signal for driving the pixel and supplies the driving signal to the pixel;
The image data comprises a multi-bit digital signal,
The third luminance gradation and the fourth luminance gradation are respectively set to half the luminance with respect to the first luminance gradation and the second luminance gradation,
The display device according to claim 2 , wherein the data driver includes an arithmetic circuit that generates ½ image data obtained by shifting the image data to one bit lower. The data driver includes a latch circuit that latches the image data, and a digital / analog conversion circuit that generates an analog voltage corresponding to a digital signal,
The display device according to claim 3 , wherein the arithmetic circuit is provided between the latch circuit and the digital-analog converter circuit. The data driver has a data register circuit that captures the image data,
4. The display device according to claim 3 , wherein the arithmetic circuit is connected to an input side of the data register circuit and is supplied with the image data. The data driver is configured to operate the pixel at the third luminance gradation and the fourth luminance gradation with respect to a gradation voltage having a voltage value corresponding to a gradation value of the image data. The display device according to claim 3 , further comprising a voltage adjustment circuit that generates a corrected gradation voltage having a reduced value. Electronic apparatus, characterized in that the display device according is implemented in any one of claims 1 to 6. A display panel in which pixels having light-emitting elements are two-dimensionally arranged along a plurality of rows and a plurality of columns is driven according to image data that is an interlace signal having a plurality of field periods, and the display panel receives the image data A display device drive control method for displaying image information according to
In a period corresponding to each field period of the image data, a first pixel disposed in a specific one of a predetermined number of two or more adjacent rows of the display panel is used as the first pixel. by the corresponding images data, a first display step of operating such a display luminance gradation corresponding to the gradation value of the image data,
In previous gradation value of outs image data, the second gradation value becomes the lowest light emission luminance in the state in which the light emitting element non when emission to become a first gradation value and the light emitting element emits light Except for a certain time, corrected image data corrected so as to reduce the gradation value of the image data is generated, and a second of the predetermined number of rows , excluding the specific row, is disposed in the second row . pixels, by the corrected image data, and a second display step of operating so as to lower correction display luminance gradation than the display luminance gradation of the first pixel,
A drive control method for a display device, comprising: The image data has an odd field period and an even field period,
The first display step includes
In a period corresponding to the odd field period,
The display luminance gradation of the pixels arranged in the (2k-1) th row (k: natural number) of the display panel is determined by the first image data corresponding to the (2k-1) th row of the display panel. a first luminance gradation display step of operating to the first luminance gradation corresponding to the gradation value of the first image data,
During the period corresponding to the even field period, the display luminance gradation of the pixels arranged in the 2k rows of the display panel, the second image data corresponding to the 2k rows of the display panel, the second A second luminance gradation display step that operates to obtain a second luminance gradation according to the gradation value of the image data,
The second display step includes
In a period corresponding to the odd-numbered field period, the display luminance gradation of the pixel arranged in one of the 2k-th row or the (2k-2) -th row of the display panel is set to the (2k-1) -th display pixel. ) by the third image data corrected to reduce the tone value of the first image data corresponding to the row, according to the gradation value of the third image data, lower than the first luminance gradation first A third luminance gradation display step which is operated to obtain a luminance gradation of 3,
In a period corresponding to the even field period, the display luminance gradation of the pixel arranged in one of the (2k−1) th row or the (2k + 1) th row of the display panel is set to the second kth row of the display panel. corresponding to the fourth image data corrected to reduce the tone value of the second image data, corresponding to the gradation value of the fourth image data, the second fourth lower than the luminance gradation The display device drive control method according to claim 8 , further comprising: a fourth luminance gradation display step that operates to obtain luminance gradation.

Images