JP5644539B2 - Processor, information processing apparatus, information processing method, and system startup program - Google Patents

Description

  The present invention relates to a processor, an information processing apparatus, an information processing method, and a system activation program, and in particular, a processor having a transfer function between an instruction cache and a data cache, an information processing apparatus including the processor, an information processing method using the processor, And a program to be executed by the processor.

  In the field of embedded devices, where the diversification and high functionality of devices are progressing, it is basically required that the devices can be used at the same time as the power is turned on, and the speeding up of the system start-up process is becoming even more important.

  Generally, in system startup processing, dynamic random access memory (hereinafter referred to as DRAM), which is faster than Read Only Memory (hereinafter referred to as ROM) or NOR flash memory (hereinafter referred to as NOR) at the start of execution of the system startup processing. ) Is temporarily transferred to the command and data stored in the ROM or NOR. Then, when the system startup process is performed using the instructions and data in the DRAM and a cache miss occurs during the execution of the system startup process, the Central Processing Unit (hereinafter referred to as CPU) Instead of re-acquiring from ROM, NOR, etc., a method of acquiring from DRAM is adopted.

  However, immediately after the system is started, initialization of the DRAM is not completed and there is a section in which the DRAM cannot be used. For this reason, when a cache miss hit occurs, the CPU needs to reread an instruction or data from a ROM, NOR, or the like that is slower than the DRAM in a section where the DRAM cannot be used.

  Therefore, as a method for reducing the number of times of reading from ROM, NOR, etc. when a cache miss occurs in a section where DRAM cannot be used, cache migration technology in a system having a multi-CPU has been developed.

  FIG. 8 shows a block diagram of an information processing apparatus related to the above-described cache migration. An inter-CPU cache sharing control module 803 is disposed between the CPUs 1 to N and the NOR 802. When a cache miss occurs in CPU-1, the inter-CPU cache sharing control module 803 refers to control information indicating the contents of the cache managed by the inter-CPU cache sharing control module 803 itself, and the other CPUs 2 to N. It is checked whether the necessary instruction 300 or data 301 exists in the Level 1 cache (hereinafter referred to as L1 cache). When there is an instruction 300 or data 301 that has a cache miss hit by CPU-1 in the L1 cache 804 of CPUs 2 to N, the inter-CPU cache sharing control module 803 is in the L1 cache 804 of CPUs 2 to N. The cache 300 transfers the instruction 300 or the data 301 existing in the CPU 1 to the L1 cache 804 of the CPU-1. As described above, the cache sharing control module 803 between the CPUs 1 to N operates so as to maintain coherency between the caches of the CPUs 1 to N, so that the caches can be shared among the CPUs 1 to N, and the processing speed is high. Has been realized.

  Further, as a technique related to the above-described cache migration, a technique for sharing a memory in a system having a plurality of microprocessors is disclosed in Patent Document 1.

JP 2005-050368 A

  In a system having multiple CPUs, some CPUs may not fetch instructions. For example, there may be a case where only one CPU is operating at the time of starting the system activation process, and the other CPUs are executing a waiting process such as waiting for an interrupt.

  In the system startup process, the order in which devices are initialized is determined, and the order in which values are set in the device registers when each device is initialized is also determined in advance. In order to set a value in a register of one device in parallel by a plurality of CPUs, complicated exclusive control is required, and conversely, the waiting time increases, and the benefits of parallelization cannot be enjoyed. For this reason, in the system activation process, there are many cases in which the operation is performed by one CPU instead of a plurality, and the other CPUs are executing a waiting process such as waiting for an interrupt.

  In a system employing a Harvard architecture in which an instruction cache and a data cache are separated, an instruction stored in a ROM or a NOR is placed in the instruction cache at the time of instruction fetch before the CPU executes the instruction. . That is, unless an instruction fetch is performed, the instruction stored in the ROM or NOR does not exist in the instruction cache.

  In this way, when one CPU performs the system startup process and the other CPUs are executing the waiting process, the instruction fetch is not performed in the other CPUs, so the instructions are stored in the instruction cache of the other CPUs. It has not been. Therefore, even if the cache migration technology is introduced, there arises a problem that the number of accesses to the ROM and NOR performed when a cache miss hits cannot be reduced.

  In view of the above problems, an object of the present invention is to provide a system that enables effective use of a cache without requiring complicated exclusive control.

  The processor according to the present invention includes a first storage unit that temporarily stores an instruction, a second storage unit that temporarily stores an instruction and data, and an instruction temporarily stored in the second storage unit. Transfer means for transferring to the storage means, first control for reading the instructions stored in the third storage means to the second storage means, and reading to the second recording means for the transfer means. Control means for performing second control for transferring the received instruction to the first storage means.

An information processing apparatus according to the present invention includes a third storage unit that stores instructions and data, a first storage unit that temporarily stores instructions, and a second storage unit that temporarily stores instructions and data; A transfer means for transferring an instruction temporarily stored in the second storage means to the first storage means; and a first for reading an instruction stored in the third storage means into the second storage means And a control means for performing a second control for causing the transfer means to transfer a command read into the second recording means to the first storage means. .

  The information processing method according to the present invention also includes a first load step for loading an instruction into a data cache, and a memory for storing control information describing a correspondence relationship between the loaded instruction and a load destination data cache and an address. A transfer step for transferring an instruction loaded in the data cache to the instruction cache, a notification step for notifying that the transfer is completed, and an update step for updating the control information based on the notification. Have.

  A program according to the present invention causes a first processor to execute processing related to system activation in an information processing apparatus having a plurality of processors, and a processor other than the first processor executes the first processor. And a process for loading an instruction that can be loaded into the data cache and a process for transferring the loaded instruction from the data cache to the instruction cache.

  According to the present invention, it is possible to share a cache without requiring complicated exclusive control.

It is a block diagram which shows the processor concerning this invention. It is a figure which shows the flowchart of operation | movement of the transfer module concerning this invention. It is a conceptual diagram which shows the mode of the transfer between caches. 1 is a block diagram illustrating an information processing apparatus according to a first embodiment; It is a conceptual diagram which shows the mode of loading from NOR to several CPU. It is a figure which shows the control information which the cache sharing control module between CPUs has. It is a figure which shows the control information which the cache sharing control module between CPUs has. It is a block diagram which shows the information processing apparatus concerning background art.

  The present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of a CPU according to the present invention. The system of the present invention employs a Harvard architecture, and the CPU 100 has two separate L1 caches, an instruction cache 101 and a data cache 102.

  The instruction cache 101 is a first recording unit that temporarily stores instructions executed by the control unit 103 described later. The instruction is stored in an external ROM or NOR (not shown), and is fetched into the instruction cache by instruction fetch performed before the instruction is executed. The instruction is executed after being decoded by the control unit 103.

  The data cache 102 is a second storage unit that temporarily stores the contents read from the NOR or the like. Usually, in the Harvard architecture, since the instruction system and the data system are separated, the instruction is not stored in the data cache. However, the present invention is characterized in that an instruction is also temporarily stored in the data cache 102 in a predetermined case. Note that the instruction stored in the data cache 102 is not fetched as an instruction to be executed by the control unit in this state.

  The control unit 103 loads the contents stored in a low-speed memory such as a ROM or NOR (not shown) into the data cache 102. ROM and NOR are third storage means for storing instructions and data, and the third storage means is more than an L1 cache such as an instruction cache as a first storage means and a data cache as a second storage means. Characterized by slow reading speed.

  As the loading method, an existing load instruction can be used. Here, the load instruction refers to an instruction for reading the contents stored at a specified address into the data cache. In the load instruction, it is possible to specify a plurality of addresses and read data and the like at once.

  Based on the inter-cache transfer request command, the control unit 103 outputs an inter-cache transfer request to the inter-cache transfer module 104 described later. The inter-cache transfer request instruction is a newly defined instruction and is an instruction for causing the inter-cache transfer module 104 to transfer the contents of the data cache to the instruction cache.

  The inter-cache transfer module 104 transfers the contents stored in the data cache 102 to the instruction cache 101 based on the inter-cache transfer request output from the control unit 103.

  FIG. 2 shows a flowchart of the operation of the inter-cache transfer module 104.

  The inter-cache transfer module 104 determines whether an inter-cache transfer request is output from the control unit 103 (step 1). If the inter-cache transfer request has not been received, the standby state is continuously maintained.

  When receiving the inter-cache transfer request, the inter-cache transfer module 104 reads the contents of the cache line other than the dirty bit portion from the data cache 102 (step 2). Note that an instruction loaded from NOR is stored in the data cache 102 at this stage. The instruction is not updated, and there is no dirty bit in the instruction cache 101. Therefore, since dirty bit transfer is not required, the read range is the contents of the cache line other than the dirty bit portion.

  Next, the inter-cache transfer module 104 copies the contents of the read data cache 102 to the instruction cache 101 (step 3).

  Next, the inter-cache transfer module 104 determines whether or not the read range has reached the end of the cache line (step 4). If the reading has not been completed up to the end of the cache line, the process returns to step 2 again, and the processes in steps 2 to 4 are repeated until all the reading is completed.

  When the reading to the end of the cache line is completed, the inter-cache transfer module 104 notifies an unillustrated inter-CPU cache sharing control module that the transfer from the data cache 102 to the instruction cache 101 has been completed (step). 5). Thereafter, the inter-cache transfer module 104 returns to step 1 again and enters a standby state.

  FIG. 3 shows how the contents stored in the data cache 102 are transferred to the instruction cache 101 by the inter-cache transfer module 104. The instruction stored in the data cache is associated with an address indicating a storage location and a dirty bit. The inter-cache transfer module 104 transfers the instruction stored in the data cache 102 to the instruction cache 101 as it is without changing the instruction content and storage address.

  The control unit 103 executes the load again after the inter-cache transfer, and reads the data stored in the NOR or the like into the data cache 102.

  As described above, by mounting the inter-cache transfer module 103 between the instruction cache 101 and the data cache 102 that exist separately in the CPU 100, a path is formed between two originally independent caches. . Therefore, by loading a large number of instructions at once from NOR, etc. and placing them in the data cache 102, the instructions can be loaded into the instruction cache 101 without being fetched by transferring the instructions to the instruction cache 101. Become.

  As described above, the processor of the present invention has two caches, that is, an instruction cache that is a first storage unit and a data cache that is a second storage unit. Furthermore, the processor of the present invention has transfer means for transferring the instruction temporarily stored in the second storage means to the instruction cache. The control means performs a first control for reading an instruction stored in an external memory as a third storage means into the data cache and a second control for causing the transfer means to perform transfer. By adopting such a configuration, the processor can store the instruction in the instruction cache without performing the instruction fetch.

  The transfer by the transfer means is enabled by a newly defined inter-cache transfer request command. That is, the control unit performs the second control by executing an inter-cache transfer request command that is a command for causing the transfer unit to perform the transfer. The control means performs the first control by executing a load instruction which is an instruction for reading the instruction or data stored in the third storage means into the second storage means. The control means executes the load instruction by designating a range of instructions stored in the third storage means, and executes the first control after the instruction is read into the second storage means. Can be temporarily stored in the first storage means. In this way, an inter-cache transfer request instruction is newly defined, and the control means starts the inter-cache transfer by executing the instruction.

  The transfer means transfers the instruction so that the address of the second storage means where the instruction is temporarily stored is the same as the address of the first storage means before and after the transfer. As described above, the transfer means transfers without changing the storage address in each storage means, thereby simplifying management before and after the transfer. When the transfer process is completed, the transfer unit notifies the transfer completion to the outside, thereby notifying that the inter-cache transfer of the own processor is completed and migration is possible.

  In the information processing method of the present invention, as a first step, an instruction is read from the external storage means into the data cache that is the first cache. Next, as a second step, the instruction read into the data cache is transferred to the instruction cache, which is the second cache, with the contents of the instruction and the address to be stored kept the same. Next, as a third step, it is notified that the transfer has been completed.

  As described above, when the migration of the L1 cache is performed, since many of the necessary instructions exist in the instruction cache, the cache hit rate is improved and the processing becomes faster. Hereinafter, this point will be described in detail in each embodiment.

(Embodiment 1)
FIG. 4 shows a block diagram of the information processing system in the first embodiment. This system is roughly composed of four CPUs 100 (CPU-1 to CPU-4) (hereinafter referred to as CPU100-1 to CPU100-4), a DRAM 201, a NOR 202, and an inter-CPU cache sharing control module 203. In the following, a case where the number of CPUs is four will be described. However, the number of CPUs is not limited to four, and a system having N CPUs can be expanded.

  An instruction 300 and data 301 are stored in the NOR 202 which is a low-speed memory. When the power is turned on and the system activation process is started, the instruction 300 and data 301 are transferred from the NOR 102 to the DRAM 201 which is a high-speed memory. However, the instruction 300 and the data 301 are read directly from the NOR 202 to each CPU 100 in a section where the DRAM 201 cannot be used due to initialization or the like.

  The inter-CPU cache sharing control module 203 is disposed between the NOR 202 and each CPU 100. The inter-CPU cache sharing control module 203 has an L1 cache migration function, and performs control to maintain cache coherency within each CPU 100.

  Each CPU 100 decodes and executes an instruction fetched by instruction fetch to perform control processing, arithmetic processing, and the like. Hereinafter, individual processing of each CPU 100 at the time of system startup will be specifically described. In the present embodiment, a case will be described in which only the CPU 100-1 among the four CPUs performs the system activation process. Note that the reason why one CPU performs the system startup process is that even if the system startup process is executed by a plurality of CPUs, the waiting time is increased and the benefits of parallelization cannot be enjoyed. In other words, in the device initialization process executed in the system startup process, the order of setting values in the device registers is determined, but in order to set values in the register of one device in parallel by multiple CPUs Complex exclusive control is required. Therefore, in order to avoid this complicated exclusive control, the system activation process is not performed in parallel by a plurality of CPUs 100 but is performed only by the CPU 100-1 as in the past.

  First, the operation of the CPU 100-2 to the CPU 100-4 that does not perform the system activation process when the system is activated will be described. The system startup process here refers to device initialization. Normally, when the system is started up, the order of device initialization is determined. When each device is initialized, a process for setting a value in the device register is required. Here, since the operations of the CPU 100-2 to the CPU 100-4 are the same, the operation of the CPU 100-2 will be described as a representative, and the description of the operations of the CPU 100-3 and the CPU 100-4 will be omitted.

  The control unit 103 in the CPU 100-2 executes the load instruction, loads the instruction 300 stored in the NOR 202, and stores the instruction 300 in the data cache 102. FIG. 5 shows the state of the load. Each CPU 100 executes a load instruction by designating a range to be loaded by its own CPU within a range that does not overlap with the load range of other CPUs. The range loaded by each CPU is the size of the cache line of the instruction cache 101 at the minimum, and the maximum size of the instruction cache 101 at the maximum. The loading range can be changed according to the reading speed from the NOR 202. However, if the CPU specifies a range that exceeds the performance of reading from the NOR 202, the construction of the instruction cache 201 may not be in time for the L1 cache migration process performed at the time of a cache miss hit, which will be described later, and a cache hit may not occur. Therefore, it is desirable for each CPU 100 to specify a load range within the read performance range of the NOR 202.

  The instruction 300 read by the load instruction from the NOR 202 is stored in the cache with a structure of an address and its contents without depending on the structure of the cache adopted as the system. The instruction 300 read by the load instruction from the NOR 202 is known by the inter-CPU cache sharing control module 203. The inter-CPU cache sharing control module 203 controls whether or not the necessary instruction 300 or data 301 exists in the L1 cache of the CPU 100-2 to the CPU 100-4, and indicates the contents of the cache managed by the inter-CPU cache sharing control module 203 itself. Confirm from the information.

  FIG. 6 shows an example of the control information. The inter-CPU cache sharing control module 203 records and updates such a management table, and records that the contents of the address range specified by the load instruction exist in the data cache 102.

  Next, the control unit 103 issues an inter-cache transfer request to the inter-cache transfer module 104 in order to transfer the instruction 300 stored in the data cache 102 to the instruction cache 101. This inter-cache transfer request is executed in accordance with an inter-cache transfer request instruction 400 which is a newly added instruction 300. That is, the control unit 103 fetches and fetches the inter-cache transfer request instruction 400 stored in the NOR, executes it, and issues an inter-cache transfer request to the inter-cache transfer module 104.

  Here, the inter-cache transfer request instruction 400 can simultaneously specify the transfer range. That is, it is possible to specify how many instructions 300 are transferred from the data cache 102 to the instruction cache 101 to the inter-cache transfer module 104. The inter-cache transfer module 104 transfers an instruction temporarily stored in the data cache 102 within a specified range to the instruction cache 101 based on the inter-cache transfer request.

  Since both the data cache 102 and the instruction cache 101 have a structure in which an address and its contents are paired, the inter-cache transfer module 104 transfers the contents stored in the data cache 102 to the instruction cache 101 as they are. It becomes possible. That is, the inter-cache transfer module 104 can transfer without changing the instruction that is the content stored in the data cache 102 and without changing the address in each cache.

  Next, the inter-cache transfer module 104 notifies the inter-CPU cache sharing control module 203 that the contents of the data cache 102 have been transferred to the instruction cache 101.

  When the inter-CPU cache sharing control module 203 receives the transfer completion notification from the inter-cache transfer module, it updates the control information indicating the contents of the cache managed internally.

  FIG. 7 shows the contents of the updated control information. Compared with the control information shown in FIG. 6, in the updated control information, the instruction storage destination is changed from the data cache to the instruction cache and recorded. This is because the instruction in the data cache is transferred to the instruction cache by the transfer process performed by the inter-cache transfer module 104. As described above, when the inter-CPU cache sharing control module 203 receives the transfer completion notification from the inter-cache transfer module 104, it updates the control information so that the location where the instruction is currently stored can be correctly specified.

  Next, the control unit 103 executes a load instruction, loads data from the NOR, and constructs a data cache.

  As described above, the CPU 100-2 to the CPU 100-4 operate to store instructions and data that may be necessary for system startup processing in each L1 cache in a state where cache coherency is maintained. be able to. Note that the contents of the program related to the system activation processing have been changed so that many instructions 300 from the NOR 202 are stored in the data cache 102 at once by load instructions.

  Further, as described above, the inter-cache transfer request instruction 400 is newly defined. Therefore, changes have been made to the compiler. The compiler newly defines a compile option indicating that the present invention is used. When the corresponding compile option is specified, the CPU 100-2 to CPU 100-4 other than the CPU 100-1 that performs the system startup process perform the above-described four processes (1: instruction load. 2: transfer process. 3: transfer completion notification) .4: Load data.) To generate code.

  Next, the operation of the CPU 100-1 will be described. The CPU 100-1 performs processing related to system activation such as initialization of each device at the time of system activation. Hereinafter, a process when a cache miss hit occurs during the system activation process will be specifically described.

  When a cache miss occurs, the control unit 103 in the CPU 100-1 makes a transfer request for the necessary instruction 300 or data 301 to the inter-CPU cache sharing control module 203.

  When receiving the transfer request from the CPU 100-1, the inter-CPU cache sharing control module 203 refers to the control information indicating the contents of the cache managed by itself and the storage location thereof, and requests the requested instruction 300 or data. It is confirmed whether 301 exists in the instruction cache or data cache of another CPU. When the instruction 300 and the data 301 exist in the cache of another CPU, the inter-CPU cache sharing control module 203 transfers the instruction 300 from the instruction cache of the other CPU to the instruction cache of the CPU 100-1 and also transfers the data 301. Control is performed to transfer data from the data cache of the other CPU to the data cache of the CPU 100-1. Note that if the information related to the instruction 300 or the data 301 is not recorded in the control information, the inter-CPU cache sharing control module 203 determines that inter-cache sharing is not possible, and obtains these instructions from the NOR 202. I do.

  Thus, the information processing apparatus according to the present invention is equipped with a plurality of CPUs. Each CPU has two L1 caches: an instruction cache as first storage means for temporarily storing instructions and a data cache as second storage means for temporarily storing instructions and data. Each CPU has execution means for fetching an instruction from the instruction cache and executing the instruction, and transfer means for transferring the instruction temporarily stored in the data cache to the instruction cache. The information processing apparatus includes transfer control means for controlling transfer of instructions temporarily stored in the instruction cache or data temporarily stored in the data cache between the plurality of CPUs. With this configuration, even when one CPU has a cache miss hit, an instruction stored in the instruction cache of another CPU can be transferred.

  Further, when the transfer from the data cache to the instruction cache is completed, the transfer means in each CPU outputs a transfer completion signal indicating that the transfer is completed to the transfer control means. The transfer control unit updates the control information based on the transfer completion signal. More specifically, when the notification completion signal is input, the transfer control unit changes the location where the instruction is stored from the data cache to the instruction cache for the control information related to the transferred instruction. However, since the addresses in the cache are transferred while being kept the same, the addresses described in the control information are not changed. Thus, even if transfer from the data cache to the instruction cache is performed in the CPU, which is to update the control information, the transfer control means can appropriately manage the information in the cache of each CPU.

  Further, in the system activation program according to the present invention, in an information processing apparatus having a plurality of CPUs, the first CPU is caused to execute processing related to system activation, and the CPU other than the first CPU is allowed to execute the first CPU. And a process for loading the instruction to be executed into the data cache and a process for transferring the loaded instruction from the data cache to the instruction cache. Here, the process related to system activation executed by the first CPU includes, for example, a device initialization process, and more specifically includes a process of setting a value in a register of the device. As described above, the system startup program according to the present invention causes one CPU to be in charge of system startup processing, and the other CPU fetches a part of instructions required by the CPU executing the system startup processing. It is stored in the instruction cache using the transfer function without performing the above. Therefore, since the cache can be migrated, even if a cache miss occurs in the CPU executing the system startup process, it is possible to appropriately transfer the instruction from the instruction cache of another CPU.

  As described above, in the invention of the present embodiment, the instruction 300 and the data 301 necessary for the processing of the system activation process are stored in the instruction cache and the data cache in the CPU other than the CPU that performs the system activation process. Each is stored. By performing inter-cache sharing for these instructions 300 and data 301, the startup process can be speeded up.

  In the conventional multi-CPU system, even if four CPUs are provided, the CPU-2 to CPU-4 are simply executing a waiting process such as waiting for an interrupt and the CPU-2 to the CPU-4 in the L1 cache. Since there is no instruction 300 or data 301 necessary for system startup processing, no cache hit occurs. For this reason, it is necessary to access the NOR in order to reacquire the instruction 300 and the data 301 every time a smith miss occurs, and the system startup processing time is increased by the access time to the NOR.

  However, in the multi-CPU system of the present invention, a cache-to-cache transfer module is newly installed in the CPU, and a predetermined process is also performed by the CPU that has been executing the waiting process conventionally. That is, a process of reading an instruction from the NOR or the like by a load instruction into the data cache and a process of transferring the contents of the data cache as it is to the instruction cache by an inter-cache transfer request instruction. Since these processes are different from the processes related to system activation, the processes can be performed without being aware of the CPU executing the system activation process. In other words, the CPU executing the system activation process does not need to perform complicated exclusive control, and does not need to wait for the completion of the process of another CPU. With this configuration, even a CPU that is not in charge of system startup processing can store instructions in the instruction cache.

  In other words, in the invention of the present embodiment, the instruction 300 which is the processing content of the system activation process and the data 301 necessary for the process exist in the corresponding caches in the L1 caches of the CPU-2 to the CPU-4. . Therefore, the inter-CPU cache sharing control module 203 specifies a cache in which necessary instructions 300 and data 301 are stored based on the control information, and transfers the instructions 300 and data 301 to the CPU-1 cache. With this configuration, the system activation process can be continued at a higher speed than when accessing the NOR.

  As described above, in the migration of the L1 cache performed by the inter-CPU cache sharing control module 203 that maintains the coherency between the caches when a cache miss occurs, the range of the L1 cache in the CPU to be searched for the migration target is smaller than that of the conventional CPU. Increases by a few minutes. If the range of the L1 cache in the CPU to be searched for as a migration target is increased, the cache hit rate is improved and the processing speed is increased.

  In the above description, the operation of starting the system when the power is turned on has been mainly described. However, the present invention is not limited to this, and the present invention can be used even when the embedded device is normally operating. However, in the system activation process characterized by a small number of process repetitions, the cache hit rate is low, and access to the NOR for reacquiring necessary instructions and data frequently occurs. The effect obtained is high.

  In the above description, the instruction and data storage destination is described as NOR. However, the storage destination storage means is not particularly limited as long as the instruction and data can be stored.

  In addition, the cache structure adopted by the instruction cache and data cache is, for example, the structure of any method such as the full associative method, direct map method, or set associative method. It can be. However, it is required that the instruction cache and the data cache adopt the same method.

  In the above description, the case of a multi-CPU has been described. However, the present invention can be similarly applied to a multi-core case. In this case, the CPUs 100-1 to 4 in FIG. 4 may be regarded as the cores 1 to 4, respectively.

  In the above description, the control unit and the inter-cache transfer module are described as separate blocks. However, the present invention is not limited to this, and the control unit may be configured to incorporate a transfer function. In this case, the control unit executes an inter-cache transfer request instruction newly defined by instruction fetch, and the control unit itself transfers the instruction stored in the data cache to the instruction cache according to the flow shown in FIG. Processing may be performed.

(Other embodiments)
Since the specific configuration of the information processing apparatus according to the present embodiment is the same as that of the first embodiment, it will be described with reference to FIG. That is, the CPU includes a data cache, an instruction cache, an inter-cache transfer module, and a control unit, and the information processing apparatus is a multi-CPU system including a plurality of such CPUs.

  When the power is turned on, CPU-1 starts a system activation process.

  CPU-2 to CPU-4 store instructions and data in the instruction cache 101 and the data cache 102 as in the first embodiment. That is, as a first process, a load instruction is executed to load an instruction from the NOR into the data cache. Next, the instruction stored in the data cache is transferred to the instruction cache. Then, the load instruction is executed again, and the data is stored in the data cache.

  Here, the CPU-2 to CPU-4 construct the processing contents ahead of the instruction executed by the CPU-1 in the instruction cache 101 and the data cache 102 in advance. That is, instructions and data that are required after the process currently executed by CPU-1 in the system startup process are stored in the instruction cache and the data cache, respectively.

  Next, the CPU that performs system startup processing is changed from CPU-1 to any one of CPUs 2 to 4. This change may be made voluntarily, or when the CPU 1 that has executed the system startup process cannot continue the startup process due to some trouble, the charge is transferred to the CPUs 2 to 4. Also good.

  In this way, in a system having multiple CPUs, one CPU performs system startup processing, and the other CPUs perform necessary instruction and data cache construction in advance in preparation for transfer of responsibility for system startup processing. Wait at. When the assigned transfer is performed, the transferred CPU continues the system activation process.

  In this way, by adopting a configuration in which the CPU that performs the system startup process can be changed, even if a hardware failure that cannot be recovered and continued in the CPU that was performing the system startup process occurs, another CPU In this way, the system startup process can be continued and the fault tolerance of the entire system is improved. That is, the system startup process itself can be migrated by changing the CPU that performs the system startup process to another CPU.

  In the above description, the case where only one CPU executes the system startup process has been described. However, the present invention is not limited to this. That is, in a multi-CPU system having N CPUs, some CPU groups are in charge of system startup processing while performing exclusive control, and other CPU groups execute load instructions and inter-cache transfer request instructions. It may operate so as to store an instruction required in the startup process in the instruction cache.

  The above-described program can be stored in various types of storage media that can be accessed by the computer system. The program can be transmitted via a communication medium. Here, the storage medium includes, for example, a flexible disk, a hard disk, a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD, a ROM cartridge, a battery-backed RAM memory cartridge, a flash memory cartridge, a nonvolatile RAM cartridge, and the like. . In addition, the communication medium includes a wired communication medium such as a telephone line, a wireless communication medium such as a microwave line, and the Internet.

  In the above description, transfer between the two L1 caches of the instruction cache and the data cache has been described. However, when the caches are hierarchized, the transfer can be expanded to transfer between these caches. . That is, when the Ln cache (n is an integer of 2 or more) is hierarchized, the above-described control means performs control for transferring an instruction read into the n-layer data cache to the n-layer instruction cache It may be.

  In the above description, the case of an embedded device has been described. However, the present invention is not limited to this, and the present invention can be used for various types of information processing apparatuses.

  The present invention is not limited to the above-described embodiments, and can be appropriately modified and changed without departing from the spirit of the present invention. Various embodiments are conceivable as embodiments of the present invention. For example, the following embodiments are possible.

(1) First storage means for temporarily storing instructions, second storage means for temporarily storing instructions and data, and instructions temporarily stored in the second storage means in the first storage means A transfer means for transferring; a first control for reading an instruction stored in a third storage means into the second storage means; and an instruction read into the second recording means for the transfer means. Control means for performing second control to be transferred to the first storage means.
(2) The control means performs the first control by executing a load instruction which is an instruction for reading the instruction or data stored in the third storage means into the second storage means, The processor according to (1), wherein the second control is performed by executing an inter-cache transfer request instruction that is an instruction for causing the transfer means to perform the transfer.
(3) In the transfer means, the address of the second storage means where the instruction before transfer is temporarily stored and the address of the first storage means where the instruction is temporarily stored after transfer are the same. The processor according to (1) or (2), wherein the transfer is performed as follows.
(4) The processor according to any one of (1) to (3), wherein the instruction processed by the first control and the second control is an instruction to be transferred to another processor .
(5) The processor according to any one of (1) to (4), wherein the first control and the second control are performed while another processor is executing a system startup process.
(6) Third storage means for storing instructions and data, first storage means for temporarily storing instructions, second storage means for temporarily storing instructions and data, and temporary storage in the second storage means Transfer means for transferring stored instructions to the first storage means, first control for reading instructions stored in the third storage means to the second storage means, and the transfer means An information processing apparatus comprising a plurality of processors each including control means for performing second control for transferring a command read to the second recording means to the first storage means.
(7) The system further comprises transfer control means for controlling transfer between the plurality of processors of instructions temporarily stored in the first storage means or data temporarily stored in the second storage means. The information processing apparatus according to 6).
(8) Each of the transfer means included in the plurality of processors is configured to temporarily store the address of the second storage means in which the instruction before transfer is temporarily stored and the instruction after transfer. The information processing apparatus according to (6) or (7), wherein the transfer is performed so that the address of the storage means is the same.
(9) The transfer control means includes control information associated with the contents and storage locations of instructions or data temporarily stored in the first storage means or the second storage means of the plurality of processors. The information processing apparatus according to any one of (6) to (8).
(10) The transfer means outputs a transfer completion signal indicating that the transfer is completed to the transfer control means, and the transfer control means updates the control information based on the transfer completion signal. ).
(11) a first loading step of loading an instruction into the data cache, a storage step of storing control information describing a correspondence relationship between the loaded instruction and the data cache and address of the loading destination, and loading into the data cache An information processing method comprising: a transfer step of transferring the executed instruction to an instruction cache; a notification step of notifying that the transfer has been completed; and an update step of updating the control information based on the notification.
(12) The update process updates the control information by changing the information indicating the storage location of the instruction from the data cache to the instruction cache while keeping the address the same based on the notification. Information processing method.
(13) Processing for causing the first processor to execute processing related to system startup, causing a processor other than the first processor to load an instruction that can be executed by the first processor into the data cache, and the loaded instruction And a process of transferring the data from the data cache to the instruction cache.
(14) causing the first processor to execute processing related to system startup, causing a processor other than the first processor to load an instruction that can be executed by the first processor into the data cache, and the loaded instruction And a process of transferring the data from the data cache to the instruction cache.
(15) causing the first processor to execute processing related to system activation, causing a processor other than the first processor to load an instruction that can be executed by the first processor into a data cache, and the loading A process of transferring an instruction from the data cache to the instruction cache, and changing a person in charge of executing the system activation process from the first processor to another processor based on a predetermined condition. System startup method to be executed.
(16) In an information processing apparatus having a plurality of processors, the first processor is caused to execute processing related to system activation, and instructions other than the first processor are executed by a data cache on instructions that can be executed by the first processor A program for executing a process for causing the instruction to be loaded and a process for transferring the loaded instruction from the data cache to the instruction cache.
(17) In an information processing apparatus having a plurality of processors, the first processor is caused to execute processing related to system activation, and a command other than the first processor is instructed to execute a command that can be executed by the first processor in a data cache And a process for transferring the loaded instruction from the data cache to the instruction cache, and executing the system activation process from the first processor to another processor based on a predetermined condition. A program that causes one of the processors to execute the process of changing to

100 CPU
101 instruction cache 102 data cache 103 control unit 104 inter-cache transfer module 201 DRAM
202 NOR
203 Inter-CPU cache sharing control module 300 Instruction 301 Data 800 CPU
801 DRAM
802 NOR
803 Inter-CPU cache sharing control module 804 L1 cache

Claims (10)

First storage means for temporarily storing instructions;
Second storage means for temporarily storing instructions and data;
Transfer means for transferring an instruction temporarily stored in the second storage means to the first storage means;
A first control for reading an instruction stored in a third storage means into the second storage means and an instruction read into the second storage means for the transfer means to the first storage means Control means for performing the second control to be transferred to,
Equipped with,
The instructions processed by the first control and the second control are instructions that can be transferred to another processor that is a processor that executes a predetermined process,
The processor that performs the first control and the second control without performing the predetermined process while the other processor is executing the predetermined process . The control means performs the first control by executing a load instruction that is an instruction for causing the second storage means to read an instruction or data stored in the third storage means, and the transfer means The second control is performed by executing an inter-cache transfer request instruction that is an instruction that causes the transfer to be performed.
The processor of claim 1. The transfer means transfers the address of the second storage means where the instruction before the transfer is temporarily stored and the address of the first storage means where the instruction is temporarily stored after the transfer. It is characterized by
The processor according to claim 1 or 2. Third storage means for storing instructions and data;
First storage means for temporarily storing instructions, second storage means for temporarily storing instructions and data, and transfer for transferring instructions temporarily stored in the second storage means to the first storage means Means, a first control for reading an instruction stored in the third storage means into the second storage means, and an instruction read into the second storage means for the transfer means in the first Introduction plurality Bei a processor comprising a control means for performing a second control to transfer to the storage means,
A first processor among the plurality of processors executes a predetermined process,
Processors other than the first processor that do not execute the predetermined processing perform the first control and the second control while the first processor is executing the predetermined processing,
The information processing apparatus , wherein the instructions processed by the first control and the second control are instructions that can be transferred to the first processor . Transfer control means for controlling transfer between the plurality of processors of instructions temporarily stored in the first storage means or data temporarily stored in the second storage means;
The information processing apparatus according to claim 4. Each of the transfer units included in the plurality of processors includes an address of the second storage unit in which the instruction before transfer is temporarily stored and the first storage unit in which the instruction after transfer is temporarily stored. The transfer is performed so that the address is the same as
The information processing apparatus according to claim 4 or 5. The transfer control means has control information in which the contents of the instruction or data temporarily stored in the first storage means or the second storage means of the plurality of processors and the storage location are associated with each other.
The information processing apparatus according to claim 5 . The transfer means outputs a transfer completion signal indicating that the transfer is completed to the transfer control means,
The transfer control means updates the control information based on the transfer completion signal;
The information processing apparatus according to claim 7. Of the plurality of processors, the first processor executes predetermined processing,
Among the plurality of processors, the processor other than the first processor that does not execute the predetermined process is stored in the third storage unit while the first processor is executing the predetermined process. The command stored in the second storage means, and the instruction read and temporarily stored in the second storage means is transferred to the first storage means,
An information processing method for transferring the instruction transferred to the first storage means to the first processor . In an information processing apparatus having a plurality of processors,
Causing the first processor to execute a predetermined process;
An instruction that can be executed by the first processor is loaded into a data cache to a processor other than the first processor that does not execute the predetermined process while the first processor is executing the predetermined process. Processing to transfer the loaded instruction from the data cache to the instruction cache;
A program that executes

Images