JP5645262B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a function of automatically canceling a parity error generated in a memory due to a soft error.

  In general, information processing devices perform self-diagnosis of microprocessors such as CPU, ROM, RAM, I / O ports, etc. that make up the information processing device when the power is turned on and restarted. If it can, the application program is started to perform normal business processing. In this self-diagnosis, for example, a ROM checksum test, a RAM parity error check, and the like are performed.

  In addition, when a parity error is detected in the parity error check of the RAM in the self-diagnosis, initialization is performed by writing an initial value (for example, a numerical value 0) to the entire RAM or a part of the RAM in which the parity error has occurred. Do. If a parity error has occurred due to a soft error, the parity error is eliminated by the above initialization. Thereafter, when it is determined that the other diagnosis is normal, the application program is started as described above, and normal business processing is started. As a document describing a mechanism for automatically canceling such a parity error that occurs at power-on and restart, there is, for example, Patent Document 1.

  On the other hand, when a parity error occurs in the memory during normal business processing by the application program, a method of restarting the apparatus is generally employed.

JP-A-6-250866

  With the recent high integration of memories, the influence of soft errors is increasing. For this reason, if the information processing apparatus is restarted each time a soft error occurs in the memory, the mean time between failures (MTBF) becomes extremely short.

  An object of the present invention is to provide an information processing apparatus that solves the above-described problem, that is, the problem that the average failure interval is shortened when the apparatus is restarted each time an error occurs in the memory. It is in.

An information processing apparatus according to an aspect of the present invention includes:
A memory and a microprocessor connected to the memory;
The microprocessor is
When an error occurs in the memory during execution of the application program, it is determined whether or not the usage of the memory area in which the error has occurred is a predetermined usage.
If the memory area in which the error has occurred is the predetermined usage, it is programmed to initialize the memory address in which the error has occurred and continue execution of the application program.

  Since the present invention has the configuration as described above, even if an error occurs in the memory, the memory in which the error has occurred is determined if the memory area in which the error has occurred is a use intended to be determined in advance as not affecting the operation of the apparatus. Since the address is initialized and the execution of the application program is continued, the average failure interval of the apparatus can be extended.

It is a block diagram of a 1st embodiment of the present invention. It is a flowchart which shows an example of the process performed at the time of power activation or restart of the information processing apparatus concerning the 1st Embodiment of this invention. It is a structural example of the map data used in the 1st Embodiment of this invention. 6 is a flowchart illustrating an example of processing of the information processing apparatus when a parity error occurs during execution of normal business processing in the first embodiment of the present invention. 10 is a flowchart illustrating an example of processing of the information processing apparatus when a parity error occurs during execution of normal business processing in the second embodiment of the present invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
[First embodiment]
Referring to FIG. 1, an information processing apparatus 1 according to a first embodiment of the present invention includes a microprocessor 2, a ROM 4, a RAM 5, a communication interface unit 6, an operation input unit 7, and a screen connected to the bus 3. And a display unit 8.

  The microprocessor 2 is composed of a CPU and the like, and controls the information processing apparatus 1 as a whole. The bus 3 includes an address bus, a data bus, a control line, and the like. The ROM 4 stores application programs executed by the microprocessor and constants that do not change.

  The RAM 5 stores various data processed by the microprocessor 2. In the RAM 5, one parity check bit is formed with respect to the bit length (for example, 8 bits, 16 bits, 32 bits, etc.) for each address of the RAM. The parity check bit for each address is calculated from the data to be written and written to the address when data is written to the address. In addition, the parity check bit of each address is inspected when the address is read, and if the sum of the bit data including the parity check bit is other than the predetermined side of the odd number or even number, the data at the address is destroyed. If so, a parity error interrupt is generated in the microprocessor 2 with an error address.

  A communication interface unit (hereinafter referred to as a communication I / F unit) 6 includes a dedicated data communication circuit, and performs data communication with various devices (not shown) connected via a communication line (not shown). It has a function. The operation input unit 7 includes an operation input device such as a keyboard and a mouse, and has a function of detecting an operation of the operator and outputting it to the microprocessor 2. The screen display unit 8 includes a screen display device such as an LCD or a PDP, and has a function of displaying various information such as an error message on the screen in response to an instruction from the microprocessor 2.

  FIG. 2 is a flowchart illustrating an example of processing performed when the information processing apparatus 1 is turned on or restarted. When the power is turned on or restarted, the microprocessor 2 executes an initialization process (step S1). In this initialization process, self-diagnosis of the ROM 4 and RAM 5, etc., initialization of each area of the RAM 5, copying of programs and constants stored in the ROM 4 to the RAM 5, and the like are performed. In addition, map data creation processing S2 is performed as processing related to the present invention.

  In the map data creation process S2, map data 9 representing the usage of the memory is created. FIG. 3 is a configuration example of the generated map data 9. The map data 9 in this example stores the usage of the memory area in the address range corresponding to the memory address range. For example, the first line indicates that addresses 0x0070 to 0x0100 are statistical areas. The second line indicates that addresses 0x00E0 to 0x0FFF are log areas. The third line indicates that addresses other than addresses 0x0070 to 0x0100 and 0x00E0 to 0x0FFF are areas other than the statistics area and the log area. Here, the statistical region is, for example, a transmission counter that counts the number of transmitted packets and a reception that counts the number of received packets when the information processing apparatus 1 is a communication apparatus that transmits and receives packets. An area for storing statistical information such as a counter. The log area is an area for storing various logs such as a communication log. The statistical information and the log area are areas that do not hinder normal operations of the information processing apparatus 1 even if data in the area is destroyed.

  The map data 9 shown in FIG. 3 describes its intended use only for areas that do not interfere with normal business even if the data is destroyed. However, the present invention is not limited to such map data. For example, the address range and the intended use of an area such as a program area that may interfere with normal operations when the data in the area is destroyed. The described map data may be created.

  If it is determined that the initialization process S1 is normal, the application program is started and normal business processes are executed (steps S3 and S4). On the other hand, if it is determined that there is an abnormality, the application program is not started and the apparatus stops (step S5).

  FIG. 4 is a flowchart illustrating an example of processing of the information processing apparatus 1 when a parity error occurs in the RAM 5 during execution of normal business processing. When an interrupt due to the detection of a parity error occurs (step S11), the microprocessor 2 first saves information on the application program being executed (program counter, stack pointer, etc.) (step S12).

  Next, a RAW (read-after-write) test is performed on the address of the parity error occurrence address notified by the interrupt (step S13). That is, predetermined data is written to a corresponding address and then read, and the read data is compared with the predetermined data. For example, the first RAW test for determining whether or not all the bits of the read data are the value 1 after writing the data having the value 1 for all the bits of the data, and the data for which all the bits of the data are the value 0 Is written, then a second RAW test is performed to determine whether or not all bits of the read data have a value of 0. If the parity error is temporary due to a soft error, the read data and the predetermined data match, so the RAW test succeeds. On the other hand, if the failure is a fixed failure due to a hardware failure, the read data and the predetermined data do not match, so the RAW test fails. The microprocessor 2 determines whether the cause of the parity error is a soft error based on the result of the RAW test (step S14). If the failure is not a soft error but a fixed failure, an error message prompting replacement of the failed part is displayed on the screen display unit 8 along with information on the part where the fixed failure has occurred (step S15). Finish the process.

  On the other hand, if the cause of the parity error is a soft error, the microprocessor 2 obtains the intended use by subtracting the map data of FIG. 3 by the error address (step S16), and uses the memory area at the address where the parity error has occurred. It is determined whether the usage is a predetermined usage (step S17). Here, the predetermined usage is a usage that does not hinder normal business processing even if data is destroyed. Specifically, in the case of this embodiment, the statistical area and the log area are Point to.

  If the usage of the memory area at the address where the parity error occurred is other than the statistical area and the log area, the microprocessor 2 restarts the information processing apparatus 1 (step S18). However, if the usage of the memory area at the address where the parity error has occurred is the statistical area and the log area, the microprocessor 2 initializes the memory area at the address again (step S19). Specifically, the value 0 is written at the address. Then, the saved application program information is restored and re-executed (step S20). As a result, normal operations are continued.

  As described above, according to the present embodiment, even if a parity error occurs in the RAM 5, if the memory area in which the error occurs is a use purpose that is determined in advance as not affecting the operation of the apparatus, the address where the parity error has occurred. Since the memory area is initialized and the execution of the application program is continued, the average failure interval of the apparatus can be extended.

  In addition, according to the present embodiment, a RAW test is performed on the address where a parity error has occurred, and it is determined whether or not the cause of the parity error is a soft error. The usage of the address is confirmed, the memory area is initialized and the application program is re-executed for a predetermined usage. For this reason, it is possible to avoid a risk that multiple failures occur due to initialization and re-execution of the application program despite the fixed failure.

  Further, since map data is created every time it is activated, there is an advantage that it is possible to deal with a case where a used area of a memory area is dynamically allocated. However, the present invention is not limited to the case where the map data is generated every time it is activated, and may be held in the ROM fixedly.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above embodiment, Other various addition changes are possible. For example, as shown in step S13 'of the flowchart of FIG. 5, the RAW test may be performed once or more, and in the last RAW test, data of all bits 0 that is the same value as the initialization may be written. According to this embodiment, the initialization processing of the memory area of the error occurrence address in step S19 can be omitted because the purpose has already been achieved.

DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus 2 ... Microprocessor 2
3 ... Bus 4 ... ROM
5 ... RAM
6 ... Communication I / F unit 7 ... Operation input unit 8 ... Screen display unit

Claims (7)

An information processing apparatus that includes a communication interface unit, a memory, and a microprocessor connected to the memory and the communication interface unit , and transmits and receives packets.
The microprocessor is
When an error occurs in the memory during the execution of an application program, the usage of the memory area where the error has occurred is a transmission counter that counts the number of transmitted packets, and counts the number of received packets. To determine whether it is a reception counter or communication log
If the memory area in which the error has occurred is any of the transmission counter, the reception counter, and the communication log, the memory area of the memory address in which the error has occurred is initialized and execution of the application program is resumed .
If the memory area where the error has occurred is other than the transmission counter, the reception counter, or the communication log, the information processing apparatus is programmed to restart. Information processing device. The microprocessor further includes:
The information processing apparatus according to claim 1, wherein the information processing apparatus is programmed to perform a RAW test on a memory area at a memory address where the error has occurred to determine whether the error is an intermittent failure. The RAW test is performed at least once, and in the last RAW test, the RAW test and the initialization are performed at the same time by writing the same value as the initialization in the memory area of the memory address where the error has occurred. The information processing apparatus according to claim 2 , wherein the information processing apparatus is programmed. The microprocessor further includes:
When starting up, create map data representing the usage of the memory,
Wherein in the determination information according to any one of claims 1 to 3, characterized in that the error by referring to the map data is programmed to confirm the intended use of the memory area of the memory addresses generated Processing equipment. The error information processing apparatus according to any one of claims 1 to 4, characterized in that a parity error. A memory failure recovery method executed by an information processing apparatus including a communication interface unit, a memory, and a microprocessor connected to the memory and the communication interface unit ,
The microprocessor is
When an error occurs in the memory during the execution of an application program, the usage of the memory area where the error has occurred is a transmission counter that counts the number of transmitted packets, and counts the number of received packets. To determine whether it is a reception counter or communication log
If the memory area in which the error has occurred is any of the transmission counter, the reception counter, and the communication log, the memory area of the memory address in which the error has occurred is initialized and execution of the application program is resumed .
The memory failure recovery method , wherein the information processing apparatus is restarted if the memory area where the error has occurred is any one of the transmission counter, the reception counter, and the communication log . A computer that includes a communication interface unit, a memory, and a microprocessor connected to the memory and the communication interface unit, and transmits and receives packets .
When an error occurs in the memory during the execution of the application program, the usage of the memory area where the error has occurred is a transmission counter that counts the number of transmitted packets, and counts the number of received packets. Determining whether it is a reception counter or a communication log ,
If the memory area in which the error has occurred is any one of the transmission counter, the reception counter, and the communication log, the step of reinitializing the execution of the application program by initializing the memory area of the memory address in which the error has occurred; ,
A program for executing a step of restarting the information processing apparatus if the memory area where the error has occurred is any one of the transmission counter, the reception counter, and the communication log .

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