JP5655033B2 - Sampling circuit and integration circuit - Google Patents

Description

  The present invention relates to a sampling circuit and an integrating circuit using the sampling circuit.

In recent years, when analog signals are handled in semiconductor integrated circuits, continuous time analog signals are handled as they are by operational amplifiers, resistors and capacitors, and analog signals are sampled at a predetermined sampling rate and processed in a sampling time system. There is a case to do.
In the latter case, since the input differential pair is composed of MOS transistors, a MOS operational amplifier having no input leakage current has been developed. Has appeared and has become the central technology of analog signal processing until recently.

  This switched capacitor circuit technology is not only a switched capacitor filter but also a so-called delta that combines a multi-stage integrator and an A / D converter with a small number of bits and feeds back the result of the A / D conversion to the first stage. The present invention can be applied to a sigma modulator and is also used for an oversampling delta sigma type A / D converter which has become mainstream in recent audio bands.

  Such a switched capacitor circuit has appeared in a so-called single-ended type in which only one signal path is initially provided. However, in response to the recent progress in fine processing to make a single chip with high-speed digital circuits and the demand for noise countermeasures, the signal path is divided into two systems, the positive side and the negative side, and the difference between these is expressed as the signal level. As a result, so-called fully differential switched capacitor circuits that can cancel high-speed digital noise as common-mode noise have become mainstream.

FIG. 4 shows an example of an integrating circuit provided with the general differential sampling circuit cited in FIG.
In FIG. 4, the sampling capacitors 117, 118, 119, and 120 all have the same capacitance value. Here, the capacitance values of the sampling capacitors 117 to 120 are represented as “(½) Cs”.

The capacitance values of the integrating capacitors 121 and 122 are set to arbitrary magnitudes so as to appropriately set the integrator cutoff. Here, the capacitance values of the integrating capacitors 121 and 122 are represented as Ci.
The switches 401, 403, 406, 408, 410, 412, 414, 416 are driven by a clock signal Φ1 supplied by a clock generator (not shown), and the switches 402, 404, 405, 407, 409, 411, 413, 415 are It is driven by a clock signal Φ2 supplied by a clock generator (not shown). The sampling capacitors 117 to 120 operate as the switches 401 to 416 operate according to the clock signals Φ1 and Φ2, and thereby the positive signal input terminal 11 to which the positive input signal Vip composed of the voltage signal is input or the negative input signal composed of the voltage signal. The negative signal input terminal 12 to which Vin is input is connected to the fully differential operational amplifier 123 or the terminal 15 to which the analog common voltage Vcom is supplied.

That is, the sampling capacitors 117 and 118 sample the potential difference “Vip−Vcom” between the positive input signal Vip and the analog common voltage Vcom in a section in which the clock signal Φ1 is at the H level, and in a section in which the clock signal Φ2 is in the H level. The electric charge is transferred to the integrating capacitor 121 with a voltage of “Vcom−Vin”.
Also, the sampling capacitors 119 and 120 sample the potential difference “Vin−Vcom” during the interval in which the clock signal Φ1 is at the H level, and the integration capacitor 122 with the voltage “Vcom−Vip” in the interval in which the clock signal Φ2 is at the H level. Transfer charge to

  As described above, the connection relationship between the sampling capacitor 117 and the switches 401, 402, 409, and 410 and the connection relationship between the sampling capacitor 118, the switches 403, 404, 411, and 412 are equivalent, and the sampling capacitance (1/2) Cs. X2 = equivalent to replacing with one sampling capacity of Cs. The connection relationship between the sampling capacitor 119 and the switches 405, 406, 413 and 414 is equivalent to the connection relationship between the sampling capacitor 120 and the switches 407, 408, 415 and 416, and the sampling capacity (1/2) Cs × 2 = Equivalent to replacing with one sampling capacity of Cs.

Here, the transfer function in the Z region of the integrating circuit shown in FIG. 4 is expressed by the following equations (1) and (2).
Vop (0) -Von (0)
= Cs / Ci [{Vip (0) -Vin (-1/2)}
-{Vin (0) -Vip (-1/2)}] (1)
Vop-Von
= Cs / Ci {1 + Z ^(−1/2) } (Vip−Vin) (2)
FIG. 5 illustrates the frequency characteristic of the equation (2). In FIG. 5, the horizontal axis represents the normalized frequency (× π rad / sample), and the vertical axis represents the gain (dB). In FIG. 5, the horizontal axis is normalized so that 2 · FS = 1.0 with respect to the sampling frequency FS.

As can be seen from the equation (2), by using the sampling method shown in FIG. 4, a first-order LPF (Low Pass Filter) can be formed for a signal in the vicinity of the FS that is turned back by the sampling theorem.
In the sampling circuit shown in FIG. 4, the clock signals Φ1 and Φ2 are signals that change on and off at the timing shown in the timing chart shown in FIG. 2, for example, and both the clock signals Φ1 and Φ2 are at the H level. It is a non-overlapping clock signal with no period.

JP 2002-261614 A

When the integrating circuit including the differential sampling circuit shown in the prior art is used, a first-order LPF is formed from the sampling frequency characteristics as described above.
However, when a signal having a large interference wave is input in the vicinity of the sampling frequency FS, it is necessary to insert an anti-aliasing filter for suppressing the interference wave in the input unit in order to prevent noise contamination due to the folding theorem. There is an inevitable increase in circuit size and power consumption.

  The present invention has been made in view of the above, and it is an object of the present invention to provide a sampling circuit capable of preventing noise mixing due to the folding theorem without increasing the circuit scale and the like and an integration circuit including the sampling circuit. It is said.

  To achieve the above object, a sampling circuit according to claim 1 of the present invention includes a first sampling capacitor for accumulating charges generated by an input signal input to the first input terminal or the second input terminal. , A second sampling capacitor, a third sampling capacitor, a fourth sampling capacitor, a first switch group that charges and discharges the first sampling capacitor, and a second sampling capacitor that charges and discharges the second sampling capacitor. A second switch group, a third switch group that charges and discharges the third sampling capacitor, a fourth switch group that charges and discharges the fourth sampling capacitor, a negative input terminal, and a positive input terminal The first switch group (switches 101, 102, 109 and 110) connects the first sampling capacitor (sampling capacitor 117) between the first input terminal and a reference voltage source at a first timing, and the second input terminal at a second timing. And the negative input terminal of the fully differential operational amplifier, and the second switch group (switches 105, 106, 113, and 114) includes the second sampling capacitor (sampling capacitor 119) and the second sampling capacitor. At the first timing, it is connected between the second input terminal and the reference voltage source, and at the second timing, it is connected between the first input terminal and the positive input terminal of the fully differential operational amplifier. , The third switch group (switches 103, 104, 111 and 112) includes the third sampling capacitor (sampling capacitor). 18) is connected between the second input terminal and the negative input terminal of the fully differential operational amplifier at the first timing, and the first input terminal and the reference voltage source at the second timing. And the fourth switch group (switches 107, 108, 115, and 116) connects the fourth sampling capacitor (sampling capacitor 120) to the first input terminal at the first timing. Between the second input terminal and the reference voltage source at the second timing, the first timing, and the second input terminal of the fully differential operational amplifier. These timings are alternately generated.

  According to a second aspect of the present invention, there is provided an integrating circuit comprising: the sampling circuit according to the first aspect; a first integrating capacitor connected between a negative input terminal and a positive output terminal of the fully differential operational amplifier; And a second integration capacitor connected between a positive input terminal and a negative output terminal of the fully differential operational amplifier.

  According to the present invention, the first to fourth input terminals between the first and second input terminals to which positive and negative input signals are input and the positive input terminal, the negative input terminal, or the reference voltage source of the fully differential operational amplifier. A sampling circuit having a second-order LPF characteristic with respect to an input signal in the vicinity of the sampling frequency was configured by adjusting a connection pattern when connecting the sampling capacitors. Therefore, the sampling circuit can prevent noise from being mixed by the folding theorem. Therefore, by configuring the integration circuit including such a sampling circuit, it is possible to prevent the noise from being mixed due to the folding theorem while suppressing an increase in circuit scale and power consumption.

It is a circuit diagram which shows an example at the time of applying the sampling circuit by this invention to an integration circuit. It is an example of a timing chart of clock signals Φ1 and Φ2. It is a characteristic view showing the frequency characteristic of the sampling circuit shown in FIG. It is an example of the integrating circuit provided with the conventional sampling circuit. It is a characteristic view showing the frequency characteristic of the conventional sampling circuit shown in FIG.

Hereinafter, an example of the sampling circuit of the present invention will be described with reference to the drawings.
FIG. 1 shows an example of an integrating circuit 1 having a sampling circuit 2 of the present invention.
An integrating circuit 1 shown in FIG. 1 is a fully differential integrating circuit using a differential sampling method.
As shown in FIG. 1, a fully differential integration circuit 1 according to the present invention includes sampling capacitors 117, 118, 119 and 120, and switches 101 to 108 for charging and discharging the sampling capacitors 117 to 120. 109 to 116 and a fully differential operational amplifier 123 including integration capacitors 121 and 122. Sampling capacitors 117 to 120, switches 101 to 116, and a fully differential operational amplifier constitute sampling circuit 2.

In FIG. 1, 11 is a positive signal input terminal to which a positive input signal Vip consisting of a voltage signal is input, 12 is a negative signal input terminal to which a negative input signal Vin consisting of a voltage signal is input, and 13 is a voltage A positive signal output terminal from which a positive output signal Vop composed of a signal is output, and a negative signal output terminal from which a negative output signal Von composed of a voltage signal is output.
That is, the sampling circuit 2 samples the fully differential input signal that is the difference between the positive input signal Vip input to the positive signal input terminal 11 and the negative input signal Vin input to the negative signal input terminal 12 to perform sampling. The circuit 2 performs a predetermined sampling operation to output a positive output signal Vop from the positive signal output terminal 13 and a negative output signal Von from the negative signal output terminal 14, respectively. The difference between these positive and negative output signals Vop and Von is all Output as a differential output signal.

The fully differential operational amplifier 123 includes a negative input terminal 123in and a positive input terminal 123ip, a positive output terminal 123op, and a negative output terminal 123on.
The integration capacitor 121 is connected between the negative input terminal 123in and the positive output terminal 123op, and the integration capacitor 122 is connected between the positive input terminal 123ip and the negative output terminal 123on.

  The switches 101, 102, 109, and 110 are switches that charge and discharge the sampling capacitor 117. One end of the sampling capacitor 117 is connected to the positive signal input terminal 11 via the switch 101 and via the switch 102. To the negative signal input terminal 12. The other end of the sampling capacitor 117 is connected to the negative input terminal 123in of the fully differential operational amplifier 123 and one end of the integrating capacitor 121 via the switch 109, and the terminal 15 to which the analog common voltage Vcom is applied via the switch 110. Connected to.

  The switches 103, 104, 111, and 112 are switches that charge and discharge the sampling capacitor 118. One end of the sampling capacitor 118 is connected to the positive signal input terminal 11 via the switch 103 and via the switch 104. To the negative signal input terminal 12. The other end of the sampling capacitor 118 is connected to the negative input terminal 123in of the fully differential operational amplifier 123 and one end of the integrating capacitor 121 via the switch 111, and is connected to the terminal 15 via the switch 112.

  Switches 105, 106, 113, and 114 charge and discharge the sampling capacitor 119, and one end of the sampling capacitor 119 is connected to the positive signal input terminal 11 via the switch 105 and via the switch 106. To the negative signal input terminal 12. The other end of the sampling capacitor 119 is connected to the positive input terminal 123ip of the fully differential operational amplifier 123 and one end of the integration capacitor 122 through the switch 113, and to the terminal 15 through the switch 114.

  The switches 107, 108, 115 and 116 are switches for charging and discharging the sampling capacitor 120. One end of the sampling capacitor 120 is connected to the positive signal input terminal 11 via the switch 107 and via the switch 108. To the negative signal input terminal 12. The other end of the sampling capacitor 120 is connected to the positive input terminal 123ip of the fully differential operational amplifier 123 and one end of the integration capacitor 122 via the switch 115, and to the terminal 15 via the switch 116.

The other end of the integrating capacitor 121 and the output terminal 123 op of the fully differential operational amplifier 123 are connected to the positive signal output terminal 13. Similarly, the other end of the integrating capacitor 122 and the output terminal 123 on of the fully differential operational amplifier 123 are connected to the negative signal output terminal 14.
In the sampling circuit 2 having such a configuration, the sampling capacitors 117 to 120 have the same capacitance value, and here, the capacitance value is represented by (1/2) Cs. The integrating capacitors 121 and 122 have the same capacitance value and are set to an arbitrary size so as to appropriately set the cutoff of the integrating circuit 1. Here, the capacitance values of the integrating capacitors 121 and 122 are represented as Ci.

The switches 101, 104, 106, 107, 110, 111, 114 and 115 are driven by a clock signal Φ1 supplied by a clock generator (not shown). The switches 102, 103, 105, 108, 109, 112, 113, 116 are driven by a clock signal Φ2 supplied by a clock generator (not shown).
FIG. 2 shows a timing chart of the clock signals Φ1 and Φ2 supplied to the switches 101-116. As can be seen from FIG. 2, the clock signals Φ1 and Φ2 are alternately H level signals, and are non-overlapping clock signals having the same period of H level and no period of both H levels.

In FIG. 2, (a) represents the timing of the clock signal Φ1, and (b) represents the timing of the clock signal Φ2.
The sampling capacitor 117 samples the potential difference of “Vip−Vcom” during the interval in which the clock signal Φ1 is at the H level, and charges the integration capacitor 121 with the voltage of “Vcom−Vin” during the interval in which the clock signal Φ2 is at the H level. Forward. The sampling capacitor 118 samples the potential difference of “Vip−Vcom” during the period when the clock signal Φ2 is at the H level, and charges the integration capacitor 121 with the voltage of “Vcom−Vin” during the period when the clock signal Φ1 is at the H level. Forward.

Further, the sampling capacitor 119 samples the potential difference of “Vin−Vcom” during the interval in which the clock signal Φ1 is at the H level, and supplies the integration capacitor 122 with the voltage of “Vcom−Vip” in the interval in which the clock signal Φ2 is at the H level. Transfer charge.
The sampling capacitor 120 samples a potential difference of “Vin−Vcom” during a period when the clock signal Φ2 is at the H level, and charges the integration capacitor 122 with a voltage of “Vcom−Vip” during a period when the clock signal Φ1 is at the H level. Forward.

Here, the transfer functions in the Z region of the integrating circuit 1 shown in FIG. 1 are shown in the following equations (3) and (4).
Vop (0) -Von (0)
= Cs / 2Ci [{Vip (0) + 2Vip (−1/2) −Vip (−1)}
-{Vin (0) + 2Vin (-1/2) -Vin (-1)}] (3)
Vop-Von
= Cs / 2Ci (1 + 2Z- ^{1 / 2} + 1Z- ¹ ) (Vip-Vin)
= Cs / 2Ci (1 + Z ^−1/2 ) ² (Vip−Vin) (4)
FIG. 3 shows the frequency characteristics of the transfer function expressed by the equation (4). In FIG. 3, the horizontal axis represents normalized frequency (× π rad / sample), and the vertical axis represents gain (dB). In FIG. 3, the horizontal axis is normalized so that 2 · FS = 1.0 with respect to the sampling frequency FS.

As can be seen from the equation (4), it can be seen that by using the sampling method shown in FIG. 4, a second order LPF (Low Pass Filter) can be formed for a signal in the vicinity of the sampling frequency FS turned back by the sampling theorem. That is, as shown in FIG. 4, the attenuation effect in the vicinity of the sampling frequency FS can be improved.
As described above, by using the sampling circuit 2 shown in FIG. 1, a secondary LPF can be formed with respect to a conventional primary LPF during sampling. For this reason, when a signal having a large interference wave is input in the vicinity of the sampling frequency FS, an anti-aliasing filter needs to be inserted in the input unit in order to suppress the interference wave in order to prevent noise contamination by the aliasing theorem. However, as described above, the use of the sampling circuit 2 can improve the attenuation effect in the vicinity of the sampling frequency FS, so that the performance for attenuation of the interference wave required for the anti-aliasing filter is relaxed. can do.

Therefore, the circuit scale and power consumption of the anti-aliasing filter can be greatly reduced, and as a result, the circuit scale and power consumption of the entire sampling circuit 2 and further the entire integration circuit 1 can be reduced.
Further, in the sampling circuit 2, a secondary LPF can be configured by changing the sampling timing by the sampling capacitors 117 to 120. Therefore, the primary LPF and the secondary LPF can be formed by changing the sampling timing according to the use of the sampling circuit 2.

  In the above embodiment, the positive signal input terminal 11 corresponds to the first input terminal, the negative signal input terminal 12 corresponds to the second input terminal, the sampling capacitor 117 corresponds to the first sampling capacitor, The sampling capacitor 119 corresponds to the second sampling capacitor, the sampling capacitor 118 corresponds to the third sampling capacitor, and the sampling capacitor 120 corresponds to the fourth sampling capacitor.

The switches 101, 102, 109, and 110 correspond to the first switch group, the switches 105, 106, 113, and 114 correspond to the second switch group, and the switches 103, 104, 111, and 112 are the third switch group. Corresponding to the switch group, the switches 107, 108, 115 and 116 correspond to the fourth switch group.
The timing at which the clock signal Φ1 becomes H level corresponds to the first timing, the timing at which the clock signal Φ2 becomes H level corresponds to the second timing, and the terminal 15 to which the analog common voltage Vcom is supplied is a reference. Corresponding to the voltage source, the integrating capacitor 121 corresponds to the first integrating capacitor, and the integrating capacitor 122 corresponds to the second integrating capacitor.

11, 12 Input terminals 13, 14 Output terminals 101-116 Switches 117-120 Sampling capacitors 121, 122 Integration capacitors 123 Fully differential operational amplifier

Claims (2)

A first sampling capacitor, a second sampling capacitor, a third sampling capacitor, and a fourth sampling capacitor for accumulating charges generated by an input signal input to the first input terminal or the second input terminal;
A first switch group for charging and discharging the first sampling capacitor;
A second switch group for charging and discharging the second sampling capacitor;
A third switch group for charging and discharging the third sampling capacitor;
A fourth switch group for charging and discharging the fourth sampling capacitor;
A fully differential operational amplifier having a negative input terminal and a positive input terminal, and
The first switch group connects the first sampling capacitor between the first input terminal and a reference voltage source at a first timing, and the second input terminal at a second timing. Connect between the negative input terminal of the fully differential operational amplifier,
The second switch group connects the second sampling capacitor between the second input terminal and the reference voltage source at the first timing, and the first switching capacitor at the second timing. Connect between the input terminal and the positive input terminal of the fully differential operational amplifier,
The third switch group connects the third sampling capacitor between the second input terminal and the negative input terminal of the fully differential operational amplifier at the first timing, and the second timing. Then, connecting between the first input terminal and the reference voltage source,
The fourth switch group connects the fourth sampling capacitor between the first input terminal and the positive input terminal of the fully differential operational amplifier at the first timing, and the second timing. Then, connecting between the second input terminal and the reference voltage source,
The sampling circuit according to claim 1, wherein the first timing and the second timing occur alternately. A sampling circuit according to claim 1;
A first integrating capacitor connected between a negative input terminal and a positive output terminal of the fully differential operational amplifier;
A second integrating capacitor connected between a positive input terminal and a negative output terminal of the fully differential operational amplifier;
An integration circuit comprising:

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