JP5655051B2 - Switching amplifier - Google Patents

Description

  The present invention relates to a switching amplifier designed to reduce noise.

Conventionally, for example, a switching amplifier has been used as a circuit for amplifying an input signal such as an audio signal (see, for example, Patent Document 1 and Patent Document 2).
FIG. 11 is a circuit diagram illustrating the switching amplifier of Patent Document 1 as the driving device 70. In FIG. 11, a driving device 70 includes a triangular wave generator 71 and two kinds of level signals POS that alternately and alternately change an upper level and a lower level around a triangular wave from the triangular wave generator 71 and a signal reference level. Comparators 72 and 73 that compare NEG, a gate drive circuit 74 that generates drive signals V1P and V1N from a pulse width modulation signal CMP1 that is the output of the comparator 72, and a pulse width modulation signal that is the output of the comparator 73 A delay circuit 75 that delays CMP2 for a predetermined time, a gate drive circuit 76 that generates drive signals V2P and V2N from a delay signal CMP2D that is an output of the delay circuit 75, and an output that is driven by outputs V1P and V1N of the gate drive circuit 74. Half-bridge amplifier 77 for generating POUT and outputs V2P and V of gate drive circuit 76 It includes a half bridge amplifier 78 to generate a driven output NOUT, the by N. The triangular wave generated by the triangular wave generator 71 is a signal wave in which the rising slope / falling slope waveforms are symmetric.

The triangular wave generator 71 and the comparator 72 constitute a positive PWM circuit, and the triangular wave generator 71 and the comparator 73 constitute a negative PWM circuit.
Here, when the delay circuit 75 is not provided, when the rising or falling timings of the output POUT and the output NOUT coincide with each other because the input signal is very small or in a no-signal state, “POUT A differential pulse consisting of -NOUT "cannot be generated, and a regular operation cycle cannot be maintained. In this way, when regular operation cannot be maintained, a noise spectrum that does not occur when regular operation is performed is generated, and the audible bandwidth of this noise vector is reduced. Noise will be heard by the user.

  In order to prevent the generation of the noise spectrum, a delay circuit 75 is inserted on the output side of the positive or negative PWM circuit, or in the case of FIG. Instead of using CMP2 as a pulse width modulation signal, a differential pulse is regularly generated by using CMP2D obtained by delaying the output signal CMP2 of the comparator 73 as a pulse width modulation signal.

FIG. 12 is a diagram showing signal waveforms at various parts, showing an example of the operation of the driving device 70 when the delay circuit 75 is inserted.
When the two level signals POS and NEG are equivalent to the signal reference level as shown in FIG. 12A, the level signals POS and NEG are output by the comparators 72 and 73 as shown in FIG. Is compared with the triangular wave signal TRIANGLE, the rise timing and fall timing of the output signals CMP1 and CMP2 coincide. Therefore, if the output signal CMP2 is not delayed by the delay circuit 75, the switching timings of the drive signals V1P, V1N, V2P, and V2N match, and as a result, the switching timings of the outputs POUT and NOUT match, and POUT− A differential pulse composed of NOUT cannot be generated.

  However, by inserting the delay circuit 75, the output signal CMP2 of the comparator 73 is delayed and input to the gate drive circuit 76 as CMP2D (FIG. 12C), so that the drive signals V1P and V1N and V2P and The switching timing is shifted by V2N (FIG. 12D). Therefore, the switching timing between the outputs POUT and NOUT is shifted (FIG. 12E), and as shown in FIG. 12F, a differential pulse composed of POUT−NOUT is generated.

US6614297B2 specification JP 2006-94158 A

As described above, by providing the delay circuit 75, a differential pulse can be generated.
However, there is a manufacturing variation in each element constituting the driving device 70, and the edge may vary due to the manufacturing variation.
That is, as shown in FIG. 13A, even if the same two level signals POS and NEG and the signal reference level as those in FIG. 12 are input to the comparators 72 and 73, the manufacturing variations of the comparators 72 and 73 are different. For example, the switching timings of the output signals CMP1 and CMP2 of the comparators 72 and 73 may not match and may vary (FIG. 13B).

  Thus, when variation occurs, a CMP2D obtained by delaying the output signal CMP2 of the comparator 73 is obtained, and the gate drive circuit 74, using the output signal CMP1 and the delayed CMP2D (FIG. 13C), Even if 76 is driven, there is a possibility that the switching timings of the drive signals V1P, V1N, V2P, and V2N coincide. As shown in FIG. 13D, for example, when the rising timings of the drive signals V1P, V1N, V2P, and V2N match, the falling timings of the outputs POUT and NOUT match (FIG. 13E) As a result, as shown in FIG. 13 (f), a negative differential pulse composed of POUT-NPUT is not generated, and only a positive differential pulse is generated.

  Therefore, in order to reliably avoid the coincidence of the rising / falling timings of the outputs POUT and NPUT, the delay circuit 75 needs to delay the output signal CMP2 of the comparator 73 by a certain amount in consideration of manufacturing variations. There is. In this way, delaying the output signal CMP2 to a certain extent means that the current pulse width applied to the load widens, so that more current than necessary is supplied to the load. Increase current consumption.

  The present invention has been made paying attention to the above-mentioned conventional problems, and an object thereof is to provide a switching amplifier that reliably generates a differential pulse without increasing current consumption.

  One aspect of the present invention provides a first PWM control signal and a second PWM control for driving a first half bridge amplifier and a second half bridge amplifier (eg, half bridge amplifiers 17, 18 shown in FIG. 1). Switching timing of the PWM control signal generation unit (for example, the triangular wave generator 11, the comparators 12 and 13 shown in FIG. 1) that generates a signal, and the first and second PWM control signals generated by the PWM control signal generation unit Based on the first and second PWM control signals after adjustment by the switching timing adjustment unit (for example, the edge detection / delay insertion circuit 14 shown in FIG. 1) and the switching timing adjustment unit. A drive circuit for driving the first and second half-bridge amplifiers (for example, gate drive circuits 15 and 16 shown in FIG. 1), The load is driven in accordance with the potential difference between the output ends of the first half-bridge amplifier and the second half-bridge amplifier, and the switching timing adjustment unit is configured to output the first and second PWM control signals. Among them, a rising mask signal generation unit (for example, a PG rising detection unit shown in FIG. 5) that generates a rising mask signal that continues until a predetermined delay time elapses from the rising timing of the one PWM control signal whose rising timing precedes. 53 and an NG rising detection unit 62), and a rising delay insertion unit (for example, NAND circuits 51 and 61 shown in FIG. 5) for delaying the rising timing of the other PWM control signal based on the other PWM control signal and the rising mask signal. ) And the first and second PWM control signals Among them, a falling mask signal generation unit (for example, a PG shown in FIG. 5) that generates a falling mask signal that lasts from the falling timing of one PWM control signal that precedes the falling timing until the delay time elapses. A falling edge detecting section 57 and an NG falling edge detecting section 66) and a falling delay inserting section (for example, FIG. 5) for delaying the falling timing of the other PWM control signal based on the other PWM control signal and the falling mask signal. And a NOR circuit 55 and 64) shown in FIG.

Of the first and second PWM control signals generated by the PWM control signal generation unit, a delay unit that delays the switching timing of one predetermined PWM control signal with respect to the other PWM control signal (for example, Delay elements 52 and 56) shown in FIG. 5 may be provided.
The switching timing adjustment unit uses the first and second PWM control signals as a first PWM control signal and a signal obtained by delaying the one PWM control signal by the delay unit. The switching timing of the control signal may be adjusted.
The delay unit may adjust the rising mask signal or the falling mask signal.

  According to the present invention, the PWM control of one of the first and second PWM control signals for each of the rising timing and falling timing of the first PWM control signal and the second PWM control signal. The switching timing of the other PWM control signal is delayed until a preset delay time elapses from the switching timing of the signal. Therefore, the rising edge and falling edge of the first and second PWM control signals are shifted from each other. As a result, even if the switching timings of the first PWM control signal and the second PWM control signal coincide with each other, between the rising and falling edges of the first PWM control signal and the second PWM control signal. A predetermined delay time can be provided, that is, a differential pulse can be generated periodically. In addition, the pulse width of the differential pulse only needs to be recognized as a pulse, and may be relatively narrow. Therefore, it is possible to suppress an increase in current consumption due to generation of the differential pulse periodically. It is possible to prevent noise from being generated due to an irregular differential pulse while suppressing a decrease in the above.

It is a circuit block diagram for demonstrating the switching amplifier of one Embodiment of this invention. It is a circuit diagram which shows an example of a gate drive circuit. It is an example of the load circuit diagram of the switching amplifier of FIG. FIG. 2 is a signal waveform diagram illustrating an example of a signal waveform of each unit in FIG. 1. It is a circuit diagram showing an example of an edge detection / delay insertion circuit. It is a signal waveform diagram which shows an example of the signal waveform of each part of FIG. 1 when a switching timing corresponds. It is a signal waveform diagram which shows an example of the signal waveform of each part of FIG. 1 when the edge difference of switching timing is small. FIG. 2 is a signal waveform diagram illustrating an example of a signal waveform of each part in FIG. 1 when the edge difference in switching timing is large. It is a signal waveform diagram which shows an example of the signal waveform of each part of FIG. 1 when the edge difference of switching timing is small. FIG. 2 is a signal waveform diagram illustrating an example of a signal waveform of each part in FIG. 1 when the edge difference in switching timing is large. It is an example of the circuit block diagram for demonstrating the conventional switching amplifier. FIG. 12 is a signal waveform diagram illustrating an example of a signal waveform of each part of the switching amplifier of FIG. 11. FIG. 12 is a signal waveform diagram illustrating an example of a signal waveform of each part of the switching amplifier of FIG. 11.

Hereinafter, an example of the switching amplifier of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram for explaining the switching amplifier according to the present embodiment, and illustrates the switching amplifier as a driving device.
In FIG. 1, the switching amplifier constituting the driving device 1 includes a triangular wave generator 11, comparators 12 and 13, an edge detection / delay insertion circuit 14, gate drive circuits 15 and 16, and half bridge amplifiers 17 and 18. With.

The triangular wave generator 11 generates a triangular wave signal in which the rising slope and falling slope waveforms are symmetrical.
The comparator 12 is, for example, a level signal among the triangular wave signal output from the triangular wave generator 11 and two kinds of level signals POS and NEG that alternately and alternately change the upper level and the lower level around the signal reference level. POS is input, the level signal POS is input to the inverting input terminal, the triangular wave signal is input to the non-inverting input terminal, and the comparison result is output to the edge detection / delay insertion circuit 14 as the comparator output CMP1.

  Similarly, the comparator 13 is a signal different from the level signal input to the comparator 12 among the triangular wave signal output from the triangular wave generator 11 and the two types of level signals POS and NEG, for example, the level signal NEG. , The level signal NEG is input to the inverting input terminal, the triangular wave signal is input to the non-inverting input terminal, and the comparison result is output to the edge detection / delay insertion circuit 14 as the comparator output CMP2.

The edge detection / delay insertion circuit 14 outputs a signal obtained by delaying either the comparator output CMP1 or CMP2 as the pulse width modulation signals PG and NG in accordance with the timing of the edges of the comparator outputs CMP1 and CMP2. .
The pulse width modulation signal PG is input to the gate drive circuit 15 as a positive control signal, and the pulse width modulation signal NG is input to the gate drive circuit 16 as a negative control signal. The configuration of the edge detection / delay insertion circuit 14 will be described later.

The gate drive circuits 15 and 16 generate positive drive signals V1P and V1N and negative drive signals V2P and V2N for driving the half bridge amplifiers 17 and 18 based on the pulse width modulation signals PG and NG. . The generated drive signals are output to the corresponding half-bridge amplifiers 17 and 18, respectively.
FIG. 2 is a configuration diagram illustrating an example of the gate drive circuits 15 and 16. These gate drive circuits 15 and 16 have the same configuration. In FIG. 2, the gate drive circuit 15 for positive electrode will be described.

As shown in FIG. 2, the gate drive circuit 15 includes a positive signal generation unit 21 that generates a V1P signal and a negative signal generation unit 22 that generates a V1N signal.
In the positive signal generator 21, the sources of a pair of P-channel MOS transistors M11 and M12 connected in parallel are connected to the power supply Vdd, and the drain is connected to the drain of the N-channel MOS transistor M13. The N channel type MOS transistor M13 is grounded via the N channel type MOS transistor M14.

The pulse width modulation signal PG from the edge detection / delay insertion circuit 14 is input to the gates of the MOS transistors M11 and M14. A drive signal V1N generated by a negative signal generator 22 described later is input to the gates of the MOS transistors M12 and M13 after being delayed by an inverter as a delay element 31.
Then, the voltage at the node N1, which is a connection point between the MOS transistors M11 and M12, and the MOS transistor M13, is input to the driver 32 including an amplifier, and the output of the driver 32 becomes the drive signal V1P.

The negative signal generation unit 22 includes P-channel MOS transistors M21 and M22 connected in series and a pair of N-channel MOS transistors M23 and M24 connected in parallel. The drain of the MOS transistor M22 and the MOS transistor The drains of M23 and M24 are connected, and these are connected between the power supply Vdd and the ground.
The pulse width modulation signal PG from the edge detection / delay insertion circuit 14 is input to the gates of the MOS transistor M21 and the MOS transistor M23, and the positive signal generator 21 generates the pulse width modulation signal PG from the gates of the MOS transistor M22 and the MOS transistor M24. The drive signal V1P is delayed by an inverter as the delay element 36 and input.

The voltage at the node N2, which is a connection point between the MOS transistor M22 and the MOS transistors M23 and M24, is input to the driver 37 including an amplifier, and the output of the driver 37 becomes the drive signal V1N.
That is, the positive signal generator 21 and the negative signal generator 22 generate the drive signals V1P and V1N synchronized with each other based on the pulse width modulation signal PG.
The above is the configuration of the gate drive circuit 15, and the gate drive circuit 16 generates drive signals V2P and V2N synchronized with each other based on the pulse width modulation signal NG in the same procedure.

Next, the half bridge amplifiers 17 and 18 will be described.
FIG. 3 is a configuration diagram showing an example of the load driving circuit 40 including the half bridge amplifiers 17 and 18.
As shown in FIG. 3, the half-bridge amplifier 17 includes a P-channel MOS transistor M31 and an N-channel MOS transistor M32 connected in series and connected between the DC voltage source Vcc and the ground. Similarly, the half-bridge amplifier 18 includes a P-channel MOS transistor M33 and an N-channel MOS transistor M34 connected in series and connected between the DC voltage source Vcc and the ground. The drive signal V1P is input to the gate of the MOS transistor M31, and the drive signal V1N is input to the gate of the MOS transistor M32. Similarly, the drive signal V2P is input to the gate of the MOS transistor M33, and the drive signal V2N is input to the gate of the MOS transistor M34.

  Then, the voltage of the node OUTP, which is the connection point between the MOS transistors M31 and M32 of the half bridge amplifier 17, becomes the output signal POUT. Similarly, the voltage of the node OUTN that is the connection point of the MOS transistors M33 and M34 of the half-bridge amplifier 18 becomes the output signal NOUT. A drive coil L1 is connected as a load between the nodes OUTP and OUTN.

  As shown in FIG. 4, when the polarity of the output signal is “POUT−NOUT”, the MOS transistors of the half-bridge amplifiers 17 and 18 are controlled to be turned on / off by the drive signal, so that the state T8a (positive electrode) is obtained. Current is supplied to the load L1 from the negative side), state T8b (current is supplied to the load L1 from the negative side), state T8c or T8d (no current supply from the DC voltage source Vcc) is taken. It has become.

In the circuit configuration shown in FIG. 1, the signal waveform of each part is as shown in FIG.
That is, as shown in FIG. 4A, the comparators 12 and 13 receive a triangular wave signal TRIANGLE as a reference signal from the triangular wave generator 11 and two kinds of complementary level signals POS and NEG, respectively. Entered. Then, the comparator 12 compares the triangular wave signal TRIANGLE with the level signal POS, and the comparator 13 compares the triangular wave signal TRIANGLE with the level signal NEG.

  The comparator output CMP1 of the comparator 12 is a result of comparing the triangular wave signal TRIANGLE of the triangular wave generator 11 with the level signal POS. Further, the comparator output CMP2 of the comparator 13 is a result of comparing the triangular wave signal TRIANGLE of the triangular wave generator 11 with the level signal NEG (FIG. 4B). These two comparator outputs CMP1 and CMP2 are input to the edge detection / delay insertion circuit 14, and the edge detection / delay insertion circuit 14 performs pulse width modulation by delaying one of the comparator outputs CMP1 and CMP2. Signals PG and NG are output.

Drive signals V1P and V1N are obtained from the gate drive circuit 15 based on the pulse width modulation signal PG, and drive signals V2P and V2N are obtained from the gate drive circuit 16 based on the pulse width modulation signal NG (FIG. 4C).
For the output signals POUT, NOUT (FIG. 4D) and POUT-NOUT (FIG. 4E), when the polarity of the output signal is POUT-NOUT, the state T8a (from the positive side) This represents a three-value output state: current is supplied to the load), state T8b (current is supplied to the load from the negative polarity side), state T8c or T8d (current supply from the direct current side is not provided).

When the output signal is positive, the output amplitude is determined by the ratio between T8a and T8c or T8d. When the output signal is negative, the output amplitude is determined by the ratio of T8b and T8c or T8d. When no signal is input, the ratio of T8a and T8b is the smallest and the ratio of T8c and T8d is the largest.
Next, the edge detection / delay insertion circuit 14 will be described.

FIG. 5 is a configuration diagram showing an example of the edge detection / delay insertion circuit 14.
The edge detection / delay insertion circuit 14 includes a PG signal generation unit 41 and an NG signal generation unit 42. The PG signal generation unit 41 generates a pulse width modulation signal PG based on the comparator output CMP1 of the comparator 12 and the signals of the respective units of the NG signal generation unit 42. Similarly, the NG signal generation unit 42 generates the pulse width modulation signal NG based on the comparator output CMP2 of the comparator 13 and the signals of the respective units of the PG signal generation unit 41.

The PG signal generation unit 41 detects a rising edge of the comparator output CMP1, detects a falling edge of the comparator output CMP1, and a rising edge processing unit 41a that performs processing on the rising edge of the comparator output CMP1. And a falling edge processing unit 41b that performs processing on the falling edge of the output CMP1.
Similarly, the NG signal generator 42 detects the rising edge of the comparator output CMP2, detects the rising edge of the comparator output CMP2, and detects the falling edge of the comparator output CMP2. A falling edge processing unit 42b that performs processing on the falling edge of the comparator output CMP2.

The rising edge processing unit 41a of the PG signal generation unit 41 delays the NAND output of the NAND circuit 51 that receives the comparator output CMP1 and a rising mask signal EDGE_NP described later, and the NAND circuit 61 described later of the rising edge processing unit 42a. It includes a delay element 52, a PG rising edge detection unit 53, and an inverter 54.
The PG rising edge detection unit 53 includes a delay element 53a and a NAND circuit 53b.

  The NAND circuit 53b is an inverted output PG_X obtained by inverting the NAND output of the NAND circuit 51 by the inverter 54, a delay output obtained by delaying the NAND output of the NAND circuit 51 by the delay element 53a, and a NAND output of the NAND circuit 61. When the rising timing of the comparator output CMP1 is earlier than the rising timing of the comparator output CMP2, the comparison is performed so that a predetermined deviation occurs in the rising timing of the comparator outputs CMP1 and CMP2. The rising mask signal EDGE_PP for adjusting the rising timing of the output CMP2 is output.

An inverted output PG_X obtained by inverting the NAND output of the NAND circuit 51 by the inverter 54 becomes a rising edge adjustment signal obtained by adjusting only the rising edge of the comparator output CMP1. That is, the rising edge adjustment signal PG_X is a signal obtained by adjusting the rising timing of the comparator output CMP1.
Similarly, the rising edge processing unit 42a of the NG signal generating unit 42 includes a NAND circuit 61 that receives the comparator output CMP2 and the rising mask signal EDGE_PP that is the output of the NAND circuit 53b of the rising edge processing unit 41a, and an NG rising edge. The detector 62 and the inverter 63 are included.

  The NG rising edge detection unit 62 includes a delay element 62a and a NAND circuit 62b. The NAND circuit 62b inverts the NAND output of the NAND circuit 51 of the rising edge processing unit 41a, the delay output obtained by delaying the NAND output of the NAND circuit 61 by the delay element 62a, and the NAND output of the NAND circuit 61 by the inverter 63. When the rising timing of the comparator output CMP2 is earlier than the rising timing of the comparator output CMP1, the comparator output CMP1 is output so that a predetermined shift occurs between the rising timings of the comparator outputs CMP1 and CMP2. A rising mask signal EDGE_NP for adjusting the rising timing is output.

An inverted output NG_X obtained by inverting the NAND output of the NAND circuit 61 by the inverter 63 becomes a rising edge adjustment signal obtained by adjusting only the rising edge of the comparator output CMP2. That is, the rising edge adjustment signal NG_X is a signal obtained by adjusting the rising timing of the comparator output CMP2.
On the other hand, the falling edge processing unit 41b of the PG signal generation unit 41 receives a rising edge adjustment signal PG_X and an inverted signal of a later-described falling mask signal EDGE_NN, and a later-described falling edge processing unit 42b. The delay circuit 56 includes a delay element 56 that delays an inverted signal of the NOR output of the NOR circuit 64, a PG falling detection unit 57, and inverters 58 and 59.

The PG falling edge detection unit 57 includes a delay element 57a and a NAND circuit 57b.
The NAND circuit 57b inverts the NOR output of the NOR circuit 55 by the inverter 58, the delayed output obtained by delaying the inverted output by the delay element 57a, the NOR output of the NOR circuit 55, and a later-described of the falling edge processing unit 42b. A delay output obtained by delaying the inverted signal of the NOR output of the NOR circuit 64 by the delay element 56 is input. Then, in response to these signals, the NAND circuit 57b causes the rising edge adjustment signal PG_X and the rising edge adjustment signal NG_X to rise when the falling timing of the rising edge adjustment signal PG_X is earlier than the falling timing of the rising edge adjustment signal NG_X. A falling mask signal EDGE_PN for adjusting the falling timing of the rising edge adjustment signal NG_X is output so that a predetermined shift occurs in the falling timing. This falling mask signal EDGE_PN is input to the NOR circuit 64 via the inverter 59.

An inverted output obtained by inverting the NOR output of the NOR circuit 55 by the inverter 58 becomes the pulse width modulation signal PG. That is, the falling edge processing unit 41b adjusts the falling timing with respect to the rising edge adjustment signal PG_X in which the rising timing of the comparator output CMP1 is adjusted, and this becomes the pulse width modulation signal PG.
Similarly, the falling edge processing unit 42b of the NG signal generating unit 42 receives a rising edge adjustment signal NG_X and an inverted output obtained by inverting the falling mask signal EDGE_PN from the falling edge processing unit 41b by the inverter 59. 64, an inverter 65 for inverting the NOR output of the NOR circuit 64, an NG falling detection unit 66, and an inverter 67.

  The NG falling detection unit 66 includes a delay element 66a and a NAND circuit 66b. The NAND circuit 66b includes an inverted output obtained by inverting the NOR output of the NOR circuit 55 of the falling edge processing unit 41b by the inverter 58, and The NOR output of the NOR circuit 64 and the delay output obtained by inverting the NOR output of the NOR circuit 64 by the inverter 65 and delaying the inverted signal by the delay element 66a are input. Then, in response to these signals, the NAND circuit 66b, when the falling timing of the rising edge adjustment signal NG_X is earlier than the falling timing of the rising edge adjustment signal PG_X, the rising edge adjustment signal PG_X and the rising edge adjustment signal NG_X. The falling mask signal EDGE_NN for adjusting the falling timing of the rising edge adjustment signal PG_X is output so that a predetermined shift occurs in the falling timing of the. The falling mask signal EDGE_NN is input to the NOR circuit 55 via the inverter 67.

An inverted output obtained by inverting the NOR output of the NOR circuit 64 by the inverter 65 becomes the pulse width modulation signal NG. That is, the falling edge processing unit 42b adjusts the falling timing with respect to the rising edge adjustment signal NG_X in which the rising timing of the comparator output CMP2 is adjusted, and this becomes the pulse width modulation signal NG.
The delay time of the delay element 52 is set so that the delay time of the delay element 52 is equal to or less than the delay time of the delay elements 53a and 62a. The delay time of the delay element 56 is set so that the delay time of the delay element 56 is equal to or less than the delay time of the delay elements 57a and 66a. Further, each delay element 53a, 57a, 62a, 66a has a difference of “POUT−NOUT” due to the influence of parasitic capacitance or the like in the process of passing through the gate drive circuits 15 and 16 and the half bridge amplifiers 17 and 18 at the subsequent stage. It is sufficient that the dynamic pulse can be recognized as a differential pulse without disappearing, and the current consumption is set to a value that does not increase. For example, it is set to about 10 ns for portable device applications.

Next, the operation of the above embodiment will be described.
FIG. 6 shows that when the edges of the pulse width modulation signals PG and NG are the same, that is, when the comparator outputs CMP1 and CMP2 are used as they are as the pulse width modulation signals PG and NG, the pulse width modulation signals PG and NG 7 shows signal waveforms in the respective parts of the edge detection / delay insertion circuit 14 when the comparator outputs CMP1 and CMP2 whose switching edges are the same are inputted. That is, the signal waveforms when the signals having the switching edges at the same time are input as the comparator outputs CMP1 and CMP2.

  As shown in FIG. 6, when the rising timing and falling timing of the comparator output CMP1 and the comparator output CMP2 are the same (FIG. 6A), when both the comparator outputs CMP1 and CMP2 are at the LOW level. The rising mask signals EDGE_PP and EDGE_NP become HIGH level (FIG. 6B), and the rising edge adjustment signals PG_X and NG_X become LOW level (FIG. 6C).

Further, the falling mask signals EDGE_PN and EDGE_NN become HIGH level (FIG. 6 (d)), and the pulse width modulation signals PG and NG become LOW level (FIG. 6 (e)).
As a result, POUT-NOUT becomes substantially zero (FIG. 6 (f)).
When the comparator outputs CMP1 and CMP2 become HIGH level at time t1, the NAND output of the NAND circuit 61 is input to the PG rising detection unit 53 with a delay corresponding to the delay time of the delay element 52 from the NAND output of the NAND circuit 51. . On the other hand, since the NAND output of the NAND circuit 51 masks the NG rising detection unit 62, the PG rising detection unit 53 changes the rising mask signal EDGE_PP to the LOW level, and the NAND output of the NAND circuit 61 changes to the LOW level. Is delayed by the delay time Δd1 of the delay element 53a. Further, since the NAND output of the NAND circuit 51 is switched to the LOW level at the rising timing of the comparator output CMP1, the rising edge adjustment signal PG_X is also switched to the HIGH level.

  Since the PG rising edge detection unit 53 becomes effective earlier than the NG rising edge detection unit 62 due to the delay time of the delay element 52, the rising mask signal EDGE_PP has a delay time Δd1 from the time when the comparator outputs CMP1 and CMP2 rise at the time point t1. The LOW level is maintained until it elapses, and then the HIGH level is switched. For this reason, the rising edge adjustment signal NG_X also switches to the HIGH level at the time t2 when the delay time Δd1 has elapsed from the time t1.

Further, when the comparator output CMP1 is switched to HIGH level at the time t1 and the rising edge adjustment signal PG_X is switched to HIGH level, the NOR output of the NOR circuit 55 is switched to LOW level, and as a result, the pulse width modulation signal PG is HIGH. Switch to level.
On the other hand, the comparator output CMP2 is switched to the HIGH level at the time point t1, but the rising mask signal EDGE_PP is set to the LOW level. Therefore, the rising edge adjustment signal NG_X is not switched to the HIGH level at the time point t1, and the delay time Δd1 starts from the time point t1. At time t2 when the rising mask signal EDGE_PP rises, the high level is switched. When the rising edge adjustment signal NG_X is switched to HIGH level at time t2, the pulse width modulation signal NG is also switched to HIGH level accordingly.

As a result, the rising timings of the comparator outputs CMP1 and CMP2 are the same, but the rising timings of the pulse width modulation signals PG and NG are different, so that POUT−NOUT becomes a positive value between the time point t1 and the time point t2, that is, the difference A dynamic pulse will be generated.
That is, by providing the delay element 53a, the rising mask signal EDGE_PP is switched to the LOW level at the timing t1 when the comparator outputs CMP1 and CMP2 are switched to the HIGH level, and as shown by hatching in FIG. The rising edge adjustment signal NG_X is prohibited from changing during the delay time Δd1 from the time point t1, the edge adjustment signal NG_X is switched when the delay time Δd1 has passed, and the pulse width that changes at the rising timing of the edge adjustment signal NG_X A modulation signal NG is generated.

Therefore, the switching timing of the pulse width modulation signal NG is delayed by the delay time Δd1, and the rising timing of the pulse width modulation signals PG and NG is shifted, so that a positive differential pulse can be generated.
From this state, when both the comparator outputs CMP1 and CMP2 fall at time t3, the rising edge adjustment signals PG_X and NG_X are both switched to the LOW level, and the rising mask signals EDGE_PP and EDGE_NP maintain the HIGH level.

  On the other hand, at the timing when the rising edge adjustment signals PG_X and NG_X are switched to the LOW level, the NOR output of the NOR circuit 64 is delayed from the NOR output of the NOR circuit 55 by the delay time of the delay element 56 to the PG falling detection unit 57. Entered. On the other hand, since the NOR output of the NOR circuit 55 masks the NG fall detection unit 66, the PG fall detection unit 57 becomes effective, and the timing at which the pulse width modulation signal NG switches to the LOW level is delayed.

Therefore, the pulse width modulation signal PG switches to the LOW level at the timing when the rising edge adjustment signal PG_X switches to the LOW level. Further, the falling mask signal EDGE_PN, which is the output of the NAND circuit 57b, maintains the LOW level for the time corresponding to the delay time Δd2 of the delay element 57a, and then switches to the HIGH level at the time t4 when the delay time Δd2 has elapsed from the time t3. .
Therefore, the pulse width modulation signal NG is switched to the LOW level when the falling mask signal EDGE_PN is switched to the HIGH level at the time t4.
That is, the switching timing of the pulse width modulation signal NG is delayed by the delay time Δd2, and the falling timings of the pulse width modulation signal PG and NG are different, so that a negative differential pulse can be generated.

  From this state, when both the comparator outputs CMP1 and CMP2 rise at time t5, the rising mask signal EDGE_PP becomes LOW level for the delay time Δd1 and then switches to HIGH level at time t6, as described above. The rising edge adjustment signal NG_X rises at time t6, and the rising timing of the pulse width modulation signal NG is delayed by the delay time Δd1. As a result, a positive differential pulse can be generated.

As described above, the delay elements 53a and 57a are provided, and the switching timing of the rising edge adjustment signal NG_X and the pulse width modulation signal NG is determined by the rising mask signal EDGE_PP and the falling mask signal EDGE_PN in response to changes in the comparator outputs CMP1 and CMP2. The signal NG in which the switching timing of the comparator output CMP2 is forcibly delayed is used as the pulse width modulation signal.
Therefore, even when the rising timing and falling timing of the comparator outputs CMP1 and CMP2 coincide with each other, positive and negative differential pulses are alternately generated by adjusting the switching timing of the comparator output CMP2. Can be made.

  Further, the rising timing of the other comparator output is adjusted with reference to the rising timing of one comparator output. That is, the switching timing of the other comparator output CMP1 and CMP2 is adjusted because the switching timing of the other comparator output is adjusted with reference to the switching timing of the one comparator output in consideration of the variation. In the differential pulse determined based on the pulse width modulation signals PG and NG, the influence due to the manufacturing variation of the comparator outputs CMP1 and CMP2 is eliminated, and the differential pulse mainly affects the manufacturing variation of the delay elements 53a, 57a, 62a, and 66a. It will only be affected. Therefore, the influence of manufacturing variations in the differential pulse can be suppressed, and the differential pulse can be generated more accurately.

In FIG. 5, since the delay elements 52 and 56 are provided on the PG signal generation unit 41 side in the edge detection / delay insertion circuit 14, the rise timing or fall timing of the comparator outputs CMP1 and CMP2 is the same. In some cases, the pulse width modulation signal PG is given priority and the switching timing of the pulse width modulation signal NG is delayed, but the present invention is not limited to this.
In the edge detection / delay insertion circuit 14, the delay elements 52 and 56 are provided on the NG signal generation unit 42 side, so that the pulse width can be increased when the rising and falling switching timings of the comparator outputs CMP 1 and CMP 2 are the same. The modulation signal NG may be prioritized and the switching timing of the pulse width modulation signal PG may be delayed.

  Next, FIG. 7 shows a case where the rising edge and the falling edge of the pulse width modulation signal PG are earlier than the pulse width modulation signal NG and the rising edge difference and the falling edge difference are small. The signal waveform is shown. That is, when the comparator outputs CMP1 and CMP2 are used as they are as the pulse width modulation signals PG and NG, the comparator outputs CMP1 and CMP2 such that the pulse width modulation signal PG is switched before the pulse width modulation signal NG are input. The signal waveforms in the respective parts of the edge detection / delay insertion circuit 14 when the edge difference is shorter than the delay time of the delay elements 53a and 57a are shown.

  As shown in FIG. 7, when the rising timing and falling timing of the comparator output CMP1 are earlier than the comparator output CMP2 (FIG. 7A), when both the comparator outputs CMP1 and CMP2 are at the LOW level. Then, the rising mask signals EDGE_PP and EDGE_NP become HIGH level (FIG. 7B), and the rising edge adjustment signals PG_X and NG_X become LOW level (FIG. 7C).

Further, the falling mask signals EDGE_PN and EDGE_NN are at a HIGH level (FIG. 7 (d)), and the pulse width modulation signals PG and NG are at a LOW level (FIG. 7 (e)).
As a result, POUT-NPUT becomes substantially zero (FIG. 7 (f)).
When the comparator output CMP1 becomes HIGH level at time t11, the NAND output of the NAND circuit 51 becomes LOW level, and thereby the rising edge adjustment signal PG_X becomes HIGH level. Further, since the NAND output of the NAND circuit 51 is input to the NAND circuit 53b via the delay element 53a, it is delayed by the delay time Δd1 of the delay element 53a and input to the NAND circuit 53b.

Further, the NAND output of the NAND circuit 61 remains at the HIGH level. Therefore, as shown in FIG. 7B, the rising mask signal EDGE_PP that is the output of the NAND circuit 53b is switched to the LOW level for the delay time Δd1 of the delay element 53a, and then is switched to the HIGH level at time t13.
The rising mask signal EDGE_PP is switched to the LOW level. However, since the comparator output CMP2 remains at the LOW level, the rising edge adjustment signal NG_X remains at the LOW level. For this reason, the pulse width modulation signal NG remains at the LOW level.

Further, since the rising edge adjustment signal PG_X is switched to the HIGH level, the pulse width modulation signal PG is switched to the HIGH level.
Therefore, POUT−NOUT is a positive value.
At time t12, when the comparator output CMP2 is switched to the HIGH level, the rising mask signal EDGE_PP maintains the LOW level at this time, and the NADN output of the NAND circuit 61 maintains the HIGH level. Therefore, the rising edge adjustment signal NG_X is , LOW level is maintained.

At time t13, the rising mask signal EDGE_PP is switched to HIGH level, and when the rising edge adjustment signal NG_X is switched to HIGH level, the pulse width modulation signal NG is switched to HIGH level.
As a result, a differential pulse having a positive value is generated between time t11 when the pulse width modulation signal PG rises and time t13 when the pulse width modulation signal NG rises.

When the comparator output CMP1 is switched to the LOW level at time t14, the rising edge adjustment signal PG_X is switched to the LOW level. When the comparator output CMP2 is switched to LOW level at the time t15, the rising edge adjustment signal NG_X is set to the LOW level. Switch.
At time t14, the falling mask signal EDGE_NN remains at the HIGH level, the rising edge adjustment signal PG_X is switched to the LOW level, and the NOR output of the NOR circuit 55 is switched to the HIGH level, so that the pulse width modulation signal PG is set to the LOW level. Switch. Further, the NOR output of the NOR circuit 55 is switched to the HIGH level at time t14, and the delay output of the delay element 57a is switched to the LOW level when the delay time Δd2 has elapsed from the time t14. Further, the falling mask signal EDGE_PN becomes the LOW level between the times t14 and t16, and the rising edge adjustment signal NG_X switches to the LOW level at the falling timing of the comparator output CMP2 at the time t15, but the NOR output of the NOR circuit 64 Maintains the LOW level, the output of the inverter 65, that is, the pulse width modulation signal NG, maintains the HIGH level.

When the falling mask signal EDGE_PN is switched to the LOW level at time t16, the rising edge adjustment signal NG_X is switched to the LOW level at time t15, so that the pulse width modulation signal NG is switched to the LOW level at time t16.
Therefore, a differential pulse composed of a negative value POUT-NOUT is generated between t14 and t16 when the pulse width modulation signal PG falls at time t14 and the pulse width modulation signal NG falls at time t16.

  As described above, even when the difference between the rising edges and the falling edges of the comparator outputs CMP1 and CMP2 is relatively small, that is, when the edge difference is shorter than the delay time of the delay elements 53a and 57a, the pulse The rising edge difference and the falling edge difference can be shifted by the delay times Δd1 and Δd2 between the width modulation signals PG and NG, respectively. Therefore, a difference occurs in POUT−NOUT, and positive and negative differential pulses can be generated.

  At this time, when the comparator output CMP2 is delayed to obtain the pulse width modulation signal NG, it is not delayed by the delay time from the switching timing of the comparator output CMP2, as shown by hatching in FIG. The comparator output CMP1 that has been switched first is delayed by a delay time from the switching timing. Therefore, it is possible to avoid the pulse width modulation signal NG being delayed more than necessary, that is, the pulse width of the differential pulse can be set to the delay time at the maximum.

  Next, FIG. 8 shows a case where the rising edge and the falling edge of the pulse width modulation signal PG are earlier than the pulse width modulation signal NG, and each part when the rising edge difference and the falling edge difference are large. The signal waveform is shown. That is, when the comparator outputs CMP1 and CMP2 are used as they are as the pulse width modulation signals PG and NG, the comparator outputs CMP1 and CMP2 such that the pulse width modulation signal PG is switched before the pulse width modulation signal NG are input. The signal waveforms in the respective parts of the edge detection / delay insertion circuit 14 when the edge difference is longer than the delay time of the delay elements 53a and 57a are shown.

  As shown in FIG. 8, when the difference in switching timing between the comparator outputs CMP1 and CMP2 is relatively large, the rising edge adjustment signal PG_X switches to HIGH level when the comparator output CMP1 switches to HIGH level at time t21. When the comparator output CMP2 rises to HIGH level at t23, the rising edge adjustment signal NG_X is switched to HIGH level.

  At the time t21, the rising mask signal EDGE_NP remains at the HIGH level, the rising edge adjustment signal PG_X is switched to the HIGH level, and the NAND output of the NAND circuit 51 is switched to the LOW level. It switches to the LOW level at time t22 when the delay time Δd1 has elapsed. At time t21, the delay output of the delay element 52 continues to maintain the HIGH level. Therefore, the rising mask signal EDGE_PP that is the output of the NAND circuit 53b is switched to the LOW level at time t21, and then the delay of the delay element 53a at time t22. The LOW level is maintained until the output is switched to the LOW level.

  The rising mask signal EDGE_PP is at the LOW level from time t21 to time t22, but the comparator output CMP2 is maintained at the LOW level until time t23, so that the NAND output of the NAND circuit 61 continues to be at the HIGH level. At t23, the comparator output COM2 is switched to the HIGH level, and when the rising mask signal EDGE_PP and the comparator output CMP2 are both set to the HIGH level, the comparator output COM2 is switched to the LOW level. Therefore, the rising edge adjustment signal NG_X is switched to the HIGH level at time t23.

  The rising edge adjustment signal PG_X rises to HIGH level at time t21, and the falling mask signal EDGE_NN maintains HIGH level, so the NOR output of the NOR circuit 55 switches to LOW level at time t21. Further, the rising edge adjustment signal NG_X is switched to HIGH level at time t23, and the falling mask signal EDGE_PN is maintained at HIGH level, so that the NOR output of the NOR circuit 64 is switched to LOW level at time t23. Therefore, the pulse width modulation signal PG switches to the HIGH level at time t21, and the pulse width modulation signal NG switches to the HIGH level at time t23.

As a result, a differential pulse composed of a positive value POUT-NOUT is generated between t21 and t23 when the pulse width modulation signal PG rises at time t21 and the pulse width modulation signal NG rises at time t23.
Similarly, when the comparator output CMP1 is switched to the LOW level at the time t24 and the comparator output CMP2 is switched to the LOW level at the time t26, the delay element 57a starts from the timing at which the comparator output CMP1 is switched to the LOW level at the time t24. The pulse width modulation signal NG is prevented from changing until the delay time Δd2 elapses, that is, during the period indicated by hatching in FIG.

  In the case of FIG. 8, the difference between the rising and rising edges is relatively large between the pulse width modulation signals PG and NG, and the edge difference is longer than the delay time of each delay element. In this case, the period in which the rising mask signal EDGE_PP is at the LOW level, that is, the period for preventing the change in the rising edge adjustment signal NG_X indicated by hatching in FIG. 8 ends before the timing at which the comparator output CMP2 is switched. Therefore, the rising edge adjustment signal NG_X is not delayed at the timing when the comparator output CMP2 is switched, that is, the switching of the rising edge adjustment signal NG_X is not prohibited. Similarly, switching of the pulse width modulation signal NG is not prohibited.

  Therefore, when the edge difference between the rising edge and the falling edge between the comparator outputs CMP1 and CMP2 is a sufficient edge difference for obtaining a differential pulse, the rising / falling timing of the comparator output CMP2 is delayed. There is nothing. That is, in a situation where a sufficient differential pulse can be obtained, the comparator output CMP2 is not unnecessarily delayed.

  Next, when the rising and falling edges of the pulse width modulation signal NG are advanced with respect to the pulse width modulation signal PG, that is, the comparator outputs CMP1 and CMP2 are used as they are as the pulse width modulation signals PG and NG. In this case, a case will be described in which comparator outputs CMP1 and CMP2 are input such that the pulse width modulation signal NG is switched before the pulse width modulation signal PG.

  FIG. 9 shows signal waveforms at various portions when the rising edge difference and the falling edge difference are relatively small, that is, when the edge difference is shorter than the delay time of each delay element. These show signal waveforms of respective parts when the rising edge difference and the falling edge difference are relatively large, that is, when the edge difference is longer than the delay time of each delay element.

  As shown in FIG. 9, when the difference between the edge switching timings of the pulse width modulation signals NG and PG is shorter than the delay time of each delay element, it rises when the comparator output CMP2 switches to the HIGH level at time t31. When the edge adjustment signal NG_X is switched to HIGH level and the comparator output CMP1 is switched to HIGH level at time t32, the rising edge adjustment signal PG_X is adjusted to be switched to HIGH level at time t33.

  At the time t31, the rising mask signal EDGE_PP remains at the HIGH level, the comparator output CMP2 is switched to the HIGH level, and the NAND output of the NAND circuit 61 is switched to the LOW level, so that the delay output of the delay element 62a is delayed from the time t31. It switches to the LOW level at time t33 when the time Δd3 has elapsed. The delay output of the delay element 62a continues to be at the HIGH level at time t31. For this reason, the rising mask signal EDGE_NP that is the output of the NAND circuit 62b is maintained at the LOW level until the delay output of the delay element 62a is switched to the LOW level at the time t33 after switching to the LOW level at the time t31.

  On the other hand, the comparator output CMP1 switches to the HIGH level at the time point t32. However, the rising mask signal EDGE_NP maintains the LOW level between the time points t31 and t33, so that the NAND output of the NAND circuit 51 continues to maintain the HIGH level. At time t33, the rising mask signal EDGE_NP and the comparator output CMP1 are both switched to the LOW level when both become the HIGH level. Therefore, the rising edge adjustment signal PG_X is switched to the HIGH level at time t33.

  The rising edge adjustment signal NG_X rises to the HIGH level at time t31, and the falling mask signal EDGE_PN maintains the HIGH level. Therefore, the NOR output of the NOR circuit 64 switches to the LOW level at time t31. Further, the rising edge adjustment signal PG_X is switched to the HIGH level at the time t33, and the falling mask signal EDGE_NN is maintained at the HIGH level, so that the NOR output of the NOR circuit 55 is switched to the LOW level.

For this reason, the pulse width modulation signal NG is switched to the HIGH level at the time point t31, and during the time points t31 to t33 until the pulse width modulation signal PG is switched to the HIGH level at the time point t33, a differential pulse composed of a negative value POUT-NOUT is generated. Occur.
Similarly, when the comparator output CMP2 switches to the LOW level at time t34 and the comparator output CMP1 switches to the LOW level at time t35, the delay time of the delay element 66a starts from the timing at which the comparator output CMP2 switches to the LOW level at time t34. Until Δd4 elapses, that is, during the period indicated by hatching in FIG. 9, the pulse width modulation signal PG is prevented from changing.

Therefore, an edge difference corresponding to the delay time Δd4 can be ensured between the falling edges between the pulse width modulation signals PG and NG. Therefore, a differential pulse composed of POUT-NOUT having a positive value is generated from time t34 to time t36 until the pulse width modulation signal NG is switched to the LOW level and the pulse width modulation signal PG is switched to the LOW level at the time t36.
On the other hand, as shown in FIG. 10, when the difference in edge switching timing between the pulse width modulation signals NG and PG is longer than the delay time of each delay element, the comparator output CMP2 switches to HIGH level at time t41. When the rising edge adjustment signal NG_X is switched to HIGH level and the comparator output CMP1 is switched to HIGH level at time t43, the rising edge adjustment signal PG_X is switched to HIGH level.

  At the time point t41, the rising mask signal EDGE_PP remains at the HIGH level, and the comparator output CMP2 is switched to the HIGH level. Therefore, the NAND output of the NAND circuit 61 is switched to the LOW level. At time t42 when the delay time Δd3 elapses, the LOW level is switched. At time t41, the delay output of the delay element 62a continues to maintain the HIGH level. Therefore, the rising mask signal EDGE_NP that is the output of the NAND circuit 62b is switched to the LOW level at time t41, and then the delay of the delay element 62a at time t42. The LOW level is maintained until the output is switched to the LOW level.

  On the other hand, since the comparator output CMP1 is switched to the HIGH level at time t43, when the rising mask signal EDGE_NP is switched to the HIGH level at time t42, the NAND output of the NAND circuit 51 continues to maintain the LOW level, and the time t43. Thus, when the comparator output CMP1 is switched to the HIGH level and both the comparator output CMP1 and the rising mask signal EDGE_NP are at the HIGH level, the NAND output of the NAND circuit 51 is switched to the LOW level.

Therefore, the rising edge adjustment signal PG_X is switched to the HIGH level at time t43.
Then, the rising edge adjustment signal NG_X switches to the HIGH level at time t41, and the falling mask signal EDGE_PN maintains the HIGH level, so that the NOR output of the NOR circuit 64 switches to the LOW level at time t41. Further, the rising edge adjustment signal PG_X switches to the HIGH level at time t43, and the falling mask signal EDGE_NN maintains the HIGH level, so the NOR output of the NOR circuit 55 switches to the LOW level at time t43. Therefore, the pulse width modulation signal PG rises to HIGH level at time t43.

For this reason, the pulse width modulation signal NG rises at time t41, and a differential pulse composed of negative value POUT-NOUT is generated from time t41 to t43 until the pulse width modulation signal PG rises at time t43.
Similarly, when the comparator output CMP2 is switched to the LOW level at time t44 and the comparator output CMP1 is switched to the LOW level at time t46, the delay element 66a starts from the timing at which the comparator output CMP2 is switched to the LOW level at time t44. Until the time point t45 when the delay time Δd4 elapses, that is, during the period indicated by hatching in FIG. 10, the pulse width modulation signal PG is prevented from changing.

Therefore, an edge difference corresponding to the delay time Δd4 can be secured between the falling edge and the rising edge between the pulse width modulation signals PG and NG.
That is, as shown in FIG. 9 and FIG. 10, when the rising and falling edges of the pulse width modulation signal NG are advanced with respect to the pulse width modulation signal PG, at the timing when the comparator output CMP1 switches to the HIGH level, The output of the rising edge adjustment signal PG_X is delayed by a predetermined delay time, and the change is prevented during the delay time as shown in FIGS. 9 and 10 with respect to the rising edge adjustment signal PG_X. The change of the pulse width modulation signal PG is also prevented, and the pulse width modulation signal PG rises when a predetermined delay time has elapsed. Similarly, the change of the pulse width modulation signal PG is prevented at the timing when the comparator output CMP1 is switched to the LOW level, and the pulse width modulation signal PG is switched to the LOW level when a predetermined delay time elapses.

  Then, when the difference between the rising edges and the falling edges of the comparator outputs CMP1 and CMP2 is shorter than a predetermined delay time, the rising and falling edges of the pulse width modulation signal PG are detected as shown in FIG. Since the delay is forcibly delayed, a differential pulse having a sufficient pulse width can be generated. On the contrary, when the difference between the rising edge and the falling edge is longer than a predetermined delay time, even if the rising and falling edges of the pulse width modulation signal PG are delayed, the comparator outputs CMP1 and CMP2 Since the edge difference is longer than the delay time, the pulse width modulation signal PG in which the switching timing of the comparator output CMP1 is delayed is not generated, that is, the pulse width modulation signal PG is not affected.

  As described above, in the present embodiment, the switching of the edge of the pulse width modulation signal PG or NG that changes at the switching timing of the comparator output to be switched later, of the comparator outputs CMP1 and CMP2, is performed first. The comparator output is prohibited for a predetermined delay time from the edge timing of the comparator output, and is switched after the delay time has elapsed.

  Therefore, there is a delay time equivalent between the pulse width modulation signal that changes at the switching timing according to the comparator output that was switched first and the pulse width modulation signal that changes at the switching timing according to the comparator output that is switched later. Edge difference can be secured. Therefore, a differential pulse having a pulse width corresponding to the delay time can be generated between the pulse width modulation signals PG and NG. As a result, differential pulses can be generated periodically at the timing of rising and falling edges.

  When the timings of the edges of the comparator outputs CMP1 and CMP2 are the same, the pulse width modulation signal PG is prioritized by the delay elements 52 and 56, and the pulse width modulation signal PG is preferred to the pulse width modulation signal NG. Since the switching timing of the pulse width modulation signal NG is adjusted so that the switching timing is switched first, the differential pulses can be reliably generated even when the switching timings of the comparator outputs CMP1 and CMP2 match. Can do.

As a result, it is possible to prevent a noise spectrum from being generated due to the fact that the differential pulse is not periodically generated.
At this time, even if one of the pulse width modulation signals is delayed, the pulse width of the differential pulse generated by this delay is equivalent to a predetermined delay time at the maximum. Here, a current corresponding to the pulse width of the differential pulse is supplied to the load L1, but the pulse width of the differential pulse is equivalent to the delay time at the maximum, so the load is generated by the forcibly generated differential pulse. Therefore, a decrease in power efficiency can be avoided.

  The scope of the present invention is not limited to the illustrated and described exemplary embodiments, but includes all embodiments that provide the same effects as those intended by the present invention. Further, the scope of the invention can be defined by any desired combination of particular features among all the disclosed features.

DESCRIPTION OF SYMBOLS 1 Driver 11 Triangular wave generator 12, 13 Comparator 14 Edge detection / delay insertion circuit 15, 16 Gate drive circuit 17, 18 Half bridge amplifier 51 NAND circuit 52 Delay element 53 PG rising edge detection unit 53a Delay element 53b NAND circuit 54 Inverter 55 NOR circuit 56 Delay element 57 PG falling detection unit 57a Delay element 57b NAND circuit 58 Inverter 61 NAND circuit 62 NG rising detection unit 62a Delay element 62b NAND circuit 63 Inverter 64 NOR circuit 65 Inverter 66 NG falling detection unit 66a Delay element 66b NAND circuit 67 Inverter CMP1 Comparator output CMP2 Comparator output EDGE_NN Rising mask signal EDGE_NP Rising mask signal EDGE_PN Falling mask signal EDGE_PP falling mask signal L1 load POS, NEG level signal PG, NG pulse width modulation signal PG_X, NG_X rising edge adjustment signal Δd1, Δd2, Δd3, Δd4 delay time

Claims (4)

A PWM control signal generator for generating a first PWM control signal and a second PWM control signal for driving the first half-bridge amplifier and the second half-bridge amplifier;
A switching timing adjustment unit for adjusting a switching timing of the first and second PWM control signals generated by the PWM control signal generation unit;
A drive circuit for driving the first and second half-bridge amplifiers based on the first and second PWM control signals after being adjusted by the switching timing adjustment unit,
The load is driven according to the potential difference between the output ends of the first half-bridge amplifier and the second half-bridge amplifier,
The switching timing adjustment unit
Of the first and second PWM control signals, a rising mask signal is generated that generates a rising mask signal that lasts until a predetermined delay time elapses from the rising timing of one PWM control signal that has a rising timing earlier. And
A rising delay insertion unit that delays the rising timing of the other PWM control signal based on the other PWM control signal and the rising mask signal;
Of the first and second PWM control signals, a fall that generates a fall mask signal that lasts from the fall timing of the one PWM control signal that precedes the fall timing until the delay time elapses. A mask signal generation unit;
A falling delay insertion unit that delays the falling timing of the other PWM control signal based on the other PWM control signal and the falling mask signal;
A switching amplifier comprising:   A delay unit is provided for delaying the switching timing of one predetermined PWM control signal among the first and second PWM control signals generated by the PWM control signal generation unit with respect to the other PWM control signal. The switching amplifier according to claim 1. The switching timing adjustment unit
The switching timing of the first and second PWM control signals is adjusted using the signal obtained by delaying the one PWM control signal by the delay unit and the other PWM control signal as the first and second PWM control signals. The switching amplifier according to claim 2, wherein:   4. The switching amplifier according to claim 2, wherein the delay unit adjusts the rising mask signal or the falling mask signal.

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