JP5656360B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, various developments and researches have been made in order to obtain a high breakdown voltage semiconductor device.
For example, Patent Document 1 proposes a semiconductor device in which an element diffusion region is provided in a p-type semiconductor substrate and a hole trap level is formed in the oxide film on the surface of the semiconductor substrate by electron beam irradiation. Patent Document 2 discloses a semiconductor in which correction charges are introduced into the interface between a p-type layer and a silicon oxide film as a RESURF layer to cancel adverse effects such as fixed charges mixed in the device during the manufacturing process. A device has been proposed.

  On the other hand, Non-Patent Document 1 discloses that the amount of fixed charge (hole type) generated at the interface between the oxide film and the silicon substrate changes depending on the wafer temperature and wafer atmosphere.

Japanese Unexamined Patent Publication No. 07-221115 Japanese Patent Laid-Open No. 08-255919

Characteristics of Surface-State Charge of Thermally Oxidized Silicon (J. Electrochem. Soc: SOLID STATE SCIENCE Vol. 114, No. 3 March 1967 p266 ~ 274)

Incidentally, for example, in a semiconductor device such as a lateral power MOSFET using a reduced surface field (RESURF) structure (see FIG. 4), there is a problem that the ON resistance changes with time during operation. This is because a high voltage is applied between the source region and the drain region during the operation of the lateral power MOSFET, but surface leakage current flows in the surface layer of the passivation film (for example, plasma silicon nitride film) formed on the outermost surface, and electrons pass through the passivation film. In the process of being gradually trapped on the surface layer, the field oxide sub-region (that is, the drain drift region consisting of the high resistance diffusion region) is gradually depleted or gradually advances, so that the field oxide sub-region is the high resistance region. Therefore, it is considered that the influence of depletion appears remarkably, and the ON resistance changes with time with respect to the initial value. This is considered that the ON resistance does not change over time with respect to the initial value even when depletion occurs because the impurity concentration is high and the resistance is low in the low resistance region in the field oxide film lower region.
Therefore, an intermediate layer (interlayer insulating film) is added to the shield film so as not to affect the region below the field oxide film, and a P-type diffusion layer is formed by boron or the like in order to provide a shield effect under the field oxide film. Although a method is mentioned, the thing which can satisfy manufacturing cost was not obtained.

  SUMMARY OF THE INVENTION Therefore, the present invention is to provide a method for manufacturing a semiconductor device that can easily reduce the change with time of ON resistance during operation.

The above problem is solved by the following means. That is,
A method for manufacturing a semiconductor device of the present invention includes:
Forming a source region and a drain region on a semiconductor substrate, and forming a high resistance diffusion region between the source region and the drain region and a field oxide film as a first insulating film on the high resistance diffusion region;
Forming a gate electrode on the semiconductor substrate;
Said gate electrode, said source region, said drain region, and on the first insulating film, forming a second insulating film,
It said semiconductor substrate having the second insulating film is formed, was subjected to annealing 600 ° C. or higher placed in an annealing furnace, a gas atmosphere in which oxygen gas is contained more than 20%, the said semiconductor substrate at 600 ° C. or higher Removing from the annealing furnace;
Forming a wiring film electrically connected to each of the gate electrode, the source region, and the drain region on the second insulating film;
Forming a third insulating film so as to cover at least the wiring film;
A method for manufacturing a semiconductor device having

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that can easily reduce a change in ON resistance with time during operation.

It is process drawing which shows the manufacturing method of the semiconductor device which concerns on this embodiment. It is process drawing which shows the manufacturing method of the semiconductor device which concerns on this embodiment. It is a schematic diagram which shows an example of the annealing process sequence of the interlayer insulation film in the manufacturing method of the semiconductor device which concerns on this embodiment. It is a schematic diagram for demonstrating the effect | action of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a figure which shows the relationship between the minus electric potential biased (electron is trapped) by the outermost layer (passivation film), and ON resistance fluctuation | variation in the semiconductor device obtained by the manufacturing method of the semiconductor device which concerns on this embodiment.

  Hereinafter, an exemplary embodiment of the present invention will be described with reference to the drawings. In addition, the same code | symbol is provided to the member which has the substantially same function through all the drawings, and the overlapping description may be abbreviate | omitted.

  1 and 2 are process diagrams showing a method for manufacturing a semiconductor device according to the present embodiment. The method for manufacturing a semiconductor device according to the present embodiment will be described with reference to a method for manufacturing a lateral power MOSFET using a reduced surface field (RESURF) structure, but is not limited thereto.

  As shown in FIG. 1A, the semiconductor device according to this embodiment prepares a P-type semiconductor substrate 10 (for example, a silicon substrate having a resistance of 130 Ωcm).

Next, as shown in FIG. 1B, each well and impurity diffusion region are formed in the surface layer region of the semiconductor substrate 10 by impurity implantation. Specifically, for example, first, the n-type well 12 is formed in the semiconductor substrate 10 by n-type impurity implantation.
Next, a buried P ⁻ type diffusion region 14 is formed so as to be buried inside the n type well 12 by P type impurity implantation.
Next, by n-type impurity implantation, an n-type high-resistance diffusion region (for example, resistance 4.0 to 4.0 mm) having a width of several tens of μm, for example, is formed on the surface layer region of the N-type well 12 and above the buried P ⁻ -type diffusion region 14. 6.0 kohm / sq region), and this is used as the drain drift region 16.
Next, a P-type diffusion region 18 (so-called P Body) is formed on the surface of the semiconductor substrate 10 outside the N-type well 12 by P-type impurity implantation.
Next, a P ⁺ type diffusion region 20 is formed in the surface region of the P type diffusion region 18 by P type impurity implantation.

Next, by N-type impurity implantation, an N ⁺ -type diffusion region is formed in the surface layer region of the N-type well 12 so as to sandwich the drain drift region 16 in the semiconductor substrate 10, and this is used as the drain region 22B. On the other hand, an N ⁺ type diffusion region is formed on the surface of the P type diffusion region 18 (the surface closer to the N type well 12 than the P ⁺ type diffusion region 20), and this is used as the source region 22A.

  Next, as shown in FIG. 1C, a LOCOS oxide film is formed on the drain drift region 16 in the surface of the N-type well 12 by a LOCOS (Local Oxidation of Silicon) method. The film 24 (first insulating film) is used. Thereby, a field oxide film 24 is formed between the source region 22A and the drain region 22B. A drain drift region 16 composed of an n-type high resistance diffusion region is formed immediately below the field oxide film 24.

  Next, over the semiconductor substrate 10, the source region 22 </ b> A is exposed to the exposed p-type diffusion region 18 and the exposed N-type well 12 across the exposed surface of the semiconductor substrate 10. And a gate electrode 28A is formed on the surface of the gate oxide film 26A. The gate electrode 28A is formed so that a part thereof extends on the field oxide film 24. On the other hand, a gate oxide film 26B is formed on the semiconductor substrate 10 so as to cover a part of the drain region 22B, and a gate electrode 28B is formed on the surface of the gate oxide film 26B. The gate electrode 28B is formed so that a part thereof extends on the field oxide film 24.

  Next, as shown in FIG. 2D, an interlayer insulating film 30 is formed so as to cover the gate electrodes 28A, 28B, the source region 22A, the drain region 22B, and the field oxide film 24 by plasma CVD, reactive sputtering, or the like. (Second insulating film: for example, a silicon oxide film, a silicon nitride film, a silicon oxide film (PSG film) to which phosphorus is added, or the like) is formed.

Next, the semiconductor substrate 10 on which the interlayer insulating film 30 is formed is placed in an annealing furnace and annealed. This annealing treatment is performed, for example, for the purpose of improving the flowability and denseness of the interlayer insulating film 30, and is, for example, 600 ° C. or higher (desirably 900 ° C. to 1000 ° C. ) in an inert gas (eg, nitrogen gas) atmosphere. ) . Then, after the annealing process, the semiconductor substrate 10 is taken out from the annealing furnace. When the semiconductor substrate 10 is taken out from the annealing furnace, it is performed in a gas atmosphere containing oxygen gas. The temperature at the time of taking out is also 600 ° C. or higher (desirably 800 ° C. to 900 ° C.) . Here, so-called unloading, which is taken out from the annealing furnace, is a process of transporting the semiconductor substrate 10 from the inside of the annealing furnace to the outside of the annealing furnace through the annealing furnace entrance / exit after completion of the annealing process. Although it is performed in a contained gas atmosphere, it is preferably performed in a gas atmosphere containing oxygen gas until the temperature of the semiconductor substrate 10 becomes less than 600 ° C. after the annealing process is completed.

Specifically, for example, as shown in FIG. 3, the semiconductor substrate 10 on which the interlayer insulating film 30 is formed is placed in an annealing furnace at 900 ° C. in a nitrogen gas atmosphere (Load). After putting the semiconductor substrate 10 in the annealing furnace, the temperature in the annealing furnace is raised from 900 ° C. to 1000 ° C. over 20 minutes in a nitrogen gas atmosphere (N _{2 in the} figure). Next, the inside of the annealing furnace is maintained at 1000 ° C. for 20 minutes under a nitrogen gas atmosphere. Next, the temperature in the annealing furnace is lowered from 1000 ° C. to 900 ° C. over 40 minutes in a nitrogen gas atmosphere. In this manner, the interlayer insulating film 30 formed on the semiconductor substrate 10 is annealed. Next, the semiconductor substrate 10 subjected to the annealing treatment is taken out from the annealing furnace in a gas atmosphere containing oxygen gas (O _{2 in the} drawing) (Unload). Then, the semiconductor substrate 10 is taken out in a gas atmosphere containing oxygen gas until the temperature of the semiconductor substrate 10 becomes less than 600 ° C.

  Here, the gas atmosphere containing oxygen gas means a gas atmosphere having an oxygen gas concentration in the range of 20% to 100%. More specifically, the gas atmosphere containing oxygen gas may be a gas atmosphere containing oxygen gas and inert gas (preferably nitrogen gas), for example.

  In addition, as a method of bringing the gas atmosphere containing oxygen gas into, for example, a method of bringing the environment outside the annealing furnace into a gas environment containing oxygen gas, a gas containing oxygen gas is sprayed on the surface of the semiconductor substrate 10. A method is mentioned. Among these, the method of spraying a gas containing oxygen gas onto the surface of the semiconductor substrate 10 is preferable because it can be easily performed in a gas atmosphere containing oxygen gas.

  Next, as shown in FIG. 2E, the gate electrode 28A, 28B, the source region 22A, and the drain region are formed on the annealed interlayer insulating film 30 by, for example, photolithography and reactive etching. A contact hole (opening for exposing a part of each part) is formed, and a source region 22A, a drain region 22B, and a gate electrode 28A are formed on the interlayer insulating film 30 by photolithography, sputtering, or the like. A wiring film 32 electrically connected to 28B is formed.

  Next, a plasma silicon nitride film (P-SiN) is formed at a temperature of 300 ° C. to 400 ° C. so as to cover the wiring film 32 (in this embodiment, to cover the entire surface of the semiconductor substrate 10) by, for example, plasma CVD. Film) and this is used as a passivation film 34 (third insulating film).

  Through the above steps, a semiconductor device (Lateral Power MOSFET using a reduced surface field (ESURF) structure) is manufactured.

  In the semiconductor device manufacturing method described above, after the interlayer insulating film 30 is formed on the semiconductor substrate 10, the semiconductor substrate 10 is placed in an annealing furnace and subjected to an annealing process at 600 ° C. or higher. Then, after the annealing process, the semiconductor substrate 10 is taken out from the annealing furnace. When the semiconductor substrate 10 is taken out from the annealing furnace, it is performed in a gas atmosphere containing oxygen gas. In the present embodiment, this corresponds to the last annealing process among the processes of annealing the semiconductor substrate 10 at 600 ° C. or higher.

  The change of the fixed charge generated by the fixed charge generated at the interface between the field oxide film 24 (first insulating film) and the semiconductor substrate 10 (for example, a silicon substrate) is known as a “deal triangle” (not described above). Based on this, Patent Literature 1) receives a thermal history of 600 ° C. or higher, and the fixed charge increases or decreases.

Therefore, in the semiconductor device manufacturing method according to the present embodiment, in the present embodiment, in the annealing process for the interlayer insulating film 30, the semiconductor substrate 10 is taken out from the annealing furnace after the annealing process is completed in a gas atmosphere containing oxygen gas. Perform the operation. In particular, after the annealing process, the process is performed in a gas atmosphere containing oxygen gas until the temperature of the semiconductor substrate 10 at which no fixed charge is generated becomes less than 600 ° C. As a result, a fixed charge (for example, at the interface between the field oxide film 24 (first insulating film) and the semiconductor substrate 10 (for example, a silicon substrate) (the interface between the field oxide film 24 and the drain drift region 16 including the high-resistance diffusion layer) is fixed. A positive fixed charge) is generated and maintained (see FIG. 4). The amount of generated fixed charges depends on the temperature at which the semiconductor substrate 10 is taken out of the annealing furnace, but is about 3 × E + 11 / cm ² at a temperature of 900 ° C., for example.

Due to the fixed charges generated at the interface between the field oxide film 24 and the semiconductor substrate 10, the region under the field oxide film 24 (the drain drift region 16 made of the high resistance diffusion layer ) is depleted. That is, since the obtained semiconductor device is in a state where the region under the field oxide film 24 is depleted in the initial stage, for example, a high voltage is applied between the source region 22A and the drain region 22B during the operation of the device, Even in the process where surface leakage current flows in the surface layer of the passivation film 34 formed on the outermost surface and electrons are gradually trapped in the surface layer of the passivation film (see FIG. 4), the region below the field oxide film (consisting of a high resistance diffusion region) It is considered that the occurrence of depletion of the (drain drift region) itself is suppressed, and as a result, the temporal change in the ON resistance is also suppressed with respect to the initial value.

  Here, in FIG. 5, in the semiconductor device obtained by the method of manufacturing a semiconductor device according to the present embodiment, a negative potential biased (electron trapped) in the outermost layer (passivation film 34), ON resistance variation, The figure which shows the relationship is shown (in the figure, it describes as embodiment). For comparison, when the interlayer insulating film 30 is annealed, the semiconductor substrate 10 is taken out from the annealing furnace in a nitrogen gas atmosphere instead of in a gas atmosphere containing oxygen gas, and the above relationship in the obtained semiconductor device is also shown in FIG. 5 (denoted as a comparative example in the figure). From the relationship shown in FIG. 5, in this embodiment, for example, when electrons are trapped in the surface layer of the passivation film 34 and a negative potential of −50 V is generated, the ON resistance fluctuation is reduced by about 40% compared to the comparative example. Recognize.

  As described above, in the method for manufacturing the semiconductor device according to the present embodiment, the temporal change of the ON resistance during operation can be easily reduced.

  Note that the above-described method for manufacturing a semiconductor device according to the present embodiment is not limitedly interpreted, and can be realized within a range that satisfies the requirements of the present invention.

10 semiconductor substrate 12 N-type well 14 P ^- -type diffusion region 16 drain drift region 18 P type diffusion region 20 ^{P +} -type diffusion region 22A source region 22B · drain region 24 field oxide film 26A, 26B a gate oxide film 28A, 28B a gate electrode 30 Interlayer insulating film 32 Wiring film 34 Passivation film

Claims (9)

Forming a source region and a drain region on a semiconductor substrate, and forming a high resistance diffusion region between the source region and the drain region and a field oxide film as a first insulating film on the high resistance diffusion region;
Forming a gate electrode on the semiconductor substrate;
Said gate electrode, said source region, said drain region, and on the first insulating film, forming a second insulating film,
It said semiconductor substrate having the second insulating film is formed, was subjected to annealing 600 ° C. or higher placed in an annealing furnace, a gas atmosphere in which oxygen gas is contained more than 20%, the said semiconductor substrate at 600 ° C. or higher Removing from the annealing furnace;
Forming a wiring film electrically connected to each of the gate electrode, the source region, and the drain region on the second insulating film;
Forming a third insulating film so as to cover at least the wiring film;
A method for manufacturing a semiconductor device comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is taken out of the annealing furnace in a gas atmosphere containing the oxygen gas and an inert gas.   The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is taken out of the annealing furnace under a gas atmosphere containing the oxygen gas and nitrogen gas.   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is taken out from the annealing furnace while a gas containing the oxygen gas is sprayed on a surface of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a LOCOS oxide film.   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is an interlayer insulating film.   The method of manufacturing a semiconductor device according to claim 6, wherein the interlayer insulating film is a silicon oxide film, a silicon nitride film, or a silicon oxide film to which phosphorus is added.   The method for manufacturing a semiconductor device according to claim 1, wherein the third insulating film is a passivation film.   The method for manufacturing a semiconductor device according to claim 8, wherein the passivation film is a plasma silicon nitride film.

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