JP5659520B2 - Drive signal control device, sensor control device, image reading device, and image forming device - Google Patents

Description

The present invention relates to a drive signal control apparatus, a sensor control apparatus including the same , an image reading apparatus such as a scanner including the sensor control apparatus or the drive signal control apparatus (image formation such as a digital copying machine, a digital multifunction peripheral , and a facsimile apparatus). The present invention relates to an image reading unit or a single image reading device mounted in the apparatus, and an image forming apparatus in which the image reading device is mounted.

For example, a scanner acquires reflected light from an image surface of a document (hereinafter, also simply referred to as “document”), and uses the reflected light on a CCD (Charge Coupled Device) disposed in a sensor substrate (SBU) that is a sensor control device. An image of a document is read by photoelectric conversion by an image sensor (hereinafter simply referred to as “CCD”) and converting it into an electrical signal.
The SBU mainly drives a CCD that photoelectrically converts reflected light from a document, an analog signal processing unit (AFE: Analog-Front-End ) that performs various analog processing on an output signal from the CCD, and a CCD or AFE. A timing generator (TG: Timing-Generator) that generates a driving signal for driving the CCD and a CCD driver (image sensor driver) that drives the CCD. The analog signal processing unit is constituted by an IC (integrated circuit). The analog signal processing IC corresponds to an analog signal processing device.

Drive signals and various gate signals necessary for driving the CCD and AFE (analog signal processing unit) are generated by the TG and input to the CCD and AFE.
The CCD drive signal generated by the TG is supplied to the CCD via the CCD driver, and the CCD photoelectrically converts the reflected light from the document and outputs it as an analog electrical signal.
The output analog electric signal is AC-coupled by a capacitor via a buffer circuit (configured by an emitter follower circuit) and input to the AFE.

  In the AFE, the reference black level is corrected to the internal reference voltage of the AFE by the clamp unit (clamp circuit), the image signal is sampled by the sample hold unit (sample hold circuit), and the analog image signal amplified by the amplification unit is converted to A Is converted into a digital image signal (image data) by a / D conversion unit (analog / digital conversion circuit), and data conversion is performed in a multiplex unit (multiplexer circuit), which is followed by an LVDS (Low Voltage Differential Signals) signal or a CMOS signal. To the image processing unit.

  Here, the processing performed by the AFE is performed in synchronization with the sample hold signal up to the A / D conversion unit, but the subsequent data conversion and image data output in the multiplex unit are synchronized with the master clock. Done. Therefore, in order to appropriately perform signal processing within the AFE, there are timing standards that must be satisfied at the AFE input for the sample hold signal and the master clock.

In recent years, due to the speeding up of the scanner, when the CCD is driven at high speed, the pixel period is short and the image signal area is narrowed. In the AFE, the image signal output from the CCD is sampled and held for a certain period, thereby securing a sample hold period. It has become difficult.
As a technique to deal with the above problem, the signal delay difference is suppressed by supplying the CCD drive timing signal and the sample hold signal, which are output from the TG, for determining the CCD output timing through the same CCD driver. A method for facilitating the timing management of the signal for determining the CCD output timing and the sample hold signal and ensuring the sample hold period is already known.

  However, by supplying the sample hold signal and the signal for determining the CCD output timing via the same CCD driver, the timing relationship between the sample hold signal and the master clock becomes indefinite, and the timing of the sample hold signal and the master clock at the AFE input. There is a problem that the standard cannot be satisfied and the image data cannot be synchronized between the A / D converter and the image data output unit.

Therefore, in order to solve the problem, it is conceivable to use the technique disclosed in Patent Document 1.
In Patent Document 1, a drive timing signal and a sample hold signal output from a timing generator are provided in the same element for the purpose of easily realizing the synchronization between the CCD output and the image signal extraction timing of the subsequent image signal processing system. It is disclosed that the timing management between the reading of the image signal and the sample hold and the timing management of the control signal for processing the image signal in the subsequent circuit can be easily performed through the (driver). Yes.

However, even the one described in Patent Document 1 cannot solve the problem that the image data cannot be synchronized between the A / D conversion unit and the image data output unit as described above.
The present invention has been made in view of the above points, and satisfies the timing standards of the sample hold signal and the master clock, and is provided with an A / D conversion means (A / D conversion section) and an image data output means (image data output). and an object thereof to be able to synchronize the image data in parts).

In order to achieve the above object, the present invention provides a drive signal control device, a sensor control device , an image reading device , and an image forming device shown in the following (1) to (10).

(1) A drive signal control device according to the present invention provides an image sensor that outputs an image signal based on reflected light from a document, an image sensor driver that drives the image sensor, and an image signal output from the image sensor. Sample and hold means for sampling and holding for a certain period to generate an analog image signal, A / D conversion means for converting the analog image signal generated thereby into digital image data, and the A / D conversion And a digital image data output means for outputting the digital image data converted by the means to a subsequent stage, and driving of the image sensor and the sample hold means, the A / D conversion means, Generates signals necessary for the processing of the digital image data output means A drive signal controller having a signal generating means, said signal generating means, the sample hold of the underlying signal of the signal for determining the execution timing and the digital image data signal and the same phase for determining the output timing have a phase controlling means for controlling, the signal which becomes the source, and the inverted and delayed through the image sensor driver is to signal for determining the execution timing of the sample hold.

(2) A drive signal control device according to the present invention is configured to output an image signal based on reflected light from a document, an image sensor driver for driving the image sensor, and an image signal output from the image sensor. Sample and hold means for sampling and holding for a certain period to generate an analog image signal, A / D conversion means for converting the analog image signal generated thereby into digital image data, and the A / D conversion And a digital image data output means for outputting the digital image data converted by the means to a subsequent stage, and driving of the image sensor and the sample hold means, the A / D conversion means, Generates signals necessary for the processing of the digital image data output means A drive signal controller having a signal generating means, said signal generating means, the common signal for determining the output timing of the underlying signal and the digital image data signals for determining the execution timing of the sample hold and outputs as a signal, a signal which becomes the source, and the inverted and delayed through the image sensor driver may be a signal for determining the execution timing of the sample hold.
(3) the sensor control device according to the invention is provided with a drive signal control device (1) or (2).
(4) The image reading apparatus according to the invention is provided with a sensor control device (3).

(5) The drive signal control apparatus according to the present invention also performs a sample hold for sampling an image signal output from an image sensor that outputs an image signal based on reflected light from a document and holding it for a certain period of time, thereby providing an analog image signal. Sample-and-hold means for generating A / D conversion means for converting the analog image signal generated thereby into digital image data, and digital image data output means for outputting the converted digital image data to the subsequent stage The analog signal processing apparatus can be provided, and the image sensor is driven, the signal generation means for generating signals necessary for the processing of the sample hold means and the digital image data output means, and the image sensor is driven. driving signal control unit der having an image sensor driver Te, the signal generating means, and a signal for determining an output timing of the signal and the digital image data to determine the execution timing of the sample hold have a phase control means for controlling in phase, the signal which becomes the source The signal may be inverted and delayed through the image sensor driver to determine the execution timing of the sample hold .

(6) The drive signal control apparatus according to the present invention further performs a sample hold for sampling an image signal output from an image sensor that outputs an image signal based on the reflected light from the document and holding it for a certain period of time, and an analog image signal Sample-and-hold means for generating A / D conversion means for converting the analog image signal generated thereby into digital image data, and digital image data output means for outputting the converted digital image data to the subsequent stage The analog signal processing apparatus can include a signal generation unit that generates signals necessary for driving the image sensor and processing of the sample hold unit and the digital image data output unit , and drives the image sensor. drive signal control device having an image sensor driver There, the signal generating means outputs a signal for determining the output timing of the underlying signal and the digital image data signals for determining the execution timing of the sample hold as a common signal, the said source signal was converted, inverted and delayed through the image sensor driver may be a signal for determining the execution timing of the sample hold.

(7) (5) or the drive signal control device (6) is to be provided with a said signal generating means to said analog signal processing device.
In the driving signal control apparatus (8) (7), the analog signal processing, an output terminal for outputting the original signal which becomes a signal for determining the execution timing of the sample hold, a signal outputted from the terminal the An input terminal for inputting through an image sensor driver may be provided, and the output terminal and the input terminal may be arranged adjacent to each other.
(9) by that image reading apparatus in the present invention may comprise a drive signal control device (8).
(10) by that image forming apparatus in this invention are (4) or (9) The image reading with the apparatus, an image forming apparatus that performs image forming processing on the basis of image data read by the image reading apparatus .

According to the present invention, the signal generation means of the drive signal control device has a master clock that is a signal that determines the output timing of the digital image data and a signal that is a source of the sample and hold signal that is a signal that determines the execution timing of the sample and hold Are controlled in the same phase (set to exactly the same phase), or output as a common signal (the signal up to the output of the signal generation means is a common signal), the above original signal is imaged a sample hold signal obtained by inverting and delaying through sensor driver, satisfy the timing standards of the master clock can be synchronized image data by the a / D converter and the image data output means.

It is a circuit diagram which shows the structural example of SBU which is 1st Embodiment of this invention. FIG. 2 is a timing diagram for explaining a timing standard of a sample hold signal (SPL) and a master clock (mclk_spl) in FIG. 1. It is a circuit diagram which shows the structural example of SBU which is 2nd Embodiment of this invention. FIG. 4 is a timing diagram for explaining the timing standard of the sample hold signal (SPL) and the master clock (XSPL) in FIG. 3 in comparison with the timing standard of the sample hold signal (SPL) and the master clock (mclk_spl) in FIG. 1. . It is a circuit diagram which shows the structural example of SBU which is 3rd Embodiment of this invention. It is a circuit diagram which shows the structural example of SBU which is 4th Embodiment of this invention. FIG. 7 is a circuit diagram illustrating a configuration example of the TG built-in AFE 400 of FIG. 6.

It is a circuit diagram which shows the 1st example of a structure of the conventional SBU. It is a circuit diagram which similarly shows the 2nd example of a structure of SBU. FIG. 10 is a timing chart for explaining timing standards of the sample hold signal (SPL) and the master clock (mclk) in FIG. 9. FIG. 10 is a timing diagram for explaining a problem when the timing relationship between SPL and mclk becomes indefinite in the conventional drive configuration shown in FIG. 9. Similarly, it is another timing chart for explaining a problem when the timing relationship between SPL and mclk becomes indefinite. It is a circuit diagram which shows the 3rd example of a structure of the conventional SBU. It is a circuit diagram which similarly shows the 4th example of a structure of SBU.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
The following embodiments have the following characteristics when sample-holding an image signal output from a CCD. In other words, the master clock is set to the same phase as the signal that is the source of the sample hold signal, or the master clock and the source signal of the sample hold signal are common until the TG output, and the sample hold signal is passed through the CCD driver. By supplying the master clock directly to the AFE, the sample hold signal is input to the AFE with a delay of the CCD driver delay with respect to the master clock, so the timing relationship between the sample hold signal and the master clock is automatic. The image data can be synchronized between the A / D converter and the image data output unit.

Therefore, its features will be described in detail. Before entering the description, for convenience of understanding, the signal flow in the SBU (sensor substrate) mounted on the conventional scanner and the problems of the SUB are described. Will be described with reference to FIGS. Although the timing generator (TG) will be described as an example of a separate chip from the analog front end (AFE), a configuration in which the TG is built in the AFE may be used.
FIG. 8 is a circuit diagram showing a first example of the configuration of a conventional SBU.

  A scanner equipped with this SBU (corresponding to a sensor control device) obtains reflected light from a document, photoelectrically converts it into an electrical signal by a CCD arranged in the SBU, and converts the image of the document into an electrical signal. Read (not shown). Among them, the SBU mainly drives the CCD 1 that photoelectrically converts the reflected light from the original, the AFE 10 (corresponding to an analog signal processing device) that performs various analog processing on the output signal from the CCD 1, and the CCD 1 or the AFE 10. The timing generator (TG) 2 that generates a drive signal for driving and a plurality of CCD drivers 3 and 4 that drive the CCD 1 are configured.

Driving signals and various gate signals (not shown) necessary for driving the CCD 1 and the AFE 10 are generated by the TG 2 which is a signal generating means and input to the CCD 1 and the AFE 10.
Clocks (φ1, φ2, φ2L, RS, CP) necessary for driving the CCD 1 generated by the TG 2 are input to the CCD 1 via the CCD drivers 3 and 4. The CCD drivers 3 and 4 may be either a buffer type or an inverter type, but an inverter type is generally used from the viewpoint of high speed.

  Here, φ1 / φ2 is a transfer clock for transferring the signal charge obtained by the photodiode (PD) in the CCD 1 on the analog shift register, and φ2L is a transfer clock at the final stage. RS is a reset signal for resetting the signal charge accumulated in the floating capacitor (FJ) that detects the signal charge transferred to the output stage as a voltage, and CP is an arbitrary reference for the output signal of the CCD 1. This is a clamp signal that is adjusted (clamped) to a voltage. In addition to the above signals, there is a shift gate signal for transferring the signal charge obtained by the PD once per line to the analog shift register, which is not shown.

The analog image signal output from the CCD 1 is AC-coupled by a capacitor 6 via a buffer circuit 5 (configured by an emitter follower circuit) and input to an analog signal processing unit (AFE) 10.
The image signal input to the AFE 10 is first input to the clamp circuit 11, and the clamp circuit 11 sets the black offset level of the image signal to a predetermined potential.
The sample hold circuit (S / H circuit) 12 is a sample hold means, samples the image signal output from the clamp circuit 11 at the input timing of the sample hold signal (SPL) from the TG 2, and outputs the sampled image signal. The image signal is output as a continuous analog image signal by holding for a certain time (sample holding).

The amplification circuit (PGA) 13 amplifies the output of the analog image signal to a certain level, and then the analog / digital conversion circuit (ADC) 14 as A / D conversion means converts the amplified analog image signal into a digital image signal ( Image data) and converted in the multiplexer circuit 15 serving as digital image data output means, and output as an LVDS signal (which may of course be a CMOS signal or a TTL signal).
A sample hold signal (SPL) and a master clock (mclk) necessary for driving the AFE 10 are generated by the TG 2 and input to each circuit in the AFE 10.

  Here, the processing performed in the AFE 10 is performed in synchronization with the sample and hold signal up to the analog / digital conversion circuit 14, but data conversion in the subsequent multiplexer circuit (multiplexer unit) 15 and output of image data are performed. Is performed in synchronization with the master clock. Therefore, in order to appropriately perform signal processing in the AFE 10, there are timing standards that must be satisfied at the input of the AFE 10 for the sample hold signal and the master clock.

  In recent years, CCD 1 has been driven at a higher speed in order to increase scanner productivity. When the CCD 1 is driven at high speed, the pixel period is shortened and the image signal area is also narrowed. Therefore, various timing standards defined between the drive signals of the CCD 1 and sample hold for sampling the image signal and holding it for a certain period of time. It is becoming difficult to satisfy the period.

Therefore, for example, as shown in FIG. 9, by supplying a signal (φ2L, RS) for determining the output timing of the CCD 1 and a sample hold signal (SPL) through the same CCD driver 4 ′, a delay difference between the signals is obtained. Therefore, a technique has been devised that makes it easy to secure the sample hold period even during high-speed driving by controlling the timing of the image signal (CCD_out) output from the CCD 1 and the SPL.
FIG. 9 is a circuit diagram showing a second example of the configuration of a conventional SBU. The same parts as those in FIG. 8 are denoted by the same reference numerals.
FIG. 10 is a timing chart for explaining the timing standard of the sample hold signal (SPL) and the master clock (mclk) of FIG.

As a result, the sample hold period can be easily secured, but by supplying the sample hold signal (SPL) to the AFE 10 via the CCD driver 4 ', the timing relationship between the sample hold signal (SPL) and the master clock (mclk). Is undefined.
In order to appropriately perform signal processing in the AFE 10, there are timing standards at the input of the AFE 10 as shown in FIG. 10 for SPL and mclk. In mclk ↑ −SPL ↓ (t1) and SPL ↓ −mclk ↓ (t2), a minimum value to be secured is defined, a sample hold period is secured, and t1 and t2 must be satisfied. . Therefore, timing management between SPL and mclk signals is also important.

FIGS. 11 and 12 are timing diagrams for explaining problems when the timing relationship between SPL and mclk becomes indefinite in the conventional drive configuration shown in FIG.
FIG. 11 shows a case where the SPL phase is advanced (the mclk phase is delayed), and FIG. 12 shows a case where the SPL phase is delayed (the mclk phase is advanced). 11A and 12A show the optimum timing relationship between SPL and mclk. FIG. 11B shows a case where t1 is the minimum value defined, and FIG. 11C shows a case where t1 is not satisfied. (B) of FIG. 12 shows a case where the period t2 is the minimum value defined, and (c) shows a case where t2 is not satisfied.

If the timing relationship between SPL and mclk becomes indefinite, there is a possibility that the timing standard between the two signals cannot be satisfied, as shown in FIG. 11 and FIG. In that case, during the signal processing in the AFE 10, A / D converted image data performed in synchronization with the SPL, and an image in the image data output unit (multiplexer circuit 15) operating in synchronization with the mclk at the subsequent stage. A problem occurs that data cannot be synchronized. Note that the same problem occurs in the TG built-in AFE as shown in FIGS. 13 and 14, but the problem will be supplementarily described later.
Therefore, in order to solve the above-described problem, each embodiment of the present invention will be described below.

[First Embodiment]
First, a first embodiment of the present invention will be specifically described with reference to FIGS.
FIG. 1 is a circuit diagram showing a configuration example of an SBU according to the first embodiment of the present invention. The same reference numerals are given to the same portions as those in FIGS.
FIG. 2 is a timing chart for explaining the timing standards of the sample hold signal (SPL) and the master clock (mclk_spl) of FIG. In the figure, a solid line indicates SPL input to the AFE 10, and a broken line indicates spl (signal based on SPL) output from TG2.

In order to properly perform signal processing in the AFE 10, there are timing standards at the input of the AFE 10 as shown in FIG. 10 in SPL and mclk, but the timing relationship is indefinite as shown in FIGS. Then, the timing standards for t1 and t2 cannot be satisfied.
Therefore, the TG 2 ′ constituting the signal generation means uses a plurality of circuits including a delay circuit and a latch circuit (not shown), so that a signal spl that is a source of SPL that is a signal for determining the execution timing of sample and hold, and digital The mclk, which is a signal for determining the output timing of the image data, is controlled to the same phase. That is, as shown in FIG. 1, the phase setting of mclk at TG2 ′ is set to the signal mclk_spl having the same setting as the signal spl that is the source of SPL. This function is a function as phase control means.

Thus, the signal spl the 'logic is inverted by, a CCD driver 4' CCD driver 4 by inputting and outputting, to Mclk_spl, with only always the delay of the delay (T_delay) caused by the CCD driver 4 ', as SPL AFE10 2 and the SPL and mclk_spl are input to the sample hold circuit 12 and the multiplexer circuit 15, respectively, so that the standards of t1 and t2 can be automatically satisfied as shown in FIG. it can be synchronized image data 14 (a / D conversion section) and the multiplexer circuit 15 (the image data output unit).

[Second Embodiment]
Next, a second embodiment of the present invention will be specifically described with reference to FIGS.
FIG. 3 is a circuit diagram showing a configuration example of the SBU according to the second embodiment of the present invention, and the same reference numerals are given to the same portions as those in FIG.
The SBU circuit of the second embodiment is an improvement of the SBU circuit of the first embodiment shown in FIG.

FIG. 4 is a diagram for explaining the timing standard of the sample hold signal (SPL) and the master clock (XSPL) of FIG. 3 in comparison with the timing standard of the sample hold signal (SPL) and the master clock (mclk_spl) of FIG. It is a timing diagram.
FIG. 4A shows the variation of SPL with respect to mclk_spl in the circuit configuration of FIG. In the figure, the solid line indicates the optimal timing (typ timing) of the SPL input to the AFE 10, and the broken line indicates the variation of the SPL with respect to mclk_spl input to the AFE 10. (B) of the same figure shows the dispersion | variation in SPL with respect to XSPL in the circuit structure of FIG. In the figure, the solid line indicates the optimum timing (typ timing) of the SPL input to the AFE 10, and the broken line indicates the variation of the SPL with respect to the XSPL input to the AFE 10.

Here, in the first embodiment (the circuit configuration shown in FIG. 1), the signals spl and mclk_spl, which are the sources of SPL , have the same phase, but are different signals, and therefore, the gate-to-gate skew at the output of TG2 ′. Therefore, as shown in FIG. 4A, the delay time varies greatly.
In the second embodiment, as shown in FIG. 3, the underlying signal and mclk was a common signal XSPL to the output of TG2 '(i.e. the underlying signal and mclk and a common signal XSPL the SPL of SPL Is then output from TG2 ′), then the signal XSPL is branched into two, one is input to AFE 10 as SPL via the same CCD driver 4 ′ as RS, and the other is left as XSPL (mclk) To the AFE 10.

Thereby, in addition to the effect similar to 1st Embodiment, the following effect is also acquired. That is, there is no skew between the SPL source signal and the XSPL signal at the output of the TG 2 ′, and the delay variation between the signals can be reduced as shown in FIG.
So far, the case where the TG and the AFE are configured as separate chips has been described, but the same applies to the TG built-in AFE. However, in the case of a conventional TG built-in type AFE 100 as shown in FIG. 13, for example, a signal necessary for driving the AFE 100 can be supplied without being output to the outside. As in the case of the circuit described above, the sample hold period cannot be secured.

Therefore, a terminal that outputs a signal that is a source of SPL and a terminal that inputs SPL are provided , and for example, as shown in FIG. 14, a signal that is a source of SPL output from TG2 is once output from AFE 200, and φ2L , RS is input to the AFE 200 as SPL via the same CCD driver 4 'as that of RS, so that the sample hold period can be easily secured. However, a problem similar to that of the circuit shown in FIG. 9 occurs.
Therefore, also in the TG built-in AFE, as described with reference to FIGS. 1 and 3, the control that causes the SPL source signal and mclk to have the same phase, or the SPL source signal and mclk as a common signal. I do.

[Third Embodiment]
Next, a third embodiment of the present invention will be specifically described with reference to FIG.
FIG. 5 is a circuit diagram showing a configuration example of an SBU according to the third embodiment of the present invention, and the same reference numerals are given to the same portions as those in FIG.
Also in the SBU of the third embodiment, the timings of the signals spl and mclk, which are the sources of SPL, are the same as those in the first embodiment (when TG and AFE are separate chips) described with reference to FIG. The phase setting of mclk in TG 2 ′ of type AFE 300 is set to mclk_spl, which is the same as the signal spl that is the source of SPL.

As a result, the logic of the spl is inverted by the CCD driver 4 ′ and input / output of the CCD driver 4 ′ is surely delayed by the delay (T_delay) by the CCD driver 4 ′ and input to the TG built-in type AFE 300 as SPL. Therefore, the t1 and t2 standards can be automatically satisfied as shown in FIG. 2, and the analog / digital conversion circuit 14 and the multiplexer circuit 15 can synchronize the image data.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be specifically described with reference to FIG.
FIG. 6 is a circuit diagram showing a configuration example of the SBU according to the fourth embodiment of the present invention. The same reference numerals are given to the same parts as those in FIG.
In the SBU of the fourth embodiment, as in the second embodiment described above with reference to FIG. 3 (when TG and AFE are separate chips), the SPL source signal and mclk are shared up to the output of TG2 ′. and signal XSPL, then branches the signal XSPL two inputs one Fai2L, the TG embedded AFE400 as SPL via the same CCD driver 4 'and RS, the other remains XSPL (mclk Equivalent to

Thereby, in addition to the effect similar to 3rd Embodiment, the following effect is also acquired. That is, there is no skew between the SPL source signal and the XSPL signal at the output of the TG 2 ′, and the delay variation between the signals can be reduced as shown in FIG.
FIG. 7 is a circuit diagram showing a configuration example of the TG built-in AFE 400 of FIG.
The TG built-in AFE 400 has an output terminal 401 that outputs a signal that is a source of SPL , and an input terminal 402 that inputs a signal output from the output terminal 401 via the CCD driver 4 'shown in FIG. it by, Fai2L, supplies SPL through the same CCD driver 4 'the RS and SPL, to suppress the variation of the delay difference between the signals, it is possible to easily secure the sample and hold period.

Here, when the pin arrangement of the signal output terminal 401 that is the source of the SPL and the input terminal 402 of the SPL are distant from each other, the wiring length becomes long and the layout of the circuit board becomes difficult. In particular, when driving at a low speed so that the sample hold signal does not need to be supplied via the same CCD driver 4 'as φ2L and RS, the pin arrangement is made adjacent to each other, compared to when the pin arrangement is far away. , it is possible to shorten the wiring on the circuit board to a minimum, since Ru can reduce the circuit scale as shown, it is possible to facilitate the layout of the base.
The TG built-in AFE 300 shown in FIG. 5 can be provided with similar input / output terminals.

  As described above, the embodiment in which the present invention is applied to an SBU that can be mounted on a scanner that reads an image of a document by a CCD has been described. Of course, such SBUs can be mounted on other image reading devices that read the image of the original document with these image sensors, image reading devices on which these SBUs are mounted, digital copiers and facsimile machines on which these image reading devices are mounted. The present invention can also be applied to various image forming apparatuses such as printers. The image forming apparatus main body can print the image data from the image reading apparatus on a print medium as a visible image.

As apparent from the above description, according to the present invention, it satisfies the timing specification of the sample-and-hold signal and the master clock can be synchronized image data by the A / D converter and the image data output means. Therefore, it is possible to provide a drive signal control device, a sensor control device , an image reading device , and an image forming device that can always generate an optimal drive signal.

1: CCD 2, 2 ': Timing generator (TG)
3, 4, 4 ': CCD driver 5: Buffer circuit 6: Capacitor 10, 100-400: Analog signal processing unit (AFE)
11: Clamp circuit 12: Sample hold circuit 13: Amplifier circuit 14: Analog / digital conversion circuit 15: Multiplexer circuit 401: Output terminal 402: Input terminal

Japanese Patent Application Laid-Open No. 11-177783

Claims (10)

An image sensor that outputs an image signal based on reflected light from a document, an image sensor driver that drives the image sensor, and a sample hold that samples and holds the image signal output from the image sensor for a certain period of time, Sample hold means for generating an analog image signal, A / D conversion means for converting the analog image signal generated by the sample hold means into digital image data, and digital image data converted by the A / D conversion means A signal that can be provided in a sensor control device having digital image data output means for outputting to a subsequent stage, and that generates signals necessary for processing of the image sensor and processing of the sample hold means and the digital image data output means. A drive signal control device having a generation means ,
Said signal generating means, have a phase control means for controlling the signal for determining the output timing of the underlying signal and said digital image data signals for determining the execution timing of the sample-and-hold in phase,
The drive signal control apparatus characterized in that the original signal is inverted and delayed through the image sensor driver to determine the execution timing of the sample and hold . An image sensor that outputs an image signal based on reflected light from a document, an image sensor driver that drives the image sensor, and a sample hold that samples and holds the image signal output from the image sensor for a certain period of time, Sample hold means for generating an analog image signal, A / D conversion means for converting the analog image signal generated by the sample hold means into digital image data, and digital image data converted by the A / D conversion means A signal that can be provided in a sensor control device having digital image data output means for outputting to a subsequent stage, and that generates signals necessary for processing of the image sensor and processing of the sample hold means and the digital image data output means. A drive signal control device having a generation means ,
The signal generating means outputs , as a common signal , a signal that determines the execution timing of the sample and hold and a signal that determines the output timing of the digital image data ,
The drive signal control apparatus characterized in that the original signal is inverted and delayed through the image sensor driver to determine the execution timing of the sample and hold .   A sensor control apparatus comprising the drive signal control apparatus according to claim 1.   An image reading apparatus comprising the sensor control apparatus according to claim 3. A sample-and-hold unit that samples an image signal output from an image sensor that outputs an image signal based on reflected light from a document and holds it for a certain period, and generates an analog image signal; and the sample-and-hold unit An analog signal processing apparatus having A / D conversion means for converting the generated analog image signal into digital image data, and digital image data output means for outputting the digital image data converted by the A / D conversion means to the subsequent stage A signal generation unit that generates signals necessary for processing of the image sensor and processing of the sample hold unit and the digital image data output unit, and an image sensor driver that drives the image sensor. A drive signal control device comprising:
Said signal generating means, have a phase control means for controlling the signal for determining the output timing of the underlying signal and said digital image data signals for determining the execution timing of the sample-and-hold in phase,
The drive signal control apparatus characterized in that the original signal is inverted and delayed through the image sensor driver to determine the execution timing of the sample and hold . A sample-and-hold unit that samples an image signal output from an image sensor that outputs an image signal based on reflected light from a document and holds it for a certain period, and generates an analog image signal; and the sample-and-hold unit An analog signal processing apparatus having A / D conversion means for converting the generated analog image signal into digital image data, and digital image data output means for outputting the digital image data converted by the A / D conversion means to the subsequent stage A signal generation unit that generates signals necessary for processing of the image sensor and processing of the sample hold unit and the digital image data output unit, and an image sensor driver that drives the image sensor. A drive signal control device comprising:
The signal generating means outputs , as a common signal , a signal that determines the execution timing of the sample and hold and a signal that determines the output timing of the digital image data ,
The drive signal control apparatus characterized in that the original signal is inverted and delayed through the image sensor driver to determine the execution timing of the sample and hold . 7. The drive signal control device according to claim 5, wherein the analog signal processing device includes the signal generation unit . The drive signal control device according to claim 7,
The analog signal processing device includes: an output terminal that outputs a signal that is a source of a signal that determines the execution timing of the sample and hold; and an input terminal that inputs a signal output from the terminal through the image sensor driver. The drive signal control device is characterized in that the output terminal and the input terminal are arranged next to each other. An image reading apparatus comprising the drive signal control apparatus according to claim 8.   An image forming apparatus comprising the image reading apparatus according to claim 4, wherein an image forming process is performed based on image data read by the image reading apparatus.

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