JP5662080B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing apparatus.

  As in a large-scale signal processing system, there is a data processing system in which a plurality of data processing devices are connected to each other by a cable and data is transferred. In such a data processing system, when each data processing device is turned on, initialization such as resetting of a circuit such as a communication unit is executed in each data processing device.

  For example, in the health check system and its health check method, when a packet other than the health check is sent from the non-health check packet generator to the NMS, the non-health check packet generator sends a reset signal to the timer, On the other hand, within the NMS, the communication status determination unit determines the communication status between the NMS and the NE for all management NEs, and a health check packet and a non-health check packet are sent from a specific NE for a predetermined period. If not, a means for determining that the communication state between the NE and the NMS is abnormal has been proposed.

  Further, in the line concentrator and its reset management method, the line concentrator to which a plurality of network devices can be connected includes a communication management unit that controls transfer processing of information between the network devices, and information obtained from the communication management unit A condition determination unit that determines whether or not a condition to be reset is satisfied, and a reset control that controls a reset signal that is supplied to the communication management unit and resets the communication management unit based on the determination by the condition determination unit Has been proposed.

  Further, in the communication apparatus having the redundant common unit, when the failure detection unit detects its own failure, the active common unit notifies the standby common unit of the failure, and the standby common unit is notified from the active common unit. When the failure notification is received, the individual unit failure masking unit starts masking individual unit failure information notified from each individual unit, and then detects a system selection signal for changing the self from the standby system to the active system, A configuration has been proposed in which the individual unit failure detection unit of each individual unit is reset and then the individual unit failure information masking by the individual unit failure mask unit is released.

Japanese Patent Laid-Open No. 11-163839 Japanese Patent No. 3861226 JP-A-8-316881

  For example, as shown in FIG. 7A, the data processing apparatus 100 and the data processing apparatus 200 are connected by a cable 500 and communicate with each other. In this case, as shown in FIG. 7B, when the connection of the cable 500 is poor or when the data processing apparatus 100 is powered off, the data processing apparatus 200 cannot receive correct data. Receive indefinite data. In this case, the data processing apparatus 200 may enter an error state as a result of operating based on indefinite data.

  Thereafter, as shown in FIG. 7C, the user who knows that the data processing device 200 has entered an error state returns the connection of the cable 500 to the normal state, or the data processing device 100 is powered on. It is thrown.

  Further, in order for the data processing apparatus 200 to recover from the error state, the data processing apparatus 200 is reset from the outside as shown in FIG. The reset from the outside is, for example, when a user who knows that the data processing apparatus 200 has entered an error state presses the reset switch by a manual operation. In other words, the data processing device 200 cannot spontaneously recover from the error state.

  Further, as shown in FIG. 7D, when each of a large number of data processing devices 100 to 400 is connected in a complicated manner, if the reset order is incorrect, the data processing device 200 may not be initialized properly. is there. For example, even if only the data processing device 200 is reset, the processing may not be started correctly for various reasons.

  It is an object of the present invention to provide a data processing device that is reset based on a received signal.

The disclosed data processing device includes a receiving circuit that receives a signal, a signal processing unit that processes a signal received by the receiving circuit, and a predetermined number of predetermined data patterns from the signal received by the receiving circuit. Monitor that outputs the reset release state of the reset signal when extracted continuously, and outputs the reset state of the reset signal in cases other than when a predetermined number of predetermined data patterns are extracted continuously A circuit and a reset control circuit for releasing the reset of the receiving circuit based on the reset release state of the reset signal. The receiving circuit further stores a signal received by the data processing device and outputs the signal at a predetermined timing, and stores a signal output from the first buffer circuit at a predetermined timing. And a second buffer circuit for outputting. The reset control circuit outputs the reset state of the first reset control signal based on the reset state of the reset signal, and outputs the reset release state of the first reset control signal based on the reset release state of the reset signal. The reset release state of the second reset control signal is output after a predetermined time interval has elapsed from the output of the reset state of the first reset control signal, and the first buffer circuit performs the first reset control. After the reset is performed by the reset state of the signal, the reset is canceled by the reset release state of the first reset control signal, and the first buffer circuit is reset by the reset state of the first reset control signal, and then predetermined from the reset. At a predetermined time interval, the second buffer circuit is reset by the reset release state of the second reset control signal. Tsu is capital released.

According to the data processing apparatus disclosed, from the received signal, when extracted by continued several series defined the predetermined data pattern in advance, it can be reset release based on the extraction, normally Can recover from an error condition.

It is a figure which shows an example of a structure of a data processor. It is a figure which shows another example of a structure of a data processor. It is explanatory drawing of operation | movement of a data processor. It is explanatory drawing of operation | movement of a data processor. It is explanatory drawing of operation | movement of a data processor. It is explanatory drawing of operation | movement of a data processor. It is explanatory drawing of the technique used as the background which this inventor examined.

  FIG. 1 is a diagram illustrating an example of a configuration of a data processing apparatus.

  The data processing device includes a first data processing device 1, a second data processing device 2, and cables 3A to 3D that connect them. The first data processing device 1 and the second data processing device 2 transfer data to each other. The cables 3A to 3D are, for example, optical fiber cables that perform serial transmission in both directions. The cables 3 </ b> A to 3 </ b> D are connected to a plurality of communication ports provided in the second data processing device 2.

  In FIG. 1, the first data processing device 1 transmits a signal to the second data processing device 2, and the second data processing device 2 receives the signal transmitted from the first data processing device 1. In other words, FIG. 1 shows a case where the first data processing device 1 is a transmitting device and the second data processing device 2 is a receiving device.

  As described above, the second data processing device 2 also transmits a signal to the first data processing device 1, and the first data processing device 1 receives the signal transmitted from the second data processing device 2. To do. Both the first data processing device 1 and the second data processing device 2 are transmission / reception devices that transmit and receive signals. Therefore, the first data processing device 1 includes the same configuration as the second data processing device 2.

  The second data processing device 2 includes a plurality of receiving circuits 10A to 10D, a plurality of monitoring circuits 20A to 20D, one reset control circuit 30, and one signal processing unit 40. The reception circuits 10A to 10D are provided corresponding to the cables 3A to 3D, in other words, corresponding to each of the plurality of communication ports of the second data processing device 2. The monitoring circuits 20A to 20D are provided corresponding to the receiving circuits 10A to 10D. A plurality of reception circuits 10A to 10D and a plurality of monitoring circuits 20A to 20D constitute a reception processing unit 50.

  The receiving circuits 10 </ b> A to 10 </ b> D may receive not only signals from the first data processing device 1 but also signals from various data processing devices other than the first data processing device 1. In other words, the cables 3A to 3D may be connected to different data processing devices, respectively. Further, when a plurality of data processing devices are connected to each other as shown in FIG. 7D, each data processing device is provided with the reception processing unit 50 and the reset control circuit 30 shown in FIG. Anyway.

  The receiving circuits 10A to 10D receive the signal transmitted from the first data processing device 1 via the cables 3A to 3D, execute the receiving process on the received signal, and perform signal processing on the result of the signal processing To the unit 40.

  The signal processing unit 40 performs data processing on the signals received from the receiving circuits 10A to 10D. In other words, the signal processing unit 40 is a signal processing unit that processes a signal received by the receiving circuit.

  For example, the monitoring circuits 20 </ b> A to 20 </ b> D take in a signal transmitted through the receiving circuits 10 </ b> A to 10 </ b> D, form a reset signal based on the taken signal, and output the reset signal to the reset control circuit 30. Specifically, the monitoring circuits 20A to 20D output a reset state (for example, a low level signal) of a reset signal or output a reset release state (for example, a high level signal) of the reset signal. The monitoring circuits 20A to 20D output a reset release state of the reset signal when the power of the second data processing device 2 is turned on.

  The reset signal is in either the reset release state or the reset state. The reset release state of the reset signal is a signal that instructs to release the reset state. The reset state of the reset signal is a signal instructing to set the reset release state to the reset state.

  The reset control circuit 30 forms a reset control signal based on the reset signal received from the monitoring circuits 20A to 20D, resets or cancels the receiving circuits 10A to 10D using the reset control signal, and a signal processing unit 40 is reset or released. Specifically, the reset control circuit 30 forms a reset state of the first and second reset control signals based on the reset state of the reset signal, and resets the receiving circuits 10A to 10D and the signal processing unit 40. Further, the reset control circuit 30 forms a reset release state of the first and second reset control signals based on the reset release state of the reset signal, and releases the reset of the reception circuits 10A to 10D and the signal processing unit 40. As will be described later, since the timings of forming the first and second reset control signals are different, the receiving circuits 10A to 10D and the signal processing unit 40 are reset at different timings and released from reset.

  The reset control signal is in either the reset release state or the reset state. The reset release state of the reset control signal is a signal for actually releasing the reset state. The reset state of the reset control signal is a signal that actually sets the reset release state to the reset state.

  FIG. 2 is a diagram showing details of the configuration of the data processing device. Mainly, the receiving circuit 10D of the second data processing device 2, the monitoring circuit 20D, the reset control circuit 30D, and the function processing unit 40D corresponding thereto are shown. Indicates.

  For example, the reception circuit 10D includes a reception unit 11, a reception FIFO 12, a command control unit 13, a reception control unit 14, and an output FIFO 15. The receiving circuits 10A to 10C also include the same circuit as the receiving circuit 10D and execute the same processing.

  The monitoring circuit 20D is a circuit corresponding to the receiving circuit 10D. In other words, the monitoring circuit 20D is a partial circuit corresponding to the receiving circuit 10D in the monitoring circuit including the monitoring circuits 20A to 20D. For example, the monitoring circuit 20D takes in a signal transmitted through the reception circuit 10D and forms a reset signal RST [3] based on the signal. The monitoring circuits 20A to 20C also execute the same processing as the monitoring circuit 20D. The reset signals formed by the monitoring circuits 20A to 20C are represented as RST [0] to RST [2], respectively.

  The reset control circuit 30D is a partial circuit corresponding to the reception circuit 10D in the reset control circuit 30. The reset control circuit 30D uses the reset control signal formed based on the reset signal RST [3] received from the monitoring circuit 20D to reset or release the reception circuit 10D and reset or release the function processing unit 40D. . The reset control circuits 30A to 30C also execute the same process as the reset control circuit 30D.

  The function processing unit 40D is a partial circuit corresponding to the reception circuit 10D in the signal processing unit 40. In other words, the signal processing circuit 40 includes partial circuits corresponding to the receiving circuits 10A to 10D. The function processing unit 40D performs data processing on the signal received from the receiving circuit 10D, and realizes a predetermined signal processing function. Each of the function processing units 40A to 40C executes a predetermined process that is different from that of the function processing unit 20D.

  The receiving unit 11 receives a signal from the outside of the second data processing device 2, in other words, from the first data processing device 1 via the cable 3 </ b> D. The reception unit 11 stores the received signal in the reception FIFO 12. Specifically, the receiving unit 11 converts an optical signal (serial signal) received via the cable 3D into an electric signal (serial signal) in an OE conversion circuit. Thereafter, in the serial-parallel conversion circuit, the reception unit 11 converts the electrical signal (serial signal) output from the OE conversion circuit into a parallel signal. The parallel signal has a predetermined bit width, for example, an 8-bit width. Further, the reception unit 11 stores the parallel signals output from the serial / parallel conversion circuit in the reception FIFO 12 in the order of reception.

  The receiving unit 11 receives a frame signal from the first data processing device 1 via the communication path 3D prior to receiving the data signal. The frame signal is a signal that instructs the start of a frame, for example. The start position of the frame is determined by the frame signal. As a result, the reception unit 11 can convert the received signal into an 8-bit width parallel signal and store it in the reception FIFO 12 in the order of reception.

  The receiving unit 11 is not reset by a reset control signal described later, and is not released from the set. This is because the receiving unit 11 simply inputs the received signal to the receiving FIFO 12 as it is, and does not need to be reset. Therefore, no reset control signal is input to the receiving unit 11.

  The reception FIFO 12 is a first buffer circuit, stores the signal received by the reception unit 11, and outputs it to the command control unit 13 at a predetermined timing. For example, the reception FIFO 12 stores the 8-bit parallel signal from the reception unit 11 in the unit buffer circuit in the order of reception, and the signal stored in the four unit buffer circuits as one data (or packet). Are collectively output to the command control unit 13.

  Thereby, 32-bit data including four consecutive 8-bit parallel signals is formed. For this purpose, the reception FIFO 12 includes, for example, four or more unit buffer circuits. The reception FIFO 12 inputs four 8-bit data to the command control unit 13 as one 32-bit data. In other words, the reception FIFO 12 converts the signal received by the reception unit 11 into 32-bit data.

  As described above, the reception FIFO 12 processes the signal input from the reception unit 11 every 32 bits. Therefore, the 32-bit data output from the reception FIFO 12, in other words, four consecutive parallel signals are represented as a data signal IRXD [31: 0]. The command control unit 13, the reception control unit 14, the output FIFO 15, and the function processing unit 40D also execute processing for each data signal IRXD [31: 0].

  The reception FIFO 12 is reset by the reset state of the first reset control signal 1ST-XRST [3]. In addition, the reception FIFO 12 is released from the reset state by the reset release state of the first reset control signal 1ST-XRST [3].

  The first reset control signal 1ST-XRST [3] is a signal for resetting the reception FIFO 12, for example, and is formed by the reset control circuit 30D. The first reset control signal 1ST-XRST [3] will be described later. Note that the first reset control signals formed by the reset control circuits 30A to 30C are represented as 1ST-XRST [0] to 1ST-XRST [2], respectively.

  The command control unit 13 extracts a command from the signal output from the reception FIFO 12, in other words, from the data signal IRXD [31: 0]. The bit position of the command is set to a predetermined bit position in the data signal IRXD [31: 0]. Thereby, the command control part 13 can extract a command. The command control unit 13 outputs the extracted command and the data signal IRXD [31: 0] to the reception control unit 14.

  The command control unit 13 is reset by the reset state of the first reset control signal 1ST-XRST [3]. Further, the command control unit 13 is released from the reset by the reset release state of the first reset control signal 1ST-XRST [3]. Therefore, the command control unit 13 is controlled by the same first reset control signal 1ST-XRST [3] at the same timing as the reception FIFO 12.

  The reception control unit 14 performs reception control on the signal output from the reception FIFO 12, in other words, the data signal IRXD [31: 0]. Specifically, the reception control unit 14 outputs the extracted data signal IRXD [31: 0] received from the command control unit 13 to the output FIFO 15 to output to the function processing unit 40D via the output FIFO 15. . Further, the reception control unit 14 outputs the extracted command received from the command control unit 13 to the function processing unit 40D. At this time, the reception control unit 14 controls the output timing of the command and the output timing of the output FIFO 15. Thus, the data signal IRXD [31: 0] and the command extracted from the data signal IRXD [31: 0] are output to the function processing unit 40D at the same or predetermined timing.

  The reception control unit 14 is reset by the reset state of the second reset control signal 2ND-XRST [3]. Further, the reception control unit 14 is released from the reset state by the reset release state of the second reset control signal 2ND-XRST [3].

  The second reset control signal 2ND-XRST [3] is a signal for resetting the output FIFO 15, for example, and is formed by the reset control circuit 30D. The second reset control signal 2ND-XRST [3] will be described later. Note that the second reset control signals formed by the reset control circuits 30A to 30C are represented as 2ND-XRST [0] to 2ND-XRST [2], respectively. The reception control unit 14 is controlled by the same second reset control signal 2ND-XRST [3] at the same timing as the output FIFO 15.

  The output FIFO 15 is a second buffer circuit, stores the signal output from the reception FIFO 12, in other words, the data signal IRXD [31: 0], and is sent to the function processing unit 40D at the timing controlled by the reception control unit 14. Output. Thus, in the function processing unit 40D, the data signal IRXD [31: 0] is processed according to the command extracted from the data signal IRXD [31: 0].

  The output FIFO 15 is reset by the reset state of the second reset control signal 2ND-XRST [3]. Further, the output FIFO 15 is released from reset by the reset release state of the second reset control signal 2ND-XRST [3].

  The function processing unit 40D is reset by the reset state of the second reset control signal 2ND-XRST [3]. Further, the function processing unit 40D is released from the reset state by the reset release state of the second reset control signal 2ND-XRST [3]. Accordingly, the function processing unit 40D is controlled by the same second reset control signal 2ND-XRST [3] at the same timing as the output FIFO 15. The function processing unit 40D may be controlled by a reset control signal formed later than the second reset control signal 2ND-XRST [3] at a later timing than the output FIFO 15.

  When the power of the second data processing device 2 is turned on, the monitoring circuit 20D outputs the reset release state of the reset signal RST [3]. Accordingly, the receiving circuit 10D and the function processing unit 40D are brought into a reset release state by the reset control circuit 30D in response to power-on.

  The monitoring circuit 20D takes in a signal transmitted through the receiving circuit 10D, and monitors the taken-in signal, in other words, the signal received by the receiving circuit 10D. Specifically, the monitoring circuit 20D outputs the reset state of the reset signal RST [3] when a predetermined data pattern is not extracted from the signal received by the reception circuit 10D and output from the reception FIFO 12. On the other hand, the monitoring circuit 20D resets the reset signal RST [3] when a predetermined number of data patterns are continuously extracted from the signal received by the receiving circuit 10D and output from the reception FIFO 12. The release status is output.

  The predetermined data pattern is a status signal indicating that the first data processing device 1 and the cable 3D connected to the receiving circuit 10D are both normal. In other words, when either the first data processing device 1 that is a transmission device or the cable 3D that is a communication path is abnormal, a predetermined data pattern is not received. The predetermined data pattern will be described later.

  The reason why the reset release state is output when a predetermined number of data patterns are continuously extracted is that undefined data may coincide with the predetermined data pattern by chance. As a result, even if indefinite data coincides with a predetermined data pattern by chance, it is possible to prevent the reset from being released immediately and to perform the reset release in a stable communication state. The predetermined number will be described later.

  In practice, when the monitoring circuit 20D extracts a predetermined data pattern in the other monitoring circuits 20A to 20C, the monitoring circuit 20D counts the predetermined data pattern extracted from the signal received by the corresponding receiving circuit 10D. To do. Then, when the count value reaches a predetermined value, the monitoring circuit 20D outputs a reset release state of the reset signal RST [3].

  For this purpose, as shown in FIG. 2, a status flag which is information indicating whether or not a predetermined data pattern has been extracted in the other monitoring circuits 20A to 20C is input to the monitoring circuit 20D. For example, the status flag is input to the monitoring circuit 20D from the other monitoring circuits 20A to 20C. The status flag indicates whether or not each of the other monitoring circuits 20A to 20C has extracted a predetermined data pattern at that time. The status flag will be described later.

  Thereby, for example, in a certain monitoring circuit 20D, the reset release state of the reset signal RST [3] can be output based on the monitoring state in the other monitoring circuits 20A to 20C. For example, when all of the signals received by the four reception circuits 10A to 10D are normal, the reset cancellation can be executed for each of the reception circuits 10A to 10D. Note that when only the signal received by the receiving circuit 10D becomes normal, the reset release may be executed only for the receiving circuit 10D.

  The reset control circuit 30D outputs the reset state of the first reset control signal 1ST-XRST [3] based on the reset state of the reset signal RST [3]. Further, the reset control circuit 30D outputs the reset release state of the first reset control signal 1ST-XRST [3] based on the reset release state of the reset signal RST [3].

  After the reset signal RST [3] is output in the reset state, in other words, the reset control circuit 30D is output at the first time interval after the first reset control signal 1ST-XRST [3] is output in the reset state. The reset release state of the second reset control signal 2ND-XRST [3] is output. Therefore, at least after the reception FIFO 12 is reset by the reset state of the first reset control signal 1ST-XRST [3], the output FIFO 15 is changed to the second reset control signal 2ND-XRST [3] at the first time interval. The reset is released by the reset release state.

  In the receiving circuit 10D, the first time interval is determined according to the receiving circuit 10D and is determined in advance. Therefore, the first time interval may be different for each of the receiving circuits 10A to 10D.

  Thereby, the reset of the output FIFO 15 can be released at the timing when the correct data received by the reception FIFO 12 reaches the output FIFO 15 after the reset. In other words, since the data stored in the output FIFO 15 at the time of resetting the reception FIFO 12 is not correct data, it is possible to prevent the data from being validated.

  Actually, the reset control circuit 30D outputs the second reset control signal 2ND-XRST when the reset release states of the reset signals RST [0] to RST [2] are output from the other monitoring circuits 20A to 20C. The reset release state of [3] is output. In other words, the reset control circuit 30D includes the second reset control signal 2ND-XRST when the reset release states of the reset signals RST [0] to RST [2] are formed in all the monitoring circuits 20A to 20D. The reset release state of [3] is output. For this reason, as shown in FIG. 2, reset signals RST [0] to RST [3] are input to the reset control circuit 30D from the other monitoring circuits 20A to 20C. For example, the reset control circuit 30D detects the rise of the reset signals RST [0] to RST [3] from the low level to the high level, thereby changing the reset release state of the second reset control signal 2ND-XRST [3]. Output. As a result, as shown in FIG. 4 to be described later, the second reset control signals 2ND-XRST [0] to 2ND-XRST [3] are output from the reset state output of the reset signals RST [0] to RST [3]. The time until the output of the reset release state is different.

  Hereinafter, an example of the reset process in the second data processing apparatus 2 will be described in detail with reference to FIGS. 3 to 4 show an example of the reset process in the second data processing device 2 together, and receive when all the signals received by the four receiving circuits 10A to 10D are normal. An example in which reset release is executed for each of the circuits 10A to 10D will be described.

  Note that the signal rst_flg and the signal rst_flg_cnt in FIG. 3 are again illustrated in FIG. 4 in order to clarify the relationship between FIG. 3 and FIG. Further, the reset signals RST [0] to RST [3] are signals formed in the monitoring circuits 20A to 20D, but are connected to the first reset control signals 1ST-XRST [0] to 1ST-XRST [3]. For comparison, FIG. 4 shows the column of the reset control circuit.

  When the data processing device 2 is turned on, the reset signals RST [0] to RST [3] are released from the reset state (high) by the monitoring circuits 20A to 20D as shown in FIG. Level) is formed. Further, based on the power-on and the reset release state (high level) of the reset signals RST [0] to RST [3], the reset control circuits 30A to 30D perform the first reset control signal 1ST-XRST [0]. A reset release state (high level) of ˜1ST-XRST [3] is formed, and a reset state (low level) of the second reset control signals 2ND-XRST [0] to 2ND-XRST [3] is formed.

  As a result, in the receiving circuits 10A to 10D, the reception FIFO 12 and the command control unit 13 are released from reset, and the reception control unit 14 and the output FIFO 15 are reset. In other words, the reception FIFO 12 and the command control unit 13 execute normal processing, and the reception control unit 14 and the output FIFO 15 are reset each time in synchronization with the reference clock. Therefore, the data signal reception process can be executed in response to the power-on, while the reception control unit 14 and the output FIFO 15 can be prevented from malfunctioning due to an indefinite data signal. Further, the function receivers 40A to 40D are reset, in other words, reset each time in synchronization with the reference clock. Therefore, it is possible to prevent the function receiving units 40A to 40D from malfunctioning due to an indefinite data signal.

  In FIG. 3, for example, a clock signal CLOCK is an internal clock in the second data processing apparatus 2 and is supplied as a reference clock to all circuits. In synchronization with one cycle of the clock signal CLOCK, 32-bit data, in other words, the data signal IRXD [31: 0] is output from the reception FIFO 12 and processed in a circuit such as the command control unit 13 in the subsequent stage.

  Based on the frame signal, the receiving unit 11 converts the signal received from the first data processing device 1 via the cable 3D into an 8-bit parallel signal, and inputs the converted signal to the reception FIFO 12 in the order received.

  The reception FIFO 12 stores the 8-bit parallel signal from the reception unit 11 in the four unit buffer circuits in the order of reception. As a result, a 32-bit data signal IRXD [31: 0] is formed and input to the command control unit 13.

  The monitoring circuit 20D takes in the data signal IRXD [31: 0] output from the reception FIFO 12. Thereafter, the monitoring circuit 20D detects a predetermined data pattern that is a state signal indicating normality, and detects an enable signal for the reset state output of the reset signal RST [3].

  Specifically, the monitoring circuit 20D extracts signals at a plurality of bit positions in the data signal IRXD [31: 0] as status signals. Specifically, the monitoring circuit 20D stores signals at a plurality of bit positions in the data signal IRXD [31: 0] in a predetermined register. A plurality of bit positions to be extracted are determined in advance. For example, a signal from the 31st bit to the 24th bit, in other words, an 8-bit signal IRXD [31:24] in the data signal IRXD [31: 0] is extracted. In other words, the status signal indicating normality is stored in a predetermined bit position, in other words, in the position from the 31st bit to the 24th bit in the data signal IRXD [31: 0].

  The position where the status signal is stored may be different for each of the receiving circuits 10A to 10D. For example, as shown in FIG. 3 described later, the signal IRXD [23:16] from the 23rd bit to the 16th bit is extracted from the data signal [31: 0] received by the receiving circuit 10C.

  Further, the monitoring circuit 20D extracts signals at two bit positions in the data signal IRXD [31: 0] as two enable signals. The monitoring circuit 20D stores signals at two bit positions in the data signal IRXD [31: 0] in two predetermined registers. The two bit positions to be extracted are determined in advance. In other words, the two enable signals are stored at predetermined positions in the data signal IRXD [31: 0]. By using two enable signals, it is possible to variously control the timing of forming state signals idle_flg0 to idle_flg3 described later.

  The two enable signals formed by the monitoring circuit 20D are referred to as IRXC [3] and IRXH [3], respectively. The enable signals corresponding to IRXC [3] formed by the monitoring circuits 20A to 20C are represented as IRXC [0] to IRXC [2]. The enable signals corresponding to IRXH [3] formed by the monitoring circuits 20A to 20C are represented as IRXH [0] to IRXH [2]. Further, the position where the two enable signals are stored may be different for each of the receiving circuits 10A to 10D. Thereby, as shown in FIG. 3 to be described later, state flags idle_flg0 to idle_flg3 are formed at different timings.

  The monitoring circuit 20D determines whether or not the value of the extracted signal IRXD [31:24] is “BC” in hexadecimal. In other words, “BC” in hexadecimal is a predetermined data pattern, and for example, K28.5 in IEEE 802.3ae can be used. Specifically, the monitoring circuit 20D compares the output of the register storing the extracted signal IRXD [31:24] with “BC” in hexadecimal in the coincidence detection circuit, and determines whether or not they match. To detect. When the value of the signal IRXD [31:24] is “BC” in hexadecimal, a predetermined data pattern is detected, and the cable connected to the first data processing device 1 and the receiving circuit 10D. It can be seen that 3D is normal. The predetermined data pattern may be “1C” in hexadecimal.

  The monitoring circuit 20D forms a status flag idle_flg3 based on the data signal IRXD [31: 0], the enable signal IRXC [3], and the enable signal IRXH [3]. Note that the status flags formed by the monitoring circuits 20A to 20C are respectively represented as idle_flg0 to idle_flg2.

  Specifically, when the value of the signal IRXD [31:24] is “BC” in hexadecimal, the monitoring circuit 20D has the enable signal IRXC [3] at the high level and the enable signal IRXH [3] at the low level. In some cases, the high level of the status flag idle_flg3 is output. For example, when the output of the register storing the extracted signal IRXD [31:24] matches “BC” in hexadecimal, the coincidence detection circuit has the enable signal IRXC [3] at the high level and the enable signal IRXH [ 3] is a low level, a high level is output.

  As shown in FIG. 3, the status flags idle_flg0 to idle_flg3 are different from each other in bit positions used for forming the status flags idle_flg0 to idle_flg3. This is because the bit positions of a predetermined data pattern used for forming the status flags idle_flg0 to idle_flg3 are different. In other words, the bit position of the predetermined data pattern is determined according to the receiving circuits 10A to 10D, in other words, according to the transmitting device.

  Further, the timing flags idle_flg0 to idle_flg3 are formed at different timings. This is because the timing of the enable signals used for forming the status flags idle_flg0 to idle_flg3 is different. In other words, the timing of the enable signal is determined according to the receiving circuits 10A to 10D, in other words, according to the transmitting device.

  Now, as indicated by the oblique lines for the signal IRXD [31:24] in FIG. 3, for some reason, the value of the signal IRXD [31:24] becomes a state that is not “BC” in hexadecimal. Accordingly, the monitoring circuit 20D cannot extract the predetermined data pattern “BC” from the data signal IRXD [31: 0]. Therefore, the monitoring circuit 20D outputs the low level of the status flag idle_flg3. Also, the other monitoring circuits 20A to 20C cannot extract the predetermined data pattern “BC”, and output the low level of the status flags idle_flg0 to idle_flg2.

  Thereafter, for some reason, the value of the signal IRXD [31:24] becomes “BC” in hexadecimal. Thereby, the monitoring circuit 20D can extract a predetermined data pattern “BC” from the data signal IRXD [31: 0]. Therefore, the monitoring circuit 20D outputs the high level of the status flag idle_flg3 at the timing when the enable signal IRXC [3] is high level and the enable signal IRXH [3] is low level. The other monitoring circuits 20A to 20C also extract a predetermined data pattern “BC” and output the high level of the status flags idle_flg0 to idle_flg2.

  The monitoring circuit 20D counts the period during which the high level of the status flag idle_flg3 is output in the first counter circuit in synchronization with the clock signal CLOCK. The count value of the first counter circuit is referred to as a signal cnt_idle. The counter circuit of the monitoring circuit 20D is counted up to “2”, for example.

  However, for some reason, the value of the signal IRXD [31:24] again becomes a state that is not “BC” in hexadecimal. As a result, the monitoring circuit 20D cannot extract the predetermined data pattern “BC” from the data signal IRXD [31: 0], and outputs the low level of the status flag idle_flg3. Also, the other monitoring circuits 20A to 20C cannot extract the predetermined data pattern “BC”, and output the low level of the status flags idle_flg0 to idle_flg2.

  Here, as described above, information indicating whether or not a predetermined data pattern has been extracted in the other monitoring circuits 20A to 20C, in other words, a status flag is input to the monitoring circuit 20D. The counter circuit of the monitoring circuit 20D is cleared when any one of the status flags idle_flg0 to idle_flg3 goes low. Therefore, as shown in FIG. 3, the counter circuit of the monitoring circuit 20D is cleared by the low level of the state flag idle_flg3 and the low level of the state flag idle_flg1.

  As a result, at this time, the reset release state (high level) of the reset signal RST [3] remains formed. Further, the reset release state (high level) of the first reset control signal 1ST-XRST [3] is kept formed, and the reset state (low level) of the second reset control signal 2ND-XRST [3] is formed. It will be kept.

  After this, for some reason, the value of the signal IRXD [31:24] again becomes “BC” in hexadecimal. Thereby, the monitoring circuit 20D can extract a predetermined data pattern “BC” from the data signal IRXD [31: 0]. Therefore, the monitoring circuit 20D outputs the high level of the status flag idle_flg3 at the timing when the enable signal IRXC [3] is high level and the enable signal IRXH [3] is low level. The other monitoring circuits 20A to 20C also extract a predetermined data pattern “BC” and output the high level of the status flags idle_flg0 to idle_flg2.

  In the first counter circuit, the monitoring circuit 20D counts the period during which the high level of the status flag idle_flg3 is output in synchronization with the clock signal CLOCK and counts up to the maximum value of the first counter circuit. The maximum value of the first counter circuit is predetermined. The maximum value of the first counter circuit is the aforementioned predetermined number. By determining the maximum value of the first counter circuit, it is possible to detect that a predetermined number of data patterns have been continuously extracted.

  When the value of the signal cnt_idle reaches the maximum value of the first counter circuit, the monitoring circuit 20D outputs the high level of the signal rst_flg. Furthermore, the monitoring circuit 20D outputs the reset state (low level) of the reset signal RST [3] based on the high level of the signal rst_flg.

  The reset control circuit 30D outputs the reset state (low level) of the first reset control signal 1ST-XRST [3] based on the reset state (low level) of the reset signal RST [3]. As a result, the reception FIFO 12 and the command control unit 13 are reset.

  Even if the reception FIFO 12 is reset, if the data signal received after the reset includes a predetermined data pattern “BC”, the reception FIFO 12 can correctly receive the data signal. Therefore, the predetermined data pattern “BC” is correctly extracted and counted. Therefore, there is no problem in forming the reset signal RST [3] and the like.

  On the other hand, the monitoring circuit 20D counts the period during which the high level of the signal rst_flg is output in the second counter circuit in synchronization with the clock signal CLOCK. The count value of the second counter circuit is referred to as a signal rst_flg_cnt. When the value of the signal rst_flg_cnt reaches the maximum value of the second counter circuit, the monitoring circuit 20D sets the reset signal RST [3] to a high level.

  The reset control circuit 30D sets the first reset control signal 1ST-XRST [3] to a high level based on the high level of the reset signal RST [3]. The high level signal is not taken in by the reception FIFO 12 and the command control unit 13 and is an invalid signal.

  Also in the monitoring circuits 20A to 20C, reset states (low level) of the reset signals RST [0] to RST [2] are formed, and the low level signal is subsequently set to the high level.

  Also in the reset control circuits 30A to 30C, the first reset control signals 1ST-XRST [0] to 1ST-XRST [2 are based on the reset state (low level) of the reset signals RST [0] to RST [2]. ] Is formed, and this low level signal is then set to the reset release state (high level).

  As described above, the reset control circuit 30D performs the second reset at a first time interval after the reset state of the reset signal RST [3] or the first reset control signal 1ST-XRST [3] is formed. The reset release state of the control signal 2ND-XRST [3] is output.

  Therefore, the maximum value of the second counter circuit is the first time interval. The maximum value of the second counter circuit is predetermined. By determining the maximum value of the second counter circuit, the second reset is performed at a first time interval after the reset state of the reset signal RST [3] or the first reset control signal 1ST-XRST [3] is formed. The reset state of the control signal 2ND-XRST [3] can be set.

  Actually, as described above, in all the monitoring circuits 20A to 20D, after the reset release states (high level) of the reset signals RST [0] to RST [3] are formed, the reset control circuits 30A to 30D The reset release states of the second reset control signals 2ND-XRST [0] to 2ND-XRST [3] are output. In other words, the second reset control signals 2ND-XRST [0] to 2ND-XRST [3] are the same signal.

  When the reset is released, as described above, the 32-bit data signal IRXD [31: 0] is output from the reception FIFO 12, and the command is extracted from the data signal IRXD [31: 0] in the command control unit 13. When the reception control unit 14 performs reception control, the data signal IRXD [31: 0] is sent to the function processing unit 40D via the output FIFO 15 together with the command extracted from the data signal IRXD [31: 0]. Sent and processed in the function processing unit 40D.

  5 to 6 show another example of the reset process in the second data processing device 2 together, and any of the signals received by the four receiving circuits 10A to 10D is normal. An example in which reset release is executed only for the receiving circuits 10A to 10D is shown. 5 to 6, it is assumed that the signal received by the receiving circuit 10D is normal and the reset process for the receiving circuit 10D is executed.

  Note that the signal rst_flg and the signal rst_flg_cnt in FIG. 5 are again illustrated in FIG. 6 in order to clarify the relationship between FIG. 5 and FIG. Further, the reset signals RST [0] to RST [3] are signals formed in the monitoring circuits 20A to 20D, but are connected to the first reset control signals 1ST-XRST [0] to 1ST-XRST [3]. For comparison, FIG. 6 shows the reset control circuit column.

  When the power of the data processing device 2 is turned on, the reset signals RST [0] to RST [3] in the reset release state (high level), as shown in FIG. Reset control signals 1ST-XRST [0] to 1ST-XRST [3] in a reset release state (high level) and reset states of the second reset control signals 2ND-XRST [0] to 2ND-XRST [3] (Low level) is formed. As a result, in the receiving circuits 10A to 10D, the reception FIFO 12 and the command control unit 13 are released from reset, and the reception control unit 14 and the output FIFO 15 are reset. Further, the function receiving units 40A to 40D are reset.

  Now, as indicated by the oblique lines for the signal IRXD [31:24] in FIG. 5, for some reason, the value of the signal IRXD [31:24] becomes a state that is not “BC” in hexadecimal. As a result, the monitoring circuit 20D cannot extract the predetermined data pattern “BC” from the data signal IRXD [31: 0], and outputs the low level of the status flag idle_flg3. Also, the other monitoring circuits 20A to 20C cannot extract the predetermined data pattern “BC”, and output the low level of the status flags idle_flg0 to idle_flg2.

  Thereafter, for some reason, the value of the signal IRXD [31:24] becomes “BC” in hexadecimal. As a result, the monitoring circuit 20D extracts a predetermined data pattern “BC” from the data signal IRXD [31: 0], the enable signal IRXC [3] is at the high level, and the enable signal IRXH [3] is at the low level. At this timing, the high level of the status flag idle_flg3 is output. The other monitoring circuits 20A to 20C also extract a predetermined data pattern “BC” and output the high level of the status flags idle_flg0 to idle_flg2.

  The monitoring circuit 20D counts the period during which the high level of the status flag idle_flg3 is output in the first counter circuit in synchronization with the clock signal CLOCK. The count value of the first counter circuit, in other words, the signal cnt_idle is counted up to, for example, “4” unlike FIG.

  However, for some reason, the value of the signal IRXD [31:24] again becomes a state that is not “BC” in hexadecimal. As a result, the monitoring circuit 20D cannot extract the predetermined data pattern “BC” from the data signal IRXD [31: 0], and outputs the low level of the status flag idle_flg3. Also, the other monitoring circuits 20A to 20C cannot extract the predetermined data pattern “BC”, and output the low level of the status flags idle_flg0 to idle_flg2.

  Here, in the examples of FIGS. 5 and 6, unlike the examples of FIGS. 3 and 4, whether or not the data patterns predetermined in the other monitoring circuits 20A to 20C have been extracted to the monitoring circuit 20D. In other words, the status flag is not input. Therefore, in the example of FIGS. 5 and 6, there is no input from the other monitoring circuits 20A to 20C shown in FIG. 2 to the monitoring circuit 20D. The counter circuit of the monitoring circuit 20D is cleared when the state flag idle_flg3 becomes low level. Therefore, the counter circuit of the monitoring circuit 20D is cleared by the low level of the status flag idle_flg3 as shown in FIG. 5, unlike FIG.

  As a result, at this time, the reset release state (high level) of the reset signal RST [3] remains formed. Further, the reset release state (high level) of the first reset control signal 1ST-XRST [3] is kept formed, and the reset state (low level) of the second reset control signal 2ND-XRST [3] is formed. It will be kept.

  After this, for some reason, the value of the signal IRXD [31:24] again becomes “BC” in hexadecimal. Thereby, the monitoring circuit 20D can extract a predetermined data pattern “BC” from the data signal IRXD [31: 0]. Therefore, the monitoring circuit 20D outputs the high level of the status flag idle_flg3 at the timing when the enable signal IRXC [3] is high level and the enable signal IRXH [3] is low level.

  On the other hand, unlike FIG. 3, the other monitoring circuits 20A to 20C do not extract the predetermined data pattern “BC”, and the status flags idle_flg0 to idle_flg2 remain at the low level.

  In the first counter circuit, the monitoring circuit 20D counts the period during which the high level of the status flag idle_flg3 is output in synchronization with the clock signal CLOCK and counts up to the maximum value of the first counter circuit.

  When the value of the signal cnt_idle reaches the maximum value of the first counter circuit, the monitoring circuit 20D outputs the high level of the signal rst_flg. Furthermore, the monitoring circuit 20D outputs the reset state (low level) of the reset signal RST [3] based on the high level of the signal rst_flg.

  The reset control circuit 30D outputs the reset state (low level) of the first reset control signal 1ST-XRST [3] based on the reset state (low level) of the reset signal RST [3]. As a result, the reception FIFO 12 and the command control unit 13 are reset. However, even if the reception FIFO 12 is reset, as described above, the predetermined data pattern “BC” is correctly received, extracted, and counted.

  On the other hand, the monitoring circuit 20D counts the period during which the high level of the signal rst_flg is output in the second counter circuit in synchronization with the clock signal CLOCK. When the count value of the second counter circuit, in other words, the value of the signal rst_flg_cnt reaches the maximum value of the second counter circuit, the monitoring circuit 20D sets the reset signal RST [3] to the high level.

  The reset control circuit 30D sets the first reset control signal 1ST-XRST [3] to a high level based on the high level of the reset signal RST [3]. The high level signal is not taken in by the reception FIFO 12 and the command control unit 13 and is an invalid signal.

  On the other hand, in the monitoring circuits 20A to 20C, unlike FIG. 4, the reset state (low level) of the reset signals RST [0] to RST [2] is not formed, and remains at the high level. Also in the reset control circuits 30A to 30D, unlike FIG. 4, the reset state (low level) of the first reset control signals 1ST-XRST [0] to 1ST-XRST [2] is not formed, and the high level To be left.

  As described above, after the reset state (low level) of the reset signal RST [3] or the first reset control signal 1ST-XRST [3] is formed, the reset control circuit 30D has a first time interval. The reset release state of 2 reset control signal 2ND-XRST [3] is output.

  In FIG. 6, unlike FIG. 4, after the reset state (low level) of the reset signal RST [3] is formed in the monitoring circuit 20D, the reset signals RST [0] to RST in the other monitoring circuits 20A to 20C are formed. Regardless of [2], the reset control circuit 30D outputs the reset release state of the second reset control signal 2ND-XRST [3] at the first time interval. Therefore, unlike the examples of FIGS. 3 and 4, in the examples of FIGS. 5 and 6, the reset control circuit 30 </ b> D receives the reset signal RST [0 from the monitoring circuits 20 </ b> A to 20 </ b> C other than the corresponding monitoring circuit 20 </ b> D. ] To RST [2] are not input. Therefore, in the example of FIGS. 5 and 6, there is no input from the other monitoring circuits 20A to 20C shown in FIG. 2 to the reset control circuit 30D.

  When the reset is released, as described above, the 32-bit data signal IRXD [31: 0] is output from the reception FIFO 12, and the command is extracted from the data signal IRXD [31: 0] in the command control unit 13. When the reception control unit 14 performs reception control, the data signal IRXD [31: 0] is sent to the function processing unit 40D via the output FIFO 15 together with the command extracted from the data signal IRXD [31: 0]. Sent and processed in the function processing unit 40D.

1, 2 Data processing device 3A to 3D cable 10A to 10D Reception circuit 11 Reception unit 12 Reception FIFO
13 Command Control Unit 14 Reception Control Unit 15 Output FIFO
20A to 20D Monitoring circuit 30 Reset control circuit 40 Signal processing unit

Claims (7)

A receiving circuit for receiving a signal;
A signal processing unit for processing the signal received by the receiving circuit;
When a predetermined number of predetermined data patterns are continuously extracted from the signal received by the receiving circuit, a reset release state of a reset signal is output, and the predetermined data pattern is A monitoring circuit that outputs a reset state of the reset signal in a case other than a case where a predetermined number is extracted continuously ;
A reset control circuit for releasing the reset of the receiving circuit based on a reset release state of the reset signal,
Said receiving circuit further stores a signal data processing apparatus receives and stores a first buffer circuit for outputting at a predetermined timing, the signal first buffer circuit outputs, in advance A second buffer circuit that outputs at a predetermined timing,
The reset control circuit, based on the reset state of the reset signal, and outputs the reset state of the first reset control signal, based on the reset release state of the reset signal, the reset release of the first reset control signal Output a reset state of the second reset control signal after a predetermined time interval has elapsed from the output of the reset state of the first reset control signal,
The first buffer circuit is reset by a reset state of the first reset control signal, and is reset by a reset release state of the first reset control signal;
After the first buffer circuit is reset by the reset state of the first reset control signal, the second buffer circuit is configured to output the second reset control signal at the predetermined time interval from the reset. The data processing device is characterized in that the reset is released in accordance with the reset release state. When the monitoring circuit does not extract the predetermined data pattern from the signal received by the receiving circuit, the reset state of the reset signal is output,
The data processing apparatus according to claim 1, wherein the reset control circuit resets the reception circuit based on a reset state of the reset signal. The receiving circuit is provided corresponding to a plurality of communication ports of the data processing device;
The monitoring circuit is provided corresponding to each of the plurality of receiving circuits;
When each of the plurality of monitoring circuits extracts a predetermined data pattern in another monitoring circuit, the predetermined data pattern extracted from the signal received by the corresponding receiving circuit is counted. The data processing apparatus according to claim 1. The data processing apparatus according to claim 1, wherein the reception circuit further includes a reception unit that receives the signal from outside the data processing apparatus via a cable. The receiving circuit further includes a command control unit that extracts a command from a signal output from the first buffer circuit,
The data processing apparatus according to claim 4, wherein the command control unit is released from a reset according to a reset release state of the first reset control signal. The data processing apparatus according to claim 4, wherein the reception circuit further includes a reception control unit that performs reception control on a signal output from the first buffer circuit. The data processing apparatus according to claim 6, wherein the reception control unit and the signal processing unit are released from reset according to a reset release state of the second reset control signal.

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