JP5662702B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image management technique.

  In a process involving image deformation such as geometric deformation, since the pixel positions of the input image and the output image are different, a method of generating an output image via a storage unit such as a frame memory is used. Since the storage unit for the frame memory is required to store a data size equivalent to that of the input image, an inexpensive and large-capacity first storage unit such as a dynamic RAM (DRAM) is generally used. A DRAM can realize a large-sized storage unit at a relatively low cost structurally compared to a static RAM (SRAM), but has a disadvantage that a data access latency is relatively long.

  In the case of processing using a DRAM, since the access latency of the DRAM is relatively long, a phenomenon in which the memory access of the DRAM becomes a bottleneck and the processing throughput is reduced can usually occur. Specifically, since the access latency from when the image processing module requests data at an arbitrary address on the DRAM to when the data comes back is long, the processing of the image processing module stops during that time, and the processing module alone has Throughput decreases with respect to peak performance. As a method for solving this problem, a static RAM (SRAM) or the like has an auxiliary storage unit that has a high cost per size but a short access latency, and stores necessary data partially in the SRAM in advance. There is a method for improving the throughput of processing.

  As a first method for storing necessary data in the SRAM in advance, there is a method called prefetch. With prefetching, the processing module issues the address of the next required data in the DRAM in advance and stores the data in the SRAM, and this data is stored in the SRAM until the processing module actually needs the data. Can be stored. By doing so, it is possible to conceal the access latency of the DRAM and to operate without stopping the processing module, so that the throughput can be improved.

  As a second method for storing necessary data in the SRAM in advance, there is a method described in Patent Document 1. In Patent Literature 1, when performing image rotation processing, an input image is divided into a plurality of image blocks, and the image blocks are read from the first storage unit in an order corresponding to the rotation angle, and the auxiliary storage unit (in the literature) Stored in buffer memory). Next, pixel data is read from the image block in the buffer memory in the order corresponding to the rotation angle. Rotation of the input image is performed by applying the reading according to the rotation angle of the image block from the first storage unit and the reading according to the rotation angle of the pixel data from the auxiliary storage unit to all the image blocks of the input image. Do.

  According to the method of Patent Document 1, the reading order of image blocks is uniquely determined by the rotation angle. Further, since the rotation processing of each image block is completed within the image block, if the access address to the first storage unit is stored, a technique equivalent to prefetch can be realized without sequentially performing address calculation.

JP 2002-125116 A

  In the first prior art, the image processing module must have a mechanism for prefetching. Since prefetching must be executed prior to data consumption of the image processing module, the image processing module needs to have two independent address issuing mechanisms (fetch, prefetch). In processing involving image deformation such as geometric deformation, the ratio of the address issuing mechanism to the entire circuit of the image processing module is relatively large, and there is a problem in terms of cost and power consumption.

  The second conventional technique can perform the same as prefetch without sequentially performing address calculation, but has a problem that the rotation angle of an image is limited to an angle completed within a single image block. Specifically, when the image block is rectangular, the processable rotation angle is limited to a multiple of 90 degrees, and arbitrary shape deformation cannot be performed.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique for realizing arbitrary shape deformation without having a prefetch mechanism that occupies a relatively large proportion in an image deformation processing circuit. To do.

In order to achieve the object of the present invention, an image processing apparatus as an example of the present invention comprises the following arrangement. That is, storage means for storing the input image;
Obtaining means for obtaining an instruction for deforming the input image;
Whether or not it is necessary to refer to the image data of the input image in order to generate a display screen including a deformed image according to the instruction is determined for each of a plurality of regions constituting the display screen. Thus, determination means for determining the number of times that the reference of the image data of the input image is necessary for the generation of the display screen for each of the plurality of regions constituting the input image,
When the number of times the image data of one area constituting the input image is referred to generate the display screen reaches the number determined by the determining means, the image data of the one area is stored. And a control means for controlling the area of the storage means to be overwritable .

  According to the configuration of the present invention, it is possible to realize an arbitrary shape deformation without having a prefetch mechanism that occupies a relatively large proportion in the image deformation processing circuit, thereby reducing the circuit scale.

FIG. 3 is a block diagram illustrating an example of a functional configuration of the image processing apparatus. The figure explaining an access sequence list. 10 is a flowchart of processing performed by the access sequence determination unit 104. The figure which shows the process in which an access sequence list is produced. 10 is a flowchart of processing performed by the memory read unit. The flowchart of the process which the block data management part 107 performs. The figure explaining an access sequence list.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. The embodiment described below shows an example when the present invention is specifically implemented, and is one of the specific examples of the configurations described in the claims.

[First Embodiment]
First, the image processing apparatus according to the present embodiment will be described with reference to the block diagram of FIG. The image processing apparatus 112 according to the present embodiment first stores an input image input from an external apparatus via the image input unit 100 in the first storage unit 105. The image processing apparatus 112 uses the block data processing unit 110 to perform a geometric deformation process for geometrically deforming the shape of the input image to generate a deformed image. The deformation instruction indicating the deformation content is performed by the user using the user operation input unit 102. Hereinafter, the operation of the image processing apparatus 112 will be described in more detail.

  As described above, the input image data is captured into the image processing apparatus 112 via the image input unit 100, and the memory write unit 101 stores the captured input image data in the first storage unit 105.

  The first storage unit 105 is generally composed of a dynamic RAM (DRAM). In the present embodiment, the first storage unit 105 will be described as a DRAM. This type of memory may be used as the first storage unit 105. The DRAM is a memory having a relatively long access latency. The memory write unit 101 is generally called a DMA controller (DMAC). The memory write unit 101 stores input image data for each pixel block including a plurality of pixels in the first storage unit 105.

  Each pixel block is attached with information indicating the position of the pixel block on the input image. This information is not attached to each pixel block, but is collected as one header information. You may store in the one memory | storage part 105. FIG.

  The user operation input unit 102 is an instruction input device typified by a keyboard and a mouse, and any input device can be used as long as it can input an instruction (deformation instruction) indicating how the input image is to be geometrically deformed. May be used as the user operation input unit 102.

  Here, performing geometric deformation of the image is equivalent to mapping a pixel position on the image to another pixel position. For example, performing geometric deformation that rotates an image by θ means that a rotation matrix that rotates by θ is multiplied by each pixel position on the image and each pixel position is mapped to another pixel position. . The same applies to other geometric deformations such as shifting or enlarging the image in an arbitrary direction. However, this deformation instruction includes information representing a mapping matrix M satisfying Q = M · P, where P is the input image and Q is the deformation image. The deformation instruction input via the user operation input unit 102 is input to the coordinate conversion unit 103.

The coordinate conversion unit 103 obtains a mapping matrix (M ⁻¹ ) for converting a pixel position on the modified image into a pixel position on the input image using the mapping matrix M included in the modification instruction. That is, if the pixel position S (input system coordinates) on the input image is mapped to the pixel position T (output system coordinates) on the deformed image using the mapping matrix M, the pixel position S is changed from the pixel position T to the pixel position S. The mapping matrix for obtaining is obtained.

  The coordinate conversion unit 103 performs an operation for obtaining such a mapping matrix every time a deformation instruction is input from the user operation input unit 102. That is, the coordinate conversion unit 103 does not always operate, and if there is an input from the user operation input unit 102, it operates only once for this input. Of course, the coordinate conversion unit 103 may operate only when there is a difference of a predetermined amount or more between the deformation instruction input last time and the deformation instruction input this time.

  Further, the coordinate conversion unit 103 does not have to be a mapping matrix as long as it is information (or information indicating the relationship between the pixel positions) for converting the pixel position on the deformed image into the pixel position on the input image. You may ask for other information.

  The access sequence determination unit 104 defines the readout order (access order) of pixel blocks when the memory read unit 106 reads out the input image stored in the first storage unit 105 for each pixel block composed of a plurality of pixels. An access sequence list to be generated is generated. The access sequence determination unit 104 stores the generated access sequence list in the first storage unit 105.

  This access sequence list will be described with reference to FIG. The access sequence list 790 includes a storage address 700 of a pixel block i (i = 1, 2,..., N: N is the total number of pixel blocks) in the first storage unit 105, and a reference count indicating the reference count of the pixel block i. A set of information 701 is stored for each pixel block. In this set, a set for a pixel block referred to earlier is positioned higher. For example, the storage address 702 in the set stored in the memory address (BASE + (OFFSET * 2)) in the first storage unit 105 is the storage address in the first storage unit 105 of the third reference pixel block. Show. The reference count information 703 in the set stored in the memory address (BASE + (OFFSET * 2)) in the first storage unit 105 indicates the reference count of the third pixel block to be referred to.

  Next, the access sequence list will be described in more detail with reference to FIG. FIG. 2 shows a case where a deformed image 201 obtained by rotating the input image 200 is created. As shown in FIG. 2A, the deformed image 201 is generated in the scanning order (output scanning order) from the uppermost line to the lowermost line of one rectangular screen 290 including the deformed image 201. Of course, it is necessary to refer to the data of the pixel block stored in the first storage unit 105 in order to generate the pixel block in the modified image 201. However, the pixel block closer to the uppermost line is referred to. For example, the pixel block 204 of interest in the input image 200 is mapped to a pixel block marked with “3” on the deformed image 201, but this pixel block is the third closest to the top line, so this pixel block is This is the third reference pixel block.

  However, the access sequence determination unit 104 specifies the position of each pixel block on the input image from the information attached to each pixel block stored in the first storage unit 105. Of course, when the position of the pixel block is managed by another management method, this position is acquired by another method. Then, the access sequence determination unit 104 obtains a mapping position in which the specified position is mapped by a deformation instruction received from the coordinate conversion unit 103. Then, the pixel block for which the mapping position closer to the uppermost line is determined is specified as a further reference order. Thereby, the arrangement order of each set shown in FIG. 7 is determined.

  Next, with reference to FIG. 2B, a method for determining the reference number information of each pixel block will be described taking the pixel block (post-mapping pixel block) to which “3” is attached as an example. That is, the following description taking the post-mapping pixel block as an example applies to other pixel blocks as well.

  In this embodiment, in principle, when a rectangular area of 2 pixels × 2 pixels is moved in the output scanning order for each pixel in the rectangular screen 290 and the rectangular area is at the position X, the pixel value at this position X is changed. The pixel value in the pixel block having a portion overlapping this rectangular area is obtained. Thereby, the deformed image 201 is generated. In the example of FIG. 2B, when the rectangular area has a portion that overlaps the post-mapping pixel block, in order to obtain the pixel value at the position of the rectangular area, the target pixel block 204 that is the mapping source of the post-mapping pixel block is determined. Need to refer. That is, the number of times to refer to the pixel block of interest 204 corresponds to the number of times the post-mapping pixel block and the rectangular area overlap. As shown in FIG. 2B, it can be seen that this rectangular area overlaps the post-mapping pixel block 15 times. In this case, the reference count for the pixel block of interest 204 is “15”. As described above, the access sequence determination unit 104 obtains reference count information for each pixel block. As a result, each set shown in FIG. 7 is confirmed.

  The access sequence determination unit 104 generates such an access sequence list every time a transformation instruction is input from the coordinate conversion unit 103. That is, the access sequence determination unit 104 does not always operate, and if there is an input from the coordinate conversion unit 103, it operates only once for this input.

  Then, the access sequence determination unit 104 stores the access sequence list generated in this way in the first storage unit 105. Details of the processing performed by the access sequence determination unit 104 will be described later.

  The memory read unit 106 first reads the access sequence list stored in the first storage unit 105. Then, the memory read unit 106 refers to the set group registered in the read access sequence list from above, and reads out the pixel block stored at the storage address in the referenced set from the first storage unit 105. Then, the memory read unit 106 sends the reference count information in the referenced set and the pixel block stored at the storage address in the set to the block data management unit 107. Details of processing performed by the memory read unit 106 will be described later.

  The block data management unit 107 stores the pixel block and the reference count information received from the memory read unit 106 in the second storage unit 108 as a set. In the present embodiment, the second storage unit 108 will be described as a static RAM (SRAM). This SRAM is a memory having a relatively short access latency. However, any other type of memory may be used as the second storage unit 108 as long as it is a readable / writable memory.

  Further, the block data management unit 107 reads out the pixel block requested from the block data processing unit 110 from the second storage unit 108 and supplies it to the block data processing unit 110. At this time, the block data management unit 107 updates the reference number information by subtracting one reference number indicated by the reference number information stored in the second storage unit 108 as a set with the supplied pixel block. The block data management unit 107 stores the reference count information and the reference count information as a set in the second storage unit 108 when the reference count indicated by the updated reference count information becomes zero. The pixel block is deleted from the second storage unit 108.

  The block data processing unit 110 generates a deformed image using the pixel block received from the block data management unit 107 in accordance with the deformation instruction by exchanging with the coordinate conversion unit 103.

  More specifically, the block data processing unit 110 moves a rectangular area (reference area) having a size of 2 pixels × 2 pixels in the output scanning order within a rectangular area (a rectangular area 290 in the case of FIG. 2) that includes the deformed image. . Then, a pixel block having a portion that overlaps the reference region is specified among the pixel blocks in the deformed image, and the coordinates of the pixel position of each pixel constituting the portion that overlaps the reference region in the specified pixel block are coordinated. The mapping matrix obtained by the conversion unit 103 is multiplied. Thereby, the corresponding pixel position on the input image can be obtained. Further, the block data processing unit 110 requests the block data management unit 107 for the data of the specified pixel block. In response to this supply, in the pixel block received from the block data management unit 107, the pixel value at the position of the reference region is obtained using the pixel value of the pixel at the obtained pixel position. By such processing, it is possible to generate a deformed image in which the pixel value of each pixel is fixed.

  In other words, the described processing is equivalent to the following processing. That is, first, a post-mapping area in the input image, which is a mapping destination in which the pixel block area in the input image is mapped in accordance with the deformation indicated by the deformation instruction, is obtained by calculation. Here, when a rectangular area of a prescribed size (for example, 2 pixels × 2 pixels) is provided at each pixel position in the input image, a post-target mapping area that is a mapping destination of the target pixel block area in the input image; Let X be the position in the input image of each rectangular region P having overlapping portions. In this case, the pixel value at the position X on the deformed image (on the rectangular area 290) is calculated using the pixel value of the pixel in the pixel block that is the mapping source of the post-mapping area having a portion overlapping the rectangular area P.

  Note that the block data processing unit 110 determines the pixel value of each pixel of the deformed image regardless of the above-described calculation, and then performs pixel value interpolation processing or filter processing on the deformed image. Image processing such as these may be applied as appropriate.

  Then, the block data processing unit 110 sends the generated deformed image to the display unit 111. The display unit 111 includes a CRT, a liquid crystal screen, and the like, and displays an image based on the deformed image data (output image data) received from the block data processing unit 110.

  Next, processing performed by the access sequence determination unit 104 will be described with reference to FIG. 3 showing a flowchart of the processing. The access sequence determination unit 104 stands by in step S301 unless it receives a deformation instruction from the coordinate conversion unit 103. If this deformation instruction is received, the process proceeds from step S301 to step S302.

  In step S302, the access sequence determination unit 104 initializes a reference block order counter, which is a variable used for determining the reference order of each pixel block, to 1. Further, the access sequence determination unit 104 initializes a variable indicating the reference order and a variable indicating the number of references, which are variables provided for each pixel block, to zero.

  Then, the access sequence determination unit 104 performs the processing from step S304 to step S310 for each pixel position in the rectangular area (rectangular area 290 in the case of FIG. 2) including the deformed image. Although not shown in the flowchart of FIG. 3, a predetermined pixel value such as 0 is given to an area outside the deformed image within this rectangular area. In the following, processing for a pixel position i (i = 1,..., M: M is the total number of pixels in the rectangular area) in the rectangular area will be described.

  In step S304, the pixel position i is converted by the mapping matrix obtained by the coordinate conversion unit 103 to obtain the converted pixel position i. In step S305, the access sequence determination unit 104 determines whether the converted pixel position i is a pixel position on the input image. As a result of this determination, if the converted pixel position i is a pixel position on the input image, the process proceeds to step S306. If the converted pixel position i is not a pixel position on the input image, the process returns to step S302. The subsequent processing is performed for the next pixel position (i + 1).

  In step S306, the access sequence determination unit 104 sets a reference area at the pixel position i in the rectangular area including the modified image, and identifies a pixel block having a portion overlapping with the reference area among the pixel blocks in the modified image. To do. Each pixel block in the deformed image corresponds to a mapping destination region in which the area of the pixel block in the input image is mapped in accordance with the deformation indicated by the deformation instruction.

  In step S307, the access sequence determination unit 104 determines whether or not the variable indicating the reference count for the pixel block identified in step S306 is zero. If the result of this determination is 0, the process proceeds to step S308, and if it is not 0, the process proceeds to step S310.

  In step S308, the access sequence determination unit 104 sets the value of the current reference block order counter as a variable indicating the reference order for the pixel block specified in step S306.

  In step S309, the access sequence determination unit 104 increments the value of the reference block order counter by one and updates the reference block order counter. In step S310, the access sequence determination unit 104 updates the variable by incrementing the value of the variable indicating the reference count by one.

  By performing the processes in steps S304 to S310 for each pixel position in the rectangular area including the deformed image, reference order information and reference number information can be obtained for each pixel block. However, in step S312, the access sequence determination unit 104 creates an access sequence list in which a set of storage addresses and reference frequency information for each pixel block is arranged in the reference order, and stores the created access sequence list in the first storage unit 105. To do.

  The process of creating an access sequence list by the above process will be described with reference to FIG. First, as shown in a list 400, each pixel block is assigned identification information (block ID) 403 that is assigned when the pixel block is stored, and is also assigned reference order information 404 and reference count information 405. . Both the reference order information information 404 and the reference count information 405 are initially initialized as described above.

  By performing the above processing, as shown in the list 401, the reference order set in step S308 for each pixel block is fixed. In the list 401, information for each pixel block is sorted in the reference order.

  Then, the address of the set of the block ID, reference order information, and reference count information information registered at the top of the list 401 is determined as (BASE + (OFFSET * 0)). In this embodiment, when the base address of the list is BASE and the space between the head addresses of each set is OFFSET, the address of the set registered in the order from the head of the list is obtained by BASE + (OFFSET * order). Furthermore, the storage address in the first storage unit 105 of each pixel block is specified. As a result, as shown in the list 402, the address 406 of each set in the list 401 and the storage address 407 of the pixel block are created. Finally, the list 408 remaining after deleting the block ID 403 and the reference order information 404 which are unnecessary data is set as an access sequence list as shown in FIG. In FIG. 7, the address 406 is not included in the access sequence list, but may be included.

  Next, processing performed by the memory read unit 106 will be described with reference to FIG. 5 showing a flowchart of the processing. In step S <b> 501, the memory read unit 106 sets a base address (BASE) that is a head address of the access sequence list as an access address to the first storage unit 105. Then, the memory read unit 106 performs each process between steps S502 to S508 for all sets registered in the access sequence list.

  In step S503, the memory read unit 106 accesses the currently set access address (initially the access address set in step S501) and stores the set (set of storage address and reference count information). Is read.

  In step S504, the memory read unit 106 accesses the storage address read in step S503, and reads the pixel block stored therein. If there is no request from the block data management unit 107, the process waits in step S505. If there is a request, the process proceeds to step S506 via step S505.

  In step S506, the memory read unit 106 sends the pixel block read in step S504 and the reference count information in the set read in step S503 to the block data management unit 107. In step S507, the memory read unit 106 adds the offset address (OFFSET) to the current access address and updates the access address.

  Next, processing performed by the block data management unit 107 will be described with reference to FIG. 6 showing a flowchart of the processing. In step S602, the block data management unit 107 determines whether there is sufficient free space in the second storage unit 108. As a result of this determination, if it is determined that there is sufficient free space, the process proceeds to step S603, and if it is determined that there is no free space, the process proceeds to step S604.

  In step S <b> 603, the block data management unit 107 stores the pixel block received from the memory read unit 106 and the reference count information in the second storage unit 108 as a set. In step S604, the block data management unit 107 determines whether there is a pixel block transfer request from the block data processing unit 110. If it is determined that there is a transfer request, the process proceeds to step S605. If there is no transfer request, the process returns to step S602.

  In step S <b> 605, the block data management unit 107 determines whether or not the requested pixel block is stored in the second storage unit 108. As a result of this determination, if it is stored, the process proceeds to step S606. If it is not stored, the process returns to step S602.

  In step S <b> 606, the block data management unit 107 reads out the pixel block requested by this transfer request from the second storage unit 108 and supplies it to the block data processing unit 110.

  In step S607, the block data management unit 107 updates the reference number information by decrementing the reference number indicated by the reference number information stored in the second storage unit 108 as a set with the supplied pixel block. In step S608, it is determined whether or not the reduced number of references is zero. If the result of this determination is 0, the process proceeds to step S609, and if not 0 (if greater than 0), the process returns to step S602.

  In step S609, the block data management unit 107 deletes the reference count information indicating the reference count 0 and the pixel block stored in the second storage unit 108 as a set together with the reference count information from the second storage unit 108, and stores the second memory The storage area for these pieces of information in the unit 108 is released. Thus, a new pixel block can be acquired.

  According to the following configuration, the block data management unit 107 can supply the pixel blocks in the order requested by the block data processing unit 110. Further, by using the reference count, it is ensured that the corresponding pixel block is held as long as the block data processing unit 110 needs, so that the processing does not fail.

  As described above, according to the present embodiment, any image deformation process can be performed without having a prefetch mechanism that occupies a relatively large proportion when performing the image deformation process. As a result, the circuit scale of the image processing apparatus (the scale of the software when the above processing is implemented by software) can be reduced.

  In the above description, every time the pixel value on the modified image is obtained by referring to the pixel block, the reference count set for this pixel block is counted down. However, a new variable for counting up may be provided for the pixel block, and the value of this variable may be counted up each time this pixel block is used for generating a pixel value. In this case, when the value of the variable after counting up reaches the upper limit number set for the pixel block, the pixel block is deleted from the first storage unit 105.

  Further, in the present embodiment, the processing using an image has been described as an example. However, the above description is not limited to an example in which an image is handled, and can also be applied when data other than an image is handled.

[Second Embodiment]
In the first embodiment, the respective units illustrated in FIG. 1 have been described as being configured by hardware. However, some or all of them may be configured as a computer program. In this case, the computer program is installed in a device such as a PC (personal computer) and executed by a CPU or the like included in the device, whereby the device executes each process described in the first embodiment. Can do.

  One or more of the units shown in FIG. 1 may be separate devices. In this case, each process described in the first embodiment is performed while performing data communication between the apparatuses via a wired or wireless network.

[Other Examples]
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (12)

Storage means for storing the input image;
Obtaining means for obtaining an instruction for deforming the input image;
Whether or not it is necessary to refer to the image data of the input image in order to generate a display screen including a deformed image according to the instruction is determined for each of a plurality of regions constituting the display screen. Thus, determination means for determining the number of times that the reference of the image data of the input image is necessary for the generation of the display screen for each of the plurality of regions constituting the input image,
When the number of times the image data of one area constituting the input image is referred to generate the display screen reaches the number determined by the determining means, the image data of the one area is stored. An image processing apparatus comprising: control means for controlling the area of the storage means to be overwritable .   The image processing apparatus according to claim 1, wherein the instruction is an instruction to rotate the input image. The determination means further determines a reference order of image data of the input image for generating the display screen,
The control means controls the timing of moving image data from the storage means of the image processing apparatus to the storage means of the image processing apparatus whose reading speed is slower than that of the storage means based on the reference order determined by the determination means. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. The determination unit performs the determination as to whether or not reference to image data of the input image is necessary using a mapping matrix for generating the display screen from the input image. The image processing apparatus according to any one of 1 to 3. The determination means determines, for each pixel block corresponding to the display screen, whether or not it is necessary to refer to the image data of the input image according to the scanning order of the display screen. The image processing apparatus according to claim 3, wherein the data reference order is determined. The image processing apparatus according to claim 1, wherein the display screen is rectangular. The control means deletes the image data of the one area from the storage means when the number of times the image data of the one area is referred reaches the number of times determined by the determination means. The image processing apparatus according to any one of claims 1 to 6. An image processing method performed by an image processing apparatus having storage means for storing an input image,
An acquisition step of acquiring an instruction for deforming the input image;
Whether or not it is necessary to refer to the image data of the input image in order to generate a display screen including a deformed image according to the instruction is determined for each of a plurality of regions constituting the display screen. Thus, a determination step of determining the number of times that the reference of the image data of the input image is necessary for the generation of the display screen for each of the plurality of regions constituting the input image;
When the number of times the image data of one area constituting the input image is referred to generate the display screen reaches the number determined in the determination step, the image data of the one area is stored. A control step of controlling so that the area of the storage means can be overwritten;
Image processing method, characterized in that it comprises a. In the determining step, further determining the reference order of the image data of the input image for generating the display screen,
In the control step, based on the reference order determined in the determination step, the timing for moving image data from the storage unit of the image processing apparatus to the storage unit, which is slower in reading speed than the storage unit, is controlled. The image processing method according to claim 8, wherein: The determination step is performed by using the mapping matrix for generating the display screen from the input image to determine whether or not the image data of the input image needs to be referred to. The image processing method according to 8 or 9. In the determination step, for each pixel block corresponding to the display screen, it is determined according to the scanning order of the display screen whether or not it is necessary to refer to the image data of the input image. The image processing method according to claim 9, wherein a reference order of data is determined. A computer program for causing a computer to function as each unit of the image processing apparatus according to any one of claims 1 to 7 .

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