JP5675464B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit equipped with a nonvolatile memory. In particular, the present invention relates to a semiconductor integrated circuit including an external terminal used for a characteristic test of a nonvolatile memory.

  Nonvolatile memories that are electrically erasable / programmable, such as flash memories and EEPROMs (Electrically Erasable Programmable ROMs), are known. Such a non-volatile memory requires a high voltage for data writing (including both erasing / programming). Such a high voltage used at the time of data writing is hereinafter referred to as “write voltage”.

  A semiconductor integrated circuit equipped with a nonvolatile memory such as a flash built-in microcomputer is generally used. For such a semiconductor integrated circuit, it may be required to supply a write voltage from the outside to the nonvolatile memory. In that case, a write voltage is supplied through an external terminal (external pad) provided in the semiconductor integrated circuit. Generally, an electrostatic discharge (ESD) protection circuit is connected to an external terminal of a semiconductor integrated circuit. In the case of an external terminal to which a write voltage is supplied, the write voltage is a high voltage, and thus a device is required for the ESD protection circuit.

  FIG. 1 shows a circuit configuration described in Patent Document 1 (Japanese Patent Laid-Open No. 2009-231650). In FIG. 1, a write voltage application terminal 101 is an external terminal used for supplying a write voltage to the nonvolatile memory 103. The ESD protection circuit connected to the write voltage application terminal 101 includes a first diode 107, a P-channel transistor 109, and a second diode 113. The first diode 107 and the P-channel transistor 109 are connected in series between the power supply voltage (Vcc) line 105 and the write voltage application terminal 101. The second diode 113 is connected between the ground (Gnd) line 111 and the write voltage application terminal 101.

  P channel MOS transistor 109 is formed in an N well diffusion region formed on a P type substrate. The N well diffusion region is floating. In this case, the potential of the N well diffusion region is automatically controlled to be always at the highest level by the PN junction between the source or drain of the P channel MOS transistor 109 and the N well diffusion region. A level shifter 401 is connected to the gate of the P-channel MOS transistor 109. This level shifter 401 controls the gate voltage of the P channel MOS transistor 109.

  At the time of data writing, a write voltage higher than the power supply voltage Vcc is applied to the write voltage application terminal 101. At this time, if the P-channel MOS transistor 109 is ON, a current flows from the write voltage application terminal 101 to the power supply voltage line 105 through the first diode 107. In this case, the supply of the write voltage to the nonvolatile memory 103 becomes insufficient and a write error occurs. Therefore, it is necessary to turn off the P-channel MOS transistor 109 when writing data. Therefore, at the time of data writing, the level shifter 401 uses the write voltage applied to the write voltage application terminal 101 as a power supply voltage, and raises the gate voltage level of the P-channel MOS transistor 109 to the write voltage level. As a result, the P channel MOS transistor 109 is turned off.

JP 2009-231650 A

  In the case of the circuit configuration shown in FIG. 1, the P-channel transistor 109 is turned OFF when the write voltage is applied to the write voltage application terminal 101. Therefore, during application of the write voltage, a current path is not formed from the voltage application terminal 101 through the diode 107 and the P-channel transistor 109 to the power supply voltage line 105, that is, the first diode 107 as an ESD protection element is not formed. It cannot be used. Therefore, when an unintended surge voltage higher than the write voltage is applied to the write voltage application terminal 101 during application of the write voltage, the surge voltage is transmitted to the nonvolatile memory 103. This causes problems such as element destruction in the nonvolatile memory 103, characteristic fluctuations, and destruction of data held in the memory cells.

  In one aspect of the present invention, a semiconductor integrated circuit includes: a nonvolatile memory; a write control line to which a write voltage is applied when writing data to the nonvolatile memory; a first node connected to the write control line; ON / OFF control of an external terminal connected to the first node via one switch circuit, a first ESD protection circuit connected to the external terminal without going through the switch circuit, and the first switch circuit according to the operation mode A control circuit. The operation mode includes a test mode in which a characteristic test of the nonvolatile memory is performed using an external terminal, and a user mode in which no external terminal is used. In the test mode, the control circuit turns on the first switch circuit. In the user mode, the control circuit turns off the first switch circuit.

  In another aspect of the present invention, a semiconductor integrated circuit includes: a nonvolatile memory; a write control line to which a write voltage is applied when writing data to the nonvolatile memory; a first node connected to the write control line; An external terminal connected to the first node through one switch circuit, a first ESD protection circuit connected to the external terminal without going through the switch circuit, and a first node connected to the first node through the second switch circuit 2 ESD protection circuit. Each of the first switch circuit and the second switch circuit is configured to be turned on when a surge is applied to the external terminal before the power is turned on.

  According to the present invention, it is possible to perform a characteristic test of a nonvolatile memory through an external terminal in a semiconductor integrated circuit equipped with the nonvolatile memory. Furthermore, even when a surge voltage is applied to the external terminal, it is possible to prevent the surge voltage from being transmitted to the nonvolatile memory.

FIG. 1 shows a circuit configuration described in Patent Document 1. FIG. 2 is a block diagram schematically showing the configuration of the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of each switch circuit included in the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 4 schematically shows the structure of a nonvolatile memory cell included in the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 5 schematically shows a control method of each switch circuit included in the semiconductor integrated circuit according to the embodiment of the present invention. FIG. 6 is a timing chart showing an operation example of the semiconductor integrated circuit according to the embodiment of the present invention.

  Embodiments of the present invention will be described with reference to the accompanying drawings.

1. Configuration FIG. 2 is a block diagram schematically showing a configuration of a semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit according to the present embodiment is an IC chip A02 including an external pad A01, a nonvolatile memory A03, a control circuit A05, and a first ESD protection circuit A07.

  The external pad A01 is an external terminal of the IC chip A02. The external pad A01 is used for a characteristic test of the nonvolatile memory A03. For example, a write voltage is supplied from the outside to the nonvolatile memory A03 through the external pad A01.

  The first ESD circuit A07 is provided to protect the internal circuit from a surge voltage applied to the external pad A01. The limit voltage of the first ESD circuit A07 is equal to or higher than the write voltage. It should be noted that the first ESD circuit A07 is connected to the external pad A01 without going through the switch circuit.

  The nonvolatile memory A03 includes an internal booster circuit A04, a memory cell array A06, a second ESD protection circuit A08, and a plurality of switch circuits (SW1, SW2, SW3).

  The internal booster circuit A04 generates a write voltage used for data writing (including both erasing / programming) to the nonvolatile memory A03. The output terminal of the internal booster circuit A04 is connected to the node X (first node), and the output voltage of the internal booster circuit A04 is output to the node X.

  The memory cell array A06 includes a plurality of memory cells MEM arranged in an array. In FIG. 2, two memory cells MEM0 and MEM1 are shown as an example. Each memory cell MEM is a nonvolatile memory cell transistor including a floating gate C04 and a control gate C05. The control gate C05, the source, and the drain of the memory cell MEM0 are connected to the word line WL0, the source line SL0, and the bit line BL0, respectively. The control gate C05, the source, and the drain of the memory cell MEM1 are connected to the word line WL1, the source line SL0, and the bit line BL0, respectively. Note that a write voltage at the time of data writing is supplied to the memory cell MEM through the source line SL0. That is, the source line SL0 is a write control line to which a write voltage is applied during data writing.

  The node X (first node) is connected to the node Y (second node) via the switch circuit SW2. The switch circuit SW2 turns on / off the electrical connection between the node X and the node Y. ON / OFF control of the switch circuit SW2 is performed by a switch control signal SWC2 output from the control circuit A05. The node Y is connected to the external pad A01 and the first ESD protection circuit A07 described above.

  The node X (first node) is connected to the node Z (third node) via the switch circuit SW1. The switch circuit SW1 turns on / off the electrical connection between the node X and the node Z. ON / OFF control of the switch circuit SW1 is performed by a switch control signal SWC1 output from the control circuit A05. The node Z is connected to the second ESD protection circuit A08.

  Note that the second ESD protection circuit A08 is provided separately from the first ESD protection circuit A07 described above. The limit voltage of the second ESD protection circuit A8 is lower than the limit voltage of the first ESD protection circuit A07. For example, the limit voltage of the first ESD protection circuit A07 is set to a level (example: 13V) slightly higher than the write voltage (example: 12V), and the limit voltage of the second ESD protection circuit A08 is higher than the write voltage (example: 12V). It is set to a level (eg, 4V) that is low and slightly higher than the power supply voltage (eg: 3V). Even when a voltage about the limit voltage of the second ESD protection circuit A08 is applied to the source line SL0, element destruction, characteristic fluctuation, and destruction of retained data do not occur with respect to the memory cell MEM.

  Further, the node X (first node) is connected to the source line SL0 (write control line) via the switch circuit SW3. The switch circuit SW3 turns on / off the electrical connection between the node X and the write control line. ON / OFF control of the switch circuit SW3 is performed by a switch control signal SWC3 output from the control circuit A05.

  The control circuit A05 outputs the switch control signals SWC1, SWC2, and SWC3 to the switch circuits SW1, SW2, and SW3, thereby controlling each of the switch circuits SW1, SW2, and SW3 on / off. Which switch circuit SW is turned on differs depending on the operation mode of the semiconductor integrated circuit. That is, the control circuit A05 performs ON / OFF control of each of the switch circuits SW1, SW2, and SW3 according to the operation mode of the semiconductor integrated circuit. Each operation mode will be described later.

  FIG. 3 is a circuit diagram showing a configuration example of each switch circuit SWn (n = 1, 2, 3). The switch circuit SWn includes an input terminal IN, an output terminal OUT, a level shifter LSn, a P-channel MOS transistor TSn, and inverters B05 and B06.

  The level shifter LSn includes P-channel MOS transistors B01 and B02 and N-channel MOS transistors B03 and B04. The gate, source, and drain of the P-channel MOS transistor B01 are connected to the node Gn, the input terminal IN, and the gate of the P-channel MOS transistor B02, respectively. The gate, source, and drain of the P-channel MOS transistor B02 are connected to the drain, input terminal IN, and node Gn of the P-channel MOS transistor B01, respectively. The source and drain of the N channel MOS transistor B03 are connected to the ground line and the drain of the P channel MOS transistor B01, respectively. The source and drain of the N-channel MOS transistor B04 are connected to the ground line and the node Gn, respectively.

  Node Gn is the output of level shifter LSn and is connected to the gate of P-channel MOS transistor TSn. The source (drain) of the P-channel MOS transistor TSn is connected to the input terminal IN, and the drain (source) is connected to the output terminal OUT.

  The switch control signal SWCn is input to the input terminal of the inverter B05. The output terminal of the inverter B05 is connected to the gate of the N-channel MOS transistor B03 and the input terminal of the inverter B06. The output terminal of the inverter B06 is connected to the gate of the N channel MOS transistor B04.

  Note that the input terminal IN of the switch circuit SW1 is connected to the node X, and its output terminal OUT is connected to the second ESD protection circuit A08. The input terminal IN of the switch circuit SW2 is connected to the node Y, and its output terminal OUT is connected to the node X. The input terminal IN of the switch circuit SW3 is connected to the node X, and its output terminal OUT is connected to the source line SL0.

  FIG. 4 schematically shows the structure of the memory cell MEM of the nonvolatile memory A03. The memory cell MEM includes N-type diffusion layers C01 and C02 as a source / drain, a substrate C03, a floating gate C04, and a control gate C05. The N-type diffusion layer C01 is connected to the bit line BLm, the N-type diffusion layer C02 is connected to the source line SLm, and the control gate C05 is connected to the word line WLm (m is a natural number).

  The data program for the memory cell MEM is performed by, for example, the CHE method. Specifically, a ground voltage is applied to the N-type diffusion layer C01 (source), a high voltage (write voltage) is applied to the N-type diffusion layer C02 (drain), and a high voltage is applied to the control gate C05. As a result, the memory cell MEM is turned on. Channel hot electrons are generated by a high electric field in the vicinity of the drain, and some of the channel hot electrons are injected into the floating gate C04 through the gate insulating film. As a result, the threshold voltage of the memory cell MEM decreases. This is the program state.

  On the other hand, data erasure with respect to the memory cell MEM is performed by, for example, the FN tunneling method. Specifically, the N-type diffusion layer C01 is set in an open state, a high voltage (write voltage) is applied to the N-type diffusion layer C02, and a ground voltage is applied to the control gate C05. As a result, a strong electric field is generated between the control gate C05 and the N-type diffusion layer C02. Then, electrons in the floating gate C04 are extracted to the N-type diffusion layer C02 by FN tunneling due to the strong electric field. As a result, the threshold voltage of the memory cell MEM increases. This is the erased state.

2. Operation FIG. 5 schematically shows a method of controlling the switch circuits SW1, SW2, and SW3 in the present embodiment. Hereinafter, as an example, the power supply voltage is 3V, the write voltage is 12V, the limit voltage of the first ESD protection circuit A07 is 13V that is slightly higher than the write voltage (12V), and the limit voltage of the second ESD protection circuit A08 is lower than the write voltage (12V). Consider the case of 4V, which is slightly higher than the power supply voltage (3V).

2-1. User Mode In the user mode, the external pad A01 is not used, and data write (program / erase) is performed by using the write voltage generated by the internal booster circuit A04. The IC chip A02 has a power supply. The internal booster circuit A04 operates and outputs a write voltage to the node X (first node). The control circuit A05 sets the switch control signals SWC1, SWC2, and SWC3 to “Low”, “Low”, and “High”, respectively. As a result, the switch circuit SW1 is turned off, the switch circuit SW2 is turned off, and the switch circuit SW3 is turned on.

  Since the switch circuit SW3 is turned on, the node X is electrically connected to the source line SL0 (write control line). Further, since the switch circuits SW1 and SW2 are turned off, the node X is electrically disconnected from the first ESD protection circuit A07 and the second ESD protection circuit A08. Therefore, the write voltage generated by the internal booster circuit A04 is normally supplied to the selected memory cell MEM through the write control line without being affected by the ESD protection circuit.

  Further, consider a case where a surge voltage is applied to the external pad A01 in the user mode. When the voltage of the external pad A01 becomes equal to or higher than the limit voltage (13V) of the first ESD protection circuit A07, the first ESD protection circuit A07 operates to pass a current. As a result, the surge voltage is prevented from being transmitted to the nonvolatile memory A03, and element destruction and characteristic fluctuation in the nonvolatile memory A03 are prevented.

2-2. Test Mode In the test mode, the characteristic test of the nonvolatile memory A03 is performed by using the external pad A01. Specifically, the test mode includes the following first test mode and second test mode.

(First test mode)
In the first test mode, the output voltage of the internal booster circuit A04 is monitored through the external pad A01. The IC chip A02 has a power supply. The internal booster circuit A04 operates and outputs the generated voltage to the node X (first node). The control circuit A05 sets the switch control signals SWC1, SWC2, and SWC3 to “Low”, “High”, and “Low”, respectively. As a result, the switch circuit SW1 is turned off, the switch circuit SW2 is turned on, and the switch circuit SW3 is turned off.

  Since the switch circuit SW3 is turned off, the node X is electrically disconnected from the write control line. Therefore, the voltage generated by the internal booster circuit A04 is not supplied to the write control line, and erroneous writing to the memory cell MEM is prevented. Further, since the switch circuit SW1 is turned off, the node X is electrically disconnected from the second ESD protection circuit A08. Therefore, the voltage generated by the internal booster circuit A04 is output from the external pad A01 without being affected by the second ESD protection circuit A08.

(Second test mode)
In the second test mode, a write voltage (a high voltage generated outside the IC chip A02) is supplied from the external pad A01 to the memory cell MEM through the write control line. The IC chip A02 has a power supply. The control circuit A05 sets the switch control signals SWC1, SWC2, and SWC3 to “Low”, “High”, and “High”, respectively. As a result, the switch circuit SW1 is turned off, the switch circuit SW2 is turned on, and the switch circuit SW3 is turned on.

  Since the switch circuits SW2 and SW3 are turned on, the write control line and the external pad A01 are electrically connected. Further, since the switch circuit SW1 is turned off, the node X is electrically disconnected from the second ESD protection circuit A08. Accordingly, the write voltage applied to the external pad A01 is normally supplied to the selected memory cell MEM through the write control line without being affected by the second ESD protection circuit A08.

  Consider a case where a surge voltage is applied to the external pad A01 in the first and second test modes. When the voltage of the external pad A01 becomes equal to or higher than the limit voltage (13V) of the first ESD protection circuit A07, the first ESD protection circuit A07 operates to pass a current. As a result, the surge voltage is prevented from being transmitted to the nonvolatile memory A03, and element destruction and characteristic fluctuation in the nonvolatile memory A03 are prevented.

2-3. Before Power On Next, a state where the power of the IC chip A02 is not turned on will be described. Before the power is turned on, the switch control signals SWC1, SW2, and SWC3 that are output signals of the control circuit A05 are all in the Hi-z state. In this state, when a surge voltage is applied to the external pad A01, the switch circuits SW1, SW2, and SW3 are turned on. With reference to the timing chart shown in FIG. 6, the mechanism by which each switch circuit is turned on and the operation of the ESD protection circuit will be described.

  Time t0 is immediately before the surge voltage is applied. The external pad A01, the nodes X, Y, and Z, the source line SL0, and the nodes G1 to G3 of the switch circuits SW1 to SW3 are in the Hi-z state, and their voltage levels are close to 0V.

  When a surge is applied to the external pad A01, the voltage level of the external pad A01 begins to rise. Following this, the voltage level of the node Y also rises with time. On the other hand, since the switch control signal SCW2 is in the Hi-z state, the voltage level of the node G2 of the switch circuit SW2 is kept near 0V. That is, the gate voltage of the P-channel MOS transistor TS2 of the switch circuit SW2 is lower than the voltage of the input terminal IN. Therefore, the P-channel MOS transistor TS2 is turned on as time passes. Accordingly, following the increase in the voltage level of the node Y, the voltage level of the node X also increases with the passage of time.

  The same applies to the switch circuits SW1 and SW3. Since the switch control signals SCW1 and SCW3 are in the Hi-z state, the voltage levels of the nodes G1 and G3 of the switch circuits SW1 and SW3 are kept near 0V. Therefore, as the voltage level of node X increases, P channel MOS transistors TS1 and TS3 are turned on as time passes. As a result, the voltage level of the node Z and the source line SL0 also increases with time following the increase of the voltage level of the node X.

  The voltage level of the node Z once exceeds the limit voltage (4V) of the second ESD protection circuit A08. Then, the second ESD protection circuit A08 operates. At time t1, the voltage level at node Z begins to drop. Thereafter, the voltage level of the node Z is maintained near the limit voltage (4V) by the second ESD protection circuit A08. The voltage level of the node Z is transmitted to the node X through the switch circuit SW1. Further, the voltage level of the node X is transmitted to the node Y and the source line SL0 through the switch circuits SW2 and SW3, respectively. As a result, following the voltage level of the node Z, the voltage levels of the nodes X and Y and the source line SL0 are also maintained near the limit voltage (4V).

  At time t2, the voltage of the external pad A01 reaches the limit voltage (13V) of the first ESD protection circuit A07. Then, the first ESD protection circuit A07 operates. Even in this case, the voltage levels of the nodes X, Y, Z and the source line SL0 of the nonvolatile memory A03 are kept near the limit voltage (4 V) of the second ESD protection circuit A08. Accordingly, erroneous rewriting of data held in the memory cell MEM of the nonvolatile memory A03, that is, destruction of the held data is prevented.

  As described above, when a surge voltage is applied to the external pad A01 before the power is turned on, the switch circuit SW2 is turned on and the switch circuit SW1 is further turned on. As a result, not only the first ESD protection circuit A07 but also the second ESD protection circuit A08 operates. Thereby, the voltage level of each node in the nonvolatile memory A03 is kept near the limit voltage (4 V) of the second ESD protection circuit A08, which is lower than the write voltage. Accordingly, erroneous rewriting of data held in the memory cell MEM of the nonvolatile memory A03, that is, destruction of the held data is prevented.

  In the user mode and the test mode described above, since it is necessary to supply the write voltage to the memory cell MEM, the switch circuit SW1 is turned off and the second ESD protection circuit A08 is not used. On the other hand, before the power is turned on, the switch circuit SW1 is turned on and the second ESD protection circuit A08 is used in order to prevent destruction of data held in the memory cell MEM.

3. Effect As described above, according to the present embodiment, the characteristic test of the nonvolatile memory A03 can be performed through the external pad A01. Even when a surge voltage is applied to the external pad A01 during the characteristic test, the first ESD protection circuit A07 operates, so that the surge voltage is prevented from being transmitted to the nonvolatile memory A03. As a result, element destruction and characteristic variation in the nonvolatile memory A03 are prevented.

  Further, when a surge voltage is applied to the external pad A01 before the power is turned on, the switch circuit SW2 is turned on and the switch circuit SW1 is further turned on. As a result, not only the first ESD protection circuit A07 but also the second ESD protection circuit A08 operates. Thereby, the voltage level of each node in the nonvolatile memory A03 is kept near the limit voltage (4 V) of the second ESD protection circuit A08, which is lower than the write voltage. Accordingly, erroneous rewriting of data held in the memory cell MEM of the nonvolatile memory A03, that is, destruction of the held data is prevented.

  As described above, according to the present embodiment, it is possible to prevent element destruction, characteristic fluctuation, and destruction of retained data while realizing the characteristic test of the nonvolatile memory A03 through the external pad A01. It becomes.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed by those skilled in the art without departing from the scope of the invention.

A01 External pad A02 IC chip A03 Non-volatile memory A04 Internal booster circuit A05 Control circuit A06 Memory cell array A07 First ESD protection circuit A08 Second ESD protection circuit SWn, SW1, SW2, SW3 Switch circuit SWCn, SWC1, SWC2, SWC3 Switch control signal X , Y, Z node IN input terminal OUT output terminal TSn P channel MOS transistor MEM0, MEM1 Memory cell WL0, WL1, WLm Word line SL0, SLm Source line BL0, BLm bit line B01, B02 P channel MOS transistor B03, B04 N channel MOS transistor B05, B06 Inverter LSn Level shifter circuit C01 N-type diffusion layer C02 N-type diffusion layer C03 Substrate C04 Floating gate (FG
C05 Control gate (CG)

Claims (8)

Non-volatile memory;
A write control line to which a write voltage is applied when writing data to the nonvolatile memory;
A first node connected to the write control line;
An external terminal connected to the first node via a first switch circuit;
A first ESD protection circuit connected to the external terminal without going through a switch circuit;
A control circuit for controlling ON / OFF of the first switch circuit according to an operation mode,
The operation mode is:
A test mode for performing a characteristic test of the nonvolatile memory using the external terminal;
Including a user mode not using the external terminal,
In the test mode, the control circuit turns on the first switch circuit,
In the user mode, the control circuit turns off the first switch circuit ,
A second ESD protection circuit connected to the first node via a second switch circuit;
Each of the first switch circuit and the second switch circuit is a semiconductor integrated circuit configured to be turned on when a surge voltage is applied to the external terminal before power is turned on . The semiconductor integrated circuit according to claim 1,
The limit voltage of the first ESD protection circuit is greater than or equal to the write voltage. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1 , wherein
A limit voltage of the second ESD protection circuit is lower than the write voltage. Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 1 to 3 ,
In the test mode and the user mode, the control circuit turns off the second switch circuit. Semiconductor integrated circuit. A semiconductor integrated circuit according to any one of claims 1 to 4 ,
An internal booster circuit for generating the write voltage;
An output terminal of the internal booster circuit is connected to the first node;
The write control line is connected to the first node via a third switch circuit;
In the user mode, the internal booster circuit operates, the control circuit turns on the third switch circuit ,
The test mode includes a first test mode for monitoring the output voltage of the internal booster circuit through the external terminal,
In the first test mode, the internal booster circuit operates, and the control circuit turns off the third switch circuit. The semiconductor integrated circuit according to claim 5 ,
The test mode includes a second test mode for supplying the write voltage from the external terminal to the nonvolatile memory through the write control line,
In the second test mode, the control circuit turns on the third switch circuit. A semiconductor integrated circuit according to claim 5 or 6 ,
The third switch circuit is configured to turn on when a surge voltage is applied to the external terminal before power is turned on. Semiconductor integrated circuit. Non-volatile memory;
A write control line to which a write voltage is applied when writing data to the nonvolatile memory;
A first node connected to the write control line;
An external terminal connected to the first node via a first switch circuit;
A first ESD protection circuit connected to the external terminal without going through a switch circuit;
A second ESD protection circuit connected to the first node via a second switch circuit;
A control circuit for controlling ON / OFF of the first switch circuit and the second switch circuit according to an operation mode,
The limit voltage of the first ESD protection circuit is not less than the write voltage,
A limit voltage of the second ESD protection circuit is lower than the write voltage. Semiconductor integrated circuit.

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