JP5692038B2 - Pulse width modulation circuit - Google Patents

Description

  The present invention relates to a pulse width modulation circuit.

  A pulse width modulation circuit used in switching amplifiers, which converts the voltage of an input signal (for example, an audio signal) into a current, charges and discharges the capacitor with that current, and drives the comparator with the capacitor charging voltage. A modulation circuit has been proposed by the applicant. For example, Patent Document 1 describes a pulse width modulation circuit using an astable multivibrator, and Patent Document 2 describes a synchronous pulse width modulation circuit that charges and discharges a capacitor in synchronization with an external clock signal. ing.

  In general, when driving a speaker as a load with a switching amplifier, there is a large difference in radiated noise and efficiency depending on the switch timing and phase of the switch element as an output element. In the single-end push-pull (SEPP) type, which uses two switch elements in the output stage and alternately switches these to extract the output, the output waveform is a binary pulse of low level and high level, and the input signal The duty ratio when is 0 is 50%. In general, a low-pass filter is inserted between the switch element and the load for the purpose of removing the switching pulse component. In the SEPP method, however, the switching current component leaked from the low-pass filter is always loaded regardless of the input signal. The noise radiation is large. When the output may be small, the low-pass filter may be omitted, and the switching waveform flows to the load as it is, so that the noise becomes very large and the load at the load due to the switching operation itself is large. Power loss occurs and efficiency is very poor.

  The above problem can be solved by adopting an H-bridge configuration using four switch elements in the output stage. The switching amplifier of the H bridge configuration has a form in which a load is connected between the output terminals of the switching output stage of the SEPP configuration, and the load is driven by a difference between two SEPP outputs. Using this characteristic, both arms of the H-bridge are moved in phase when the input signal is 0, and when there is a signal input, one SEPP output stage of the H-bridge has a pulse width that changes in the positive direction with respect to the input. By driving the modulation waveform, the other SEPP output stage, with a pulse width modulation waveform that changes in the negative direction with respect to the input, a difference component corresponding to the input signal flows to the load. Therefore, when the input signal is 0, the switching current does not flow to the load side, so that noise radiation is reduced and efficiency is increased.

  When the above control is executed, it is necessary to synchronize the timing of the switches at each duty cycle. Therefore, it is necessary to input a clock signal as an operation timing reference from the outside. This technique is described in Patent Document 3, for example. Yes. This technique is effective as a countermeasure against the above-mentioned problems, but has a drawback that noise resistance is low because the basic method of pulse width modulation is based on comparison with a triangular wave. In addition, since a very narrow pulse is output depending on the size of the input signal, the high-speed response of the output switching element is required to perform an accurate switching operation in a region with a large modulation degree. There is.

JP2011-61399A JP2008-206128 JP-A-55-153406

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to prevent the occurrence of switching noise when the input signal is 0 and to output two pulse width modulation signals. It is an object of the present invention to provide a pulse width modulation circuit that synchronizes signals without using an external clock.

  A pulse width modulation circuit according to a preferred embodiment of the present invention includes a first charging current generation unit that generates a first charging current that is a sum of a predetermined bias current and a current that varies in proportion to an input signal, and the predetermined bias. A second charging current generation unit that generates a second charging current that is a difference between the current and a current that varies in proportion to the input signal, and a first capacitor, which are supplied from a monostable multivibrator for generating a clock signal In response to the inversion of the clock signal to the other level from the other level, the first capacitor starts to charge the first capacitor with the first charging current, and the charging voltage of the first capacitor reaches the threshold voltage. A first monostable multivibrator for stopping the charging operation of the first capacitor and outputting a first pulse signal in accordance with the charging operation of the first capacitor; In response to inversion of the clock signal supplied from the monostable multivibrator for generating a clock signal from the other level to the one level, the second charging current is used to charge the second capacitor. A second unit that stops the charging operation of the second capacitor when the charging voltage of the second capacitor reaches a threshold voltage and outputs a second pulse signal in accordance with the charging operation of the second capacitor. A stable multivibrator and a third capacitor, wherein the first pulse signal is supplied as a clock signal, and the second charging current is responsive to inversion of the first pulse signal from the one level to the other level. To start the charging operation of the third capacitor, and when the charging voltage of the third capacitor reaches the threshold voltage, the charging of the third capacitor Stops the work, and a third corresponding to the charging operation of the capacitor, the monostable multivibrator clock signal generator for outputting the clock signals of said first and said second monostable multivibrator.

  According to the present embodiment, since the first monostable multivibrator and the second monostable multivibrator are operated by the clock signal generated by the clock signal generating monostable multivibrator, the first pulse can be used without using an external clock. The signal and the second pulse signal can be synchronized. When the input signal is 0, the second pulse signal is also at a high level when the first pulse signal is at a high level, and the second pulse signal is also at a low level when the first pulse signal is at a low level. Therefore, when the full-bridge switching amplifier is operated using the first pulse signal and the second pulse signal, no current flows through the load when the input signal is 0, so that the generation of noise can be prevented.

  In a preferred embodiment, the first monostable multivibrator is supplied with a high level signal when the clock signal or the first pulse signal is at a high level, and a low level signal is supplied to one end of the first capacitor. By supplying, the first capacitor is charged by the first charging current, and when the clock signal and the first pulse signal are at low level, a low level signal is supplied and a high level signal is supplied to the first capacitor. A first inverter for stopping charging of the first capacitor by supplying to one end of the capacitor; and outputting a high-level first pulse signal when a charging voltage of the first capacitor does not reach the threshold voltage. When the charging voltage of the first capacitor reaches the threshold voltage, the first pulse signal having a low level is The second monostable multivibrator is supplied with a high level signal when the clock signal or the second pulse signal is at a high level, and outputs a low level signal to the first inverter. By supplying one end of two capacitors, the second capacitor is charged by the second charging current, and when the clock signal and the second pulse signal are at a low level, a low level signal is supplied and a high level signal is supplied. A third inverter for stopping charging of the second capacitor by supplying a signal to one end of the second capacitor; and the second inverter at a high level when the charging voltage of the second capacitor does not reach the threshold voltage. When the pulse voltage is output and the charging voltage of the second capacitor reaches the threshold voltage, the low level of the second capacitor is output. Further comprising a fourth inverter for outputting a scan signal.

  In a preferred embodiment, when the clock signal generating monostable multivibrator is a fifth inverter that inverts the first pulse signal, and the pulse signal from the fifth inverter or the output signal of the seventh inverter is at a high level. Is supplied with a high level signal and a low level signal is supplied to one end of the third capacitor to charge the third capacitor with the second charging current, and the pulse signal from the fifth inverter and the A sixth inverter that stops charging of the third capacitor by supplying a low-level signal to the one end of the third capacitor when the output signal of the seventh inverter is low; When the charging voltage of the third capacitor does not reach the threshold voltage, a high level signal is When the charging voltage of the third capacitor reaches the threshold voltage, the seventh inverter that outputs the low level signal and the signal from the seventh inverter are inverted and the clock signal is output. And an eighth inverter.

  A pulse width modulation circuit according to another preferred embodiment of the present invention includes a first charging current generator that generates a first charging current that is a sum of a predetermined bias current and a current that varies in proportion to an input signal, A monostable multivibrator for generating a clock signal, having a second charging current generating unit that generates a second charging current that is a difference between a predetermined bias current and a current that changes in proportion to the input signal, and a first capacitor In response to the inversion of the clock signal supplied from the other level to the one level, the charging operation of the first capacitor is started by the first charging current, and the charging voltage of the first capacitor reaches the threshold voltage. A first monostable multivibrator for stopping the charging operation of the first capacitor and outputting a first pulse signal in response to the charging operation of the first capacitor; In response to inversion of the clock signal supplied from the monostable multivibrator for generating a clock signal from the other level to the one level, the second capacitor is charged with the second charging current. A second unit that stops the charging operation of the second capacitor when the charging voltage of the second capacitor reaches a threshold voltage and outputs a second pulse signal in accordance with the charging operation of the second capacitor. A stable multivibrator and a third capacitor, wherein the second pulse signal is supplied as a clock signal, and the first charging current is responsive to inversion of the second pulse signal from the one level to the other level. To start the charging operation of the third capacitor, and when the charging voltage of the third capacitor reaches a threshold voltage, Stops the electric operation, and a third corresponding to the charging operation of the capacitor, the monostable multivibrator clock signal generator for outputting the clock signals of said first and said second monostable multivibrator.

  It is possible to provide a pulse width modulation circuit that prevents the occurrence of switching noise when the input signal is 0 and that synchronizes the two output pulse width modulation signals without using an external clock.

1 is a block diagram illustrating a switching amplifier according to a preferred embodiment of the present invention. 1 is a block diagram illustrating a pulse width modulation circuit according to a preferred embodiment of the present invention. FIG. 6 is a block diagram illustrating a pulse width modulation circuit according to another preferred embodiment of the present invention. 1 is a circuit diagram illustrating a pulse width modulation circuit according to a preferred embodiment of the present invention. FIG. 6 is a circuit diagram showing a pulse width modulation circuit according to another preferred embodiment of the present invention. It is a time chart which shows the voltage waveform of each part of a pulse width modulation circuit. It is a time chart which shows the voltage waveform of each part of a pulse width modulation circuit.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to these embodiments. FIG. 1 is a block diagram illustrating a switching amplifier according to a preferred embodiment of the present invention.

  First, a schematic configuration of a switching amplifier 10 to which the pulse width modulation circuit 1 of the present invention is applied will be described with reference to FIG. The switching amplifier 10 includes a pulse width modulation circuit 1 and switch elements 11 to 14. The pulse width modulation circuit 1 performs pulse width modulation on the input signal to generate a first pulse signal OUTa and a second pulse signal OUTb. For example, MOSFETs are employed as the switch elements 11 to 14 (hereinafter referred to as MOSFETs 11 to 14), and the MOSFETs 11 to 14 are connected by a full bridge.

  The first pulse signal OUTa is supplied to the gates of the MOSFETs 11 and 12, and the second pulse signal OUTb is supplied to the gates of the MOSFETs 13 and 14. For example, the MOSFET 11 and the MOSFET 12 have different polarities. When the first pulse signal OUTa is at a high level, the MOSFET 11 is turned off and the MOSFET 12 is turned on. When the first pulse signal is at a low level, the MOSFET 11 is turned on and the MOSFET 12 is turned on. Turn off. The MOSFETs 13 and 14 have different polarities. When the second pulse signal OUTb is at a high level, the MOSFET 13 is turned off and the MOSFET 14 is turned on. When the second pulse signal OUTb is at a low level, the MOSFET 13 is turned on and the MOSFET 14 is turned off. become.

  When the MOSFETs 11 and 14 are on and the MOSFETs 12 and 13 are off, current flows in the order of the power source + VD, the MOSFET 11, the load (speaker) 15, the MOSFET 14, and the power source -VD. When the MOSFETs 12 and 13 are on and the MOSFETs 11 and 14 are off, current flows in the order of the power supply + VD, the MOSFET 13, the load 15, the MOSFET 12, and the power supply -VD. When the MOSFETs 11 and 13 are on and the MOSFETs 12 and 14 are off, no current flows through the load. When the MOSFETs 12 and 14 are on and the MOSFETs 11 and 13 are off, no current flows through the load.

  The MOSFETs 11 and 12 having the same polarity may be used, and a signal obtained by inverting the first pulse signal OUTa may be supplied to one MOSFET. The MOSFETs 13 and 14 having the same polarity may be used, and a signal obtained by inverting the second pulse signal OUTb may be supplied to one MOSFET.

  FIG. 2A is a block diagram showing the pulse width modulation circuit 1 of the present embodiment. FIG. 3A is a circuit diagram showing details of the pulse width modulation circuit 1 of the present embodiment. First, an outline of the pulse width modulation circuit 1 will be described mainly with reference to FIG. 2A. The pulse width modulation circuit 1 includes a charging current generator 2, a first monostable multivibrator 3, a second monostable multivibrator 4, and a monostable multivibrator 5 for generating a clock signal.

  The charging current generator 2 includes a first charging current generator that generates a first charging current Ia and a second charging current generator that generates a second charging current Ib. The first charging current Ia is the sum (Io + i) of the predetermined bias current Io and the current i that changes in proportion to the input signal (audio signal) supplied from the input signal source S. The second charging current Ib is a difference (Io−i) between the predetermined bias current Io and a current i that changes in proportion to the input signal (audio signal) supplied from the input signal source S.

  The first monostable multivibrator 3 has a first capacitor Ca (integrator, see FIG. 3A), and inverts the clock signal supplied from the clock signal generating monostable multivibrator 5 from the other level to one level ( For example, in response to the rise from the low level to the high level, the charging operation of the first capacitor Ca is started by the first charging current Ia. The first monostable multivibrator 3 stops the charging operation of the first capacitor Ca when the charging voltage of the first capacitor Ca reaches a predetermined threshold voltage. The first monostable multivibrator 3 outputs the first pulse signal OUTa in accordance with the charging operation of the first capacitor Ca.

  The second monostable multivibrator 4 has a second capacitor Cb (integrator, see FIG. 3A), and inverts the clock signal supplied from the clock signal generating monostable multivibrator 5 from the other level to one level ( For example, in response to the rise from the low level to the high level, the charging operation of the second capacitor Cb is started by the second charging current Ib. The second monostable multivibrator 4 stops the charging operation of the second capacitor Cb when the charging voltage of the second capacitor Cb reaches a predetermined threshold voltage. Then, the monostable multivibrator 4 outputs the second pulse signal OUTb according to the charging operation of the second capacitor Cb.

  The clock signal generating monostable multivibrator 5 includes a third capacitor Cc, and the first pulse signal OUTa is supplied as a clock signal, and the first pulse signal OUTa is inverted from one level to the other level (for example, high level). In response to the falling to the low level, the charging operation of the third capacitor Cc is started by the second charging current Ib. The clock signal generating monostable multivibrator 5 stops the charging operation of the third capacitor Cc when the charging voltage of the third capacitor Cc reaches a predetermined threshold voltage. The clock signal generating monostable multivibrator 5 outputs the third pulse signal as the clock signals of the first monostable multivibrator 3 and the second monostable multivibrator 4 in accordance with the charging operation of the third capacitor Cc. .

  Next, details of the pulse width modulation circuit 1 will be described with reference to FIG. 3A. The current generator 2 includes transistors Q1 to Q9, resistors Re1 and Re2, resistors R1 to R5, an input signal source S, and a constant current source J.

  The transistors Q1 and Q2, resistors Re1 and Re2, and the constant current source J constitute a differential amplifier circuit, and the transistors Q1 and Q2 generate a differential current according to an input signal. That is, the sum of the collector currents of the transistors Q1 and Q2 is the current 2Io of the constant current source J, and the distribution ratio of the differential signal is determined according to the input signal. The connection configuration will be described. The base of the transistor Q1 is connected to the positive side of the input signal source S, the emitter is connected to one end of the constant current source J through the resistor Re1, the collector is the collector of the transistor Q3, and the transistor Q5 Connected to the base of the. The base of the transistor Q2 is connected to the ground potential, the emitter is connected to one end of the constant current source J via the resistor Re2, and the collector is connected to the collector of the transistor Q6 and the base of the transistor Q9. The other end of the constant current source J is connected to the power supply line -VCC. The resistance values of the resistors Re1 and Re2 are the same.

  The transistors Q3, Q4, Q5 and the resistors R1, R2 constitute a first current generator (current mirror circuit) that generates the first charging current Ia. A collector current flows through the transistor Q3 based on the collector current of the transistor Q1 of the differential amplifier circuit, and the same current as the collector current of the transistor Q3 flows as the collector current Ia of the transistor Q4. The connection configuration will be described. The base of the transistor Q3 is connected to the base of the transistor Q4 and the emitter of the transistor Q5, the collector is connected to the collector of the transistor Q1 and the base of the transistor Q5, and the emitter is connected via the resistor R1. And connected to the positive power supply line + VCC. The transistor Q4 has a collector serving as an output terminal for the first charging current Ia and is connected to the first capacitor Ca and the like of the first monostable multivibrator 3, and an emitter connected to the positive power supply line + Vcc via the resistor R2. Has been. The transistor Q5 has a base connected to the collector of the transistor Q3 and the collector of the transistor Q1, an emitter connected to both bases of the transistors Q3 and Q4, and a collector connected to the negative power supply line -Vcc. The transistor Q5 is for compensating the base current of the transistors Q3 and Q4, and reduces variations in the first charging current Ia together with the resistors R1 and R2.

  The transistors Q6, Q7, Q8, and Q9 and the resistors R3, R4, and R5 constitute a second current generation unit (current mirror circuit) that generates the second charging current Ib. A collector current flows through the transistor Q6 based on the collector current of the transistor Q2 of the differential amplifier circuit, and the same current as the collector current of the transistor Q6 flows as the collector current Ib of the transistors Q7 and Q8. The connection structure will be described. The base of the transistor Q6 is connected to the bases of the transistors Q7 and Q8 and the emitter of the transistor Q9, the collector is connected to the collector of the transistor Q2 and the base of the transistor Q9, and the emitter is a resistor. It is connected to the positive power supply line + VCC via R3. The transistor Q7 has a collector serving as an output terminal for the second charging current Ib, connected to the second capacitor Cb and the like of the second monostable multivibrator 4, and an emitter connected to the positive power supply line + Vcc via the resistor R4. ing. The transistor Q8 has a collector serving as an output terminal for the second charging current Ib, connected to the third capacitor Cc and the like of the monostable multivibrator 5 for generating a clock signal, and an emitter connected to the positive power supply line + Vcc via the resistor R5. It is connected. The transistor Q9 has a base connected to the collector of the transistor Q6 and the collector of the transistor Q2, an emitter connected to each base of the transistors Q6, Q7, and Q8, and a collector connected to the negative power supply line -Vcc. The transistor Q9 is for compensating the base current of the transistors Q6, Q7, and Q8, and reduces variations in the second charging current Ib together with the resistors R3, R4, and R5.

  The first monostable multivibrator 3 includes a first inverter Qa1, a second inverter Qa2, and a first capacitor Ca. The first monostable multivibrator 3 includes diodes Da1, Da2, Da3, and a resistor Ra. The first inverter Qa1 inverts the high-level signal because the high-level signal is supplied to the input via the diode Da1 or Da2 when the input clock signal or the first pulse signal OUTa is at the high level. The low level signal is supplied to the first capacitor Ca. Therefore, the first capacitor Ca can be charged with the first charging current Ia. The first inverter Qa1 has both the diodes Da1 and Da2 turned off when the input clock signal and the first pulse signal OUTa are at the low level, so that the low level signal is input to the first inverter Qa1 through the resistor Ra. The supplied low level signal is inverted, and the high level signal is supplied to the first capacitor Ca. Therefore, the charging of the first capacitor Ca can be stopped. The second inverter Qa2 outputs a first pulse signal OUTa at a high level when the charging voltage of the first capacitor Ca has not reached the threshold voltage, and is at a low level when the charging voltage of the first capacitor Ca has reached the threshold voltage. The first pulse signal OUTa is output.

  The connection configuration will be described. The diode Da1 has an anode supplied with a clock (third pulse signal) from the clock signal generating monostable multivibrator 5, and a cathode connected to the input of the first inverter Qa1. The first inverter Qa1 has an input connected to the cathode of the diode Da1, a cathode of the diode Da2, and one end of the resistor Ra, and an output connected to one end of the first capacitor Ca. The first capacitor Ca has one end connected to the output of the first inverter Qa1 and the other end connected to the input of the second inverter Qa2. The second inverter Qa2 has an input connected to the other end of the first capacitor Ca, an output connected to the output of the first monostable multivibrator 3, and the anode of the diode Da2. The anode of the diode Da3 is connected to the other end of the first capacitor Ca and the input of the second inverter Qa2. The diode Da3 protects the second inverter Qa2 by clamping the output of the first capacitor Ca, and bypasses the charge to the power supply line V1 when discharging the charging voltage of the first capacitor Ca. Power supply lines V1 and V2 are connected to the first inverter Qa1 and the second inverter Qa2.

  The second monostable multivibrator 4 includes a third inverter Qb1, a fourth inverter Qb2, and a second capacitor Cb. The second monostable multivibrator 4 includes diodes Db1, Db2, and Db3, and a resistor Rb. The third inverter Qb1 inverts the high-level signal because the high-level signal is supplied to the input via the diode Db1 or Db2 when the input clock signal or the second pulse signal OUTb is at the high level. The low level signal is supplied to the second capacitor Cb. Therefore, the second capacitor Cb can be charged with the second charging current Ib. The third inverter Qb1 has both the diodes Db1 and Db2 turned off when the input clock signal and the second pulse signal OUTb are at a low level, so that a low level signal is input to the third inverter Qb1 through the resistor Rb. The low level signal is supplied, and the high level signal is supplied to the second capacitor Cb. Accordingly, the charging of the second capacitor Cb can be stopped. The fourth inverter Qb2 outputs a high-level second pulse signal OUTb when the charging voltage of the second capacitor Cb has not reached the threshold voltage, and is low when the charging voltage of the second capacitor Cb has reached the threshold voltage. The second pulse signal OUTb is output.

  The connection configuration will be described. The diode Db1 has an anode supplied with a clock (third pulse signal) from the clock signal generating monostable multivibrator 5, and a cathode connected to the input of the third inverter Qb1. The third inverter Qb1 has an input connected to the cathode of the diode Db1, a cathode of the diode Db2, and one end of the resistor Rb, and an output connected to one end of the second capacitor Cb. The second capacitor Cb has one end connected to the output of the third inverter Qb1 and the other end connected to the input of the fourth inverter Qb2. The fourth inverter Qb2 has an input connected to the other end of the second capacitor Cb, an output connected to the output of the second monostable multivibrator 4, and the anode of the diode Db2. The diode Db3 has an anode connected to the other end of the second capacitor Cb and the input of the fourth inverter Qb2. The diode Db3 protects the fourth inverter Qb2 by clamping the output of the second capacitor Cb, and bypasses the power line V1 when discharging the charging voltage of the second capacitor Cb. Power supply lines V1 and V2 are connected to the third inverter Qb1 and the fourth inverter Qb2.

  The clock signal generating monostable multivibrator 5 includes a fifth inverter Qc1, a sixth inverter Qc2, a seventh inverter Qc3, an eighth inverter Qc4, and a third capacitor Cc. The clock signal generating monostable multivibrator 5 includes diodes Dc1, Dc2, and Dc3, and a resistor Rc. The fifth inverter Qc1 inverts the first pulse signal OUTa as an input clock signal and supplies it to the anode of the diode Dc1. When the input clock signal or the signal from the seventh inverter Qc3 is at a high level, the sixth inverter Qc2 is supplied with a high level signal through the diode Dc1 or Dc2, so that the high level signal is The signal is inverted and a low level signal is supplied to the third capacitor Cc. Therefore, the third capacitor Cc can be charged with the second charging current Ib. The sixth inverter Qc2 has both the diodes Dc1 and Dc2 turned off when the input clock signal and the signal from the seventh inverter Qc3 are at a low level, so that a low level signal is output via the resistor Rc. The low level signal is supplied to the input, the low level signal is inverted, and the high level signal is supplied to the third capacitor Cc. Therefore, the charging of the third capacitor Cc can be stopped. When the charging voltage of the third capacitor Cc does not reach the threshold voltage, the seventh inverter Qc3 outputs a high level signal, and the eighth inverter Qc4 outputs a low level signal. When the charging voltage of the third capacitor Cc reaches the threshold voltage, the seventh inverter Qc3 outputs a low level signal, and the eighth inverter Qc4 outputs a high level signal.

  The connection configuration will be described. The fifth inverter Qc1 has an input connected to the output of the second inverter Qa2 and an output connected to the anode of the diode Dc1. The diode Dc1 has an anode connected to the output of the fifth inverter Qc1 and a cathode connected to the input of the sixth inverter Qc2. The sixth inverter Qc2 has an input connected to the cathode of the diode Dc1, a cathode of the diode Dc2, and one end of the resistor Rc, and an output connected to one end of the third capacitor Cc. The third capacitor Cc has one end connected to the output of the sixth inverter Qc2 and the other end connected to the input of the seventh inverter Qc3. The seventh inverter Qc3 has an input connected to the other end of the third capacitor Cc, an output connected to an input of the eighth inverter Qc4, and an anode of the diode Dc2. The output of the eighth inverter Qc4 is connected to the anode of the diode Da1 and the anode of the diode Db1. The diode Dc3 has an anode connected to the other end of the third capacitor Cc and the input of the seventh inverter Qc3. The diode Dc3 protects the seventh inverter Qc3 by clamping the output of the third capacitor Cc, and also bypasses the power line V1 when discharging the charging voltage of the third capacitor Cc. Power supply lines V1 and V2 are connected to the sixth inverter Qc2 and the seventh inverter Qc3.

  Hereinafter, the operation of the pulse width modulation circuit 1 of the present embodiment will be described. FIG. 4 is a time chart showing voltage waveforms at each point of the pulse width modulation circuit 1, and each number corresponds to a voltage of each number in FIG. 3A. First, it is assumed that the charge of the first capacitor Ca, the second capacitor cb, and the third capacitor Cc is 0 at time t1. That is, the voltages (3) and (6) are both at the low level (V2). Here, the clock (third pulse signal) from the monostable multivibrator 5 for generating a clock signal becomes a high level (see (1)).

  Focusing on the first monostable multivibrator 3, a high-level clock is supplied to the first inverter Qa1 via the diode Da1, and the output (2) of the first inverter Qa1 and the input (3) of the second inverter Qa2 ) Are both low. Therefore, the output of the second inverter Qa2, that is, the first pulse signal OUTa becomes high level (see (4)).

  Focusing on the second monostable multivibrator 4, a high level clock is supplied to the third inverter Qb1 via the diode Db1, and the output (5) of the third inverter Qb1 and the input (6 of the fourth inverter Qb2). ) Are both low. Accordingly, the output of the fourth inverter Qb2, that is, the second pulse signal OUTb becomes high level (see (7)).

  Focusing on the clock signal generating monostable multivibrator 5, a high-level first pulse signal OUTa is supplied to the input of the fifth inverter Qc1. The output of the fifth inverter Qc1 becomes low level (8). Since the diode Dc1 is turned off, the power source V2 is connected to the input of the sixth inverter Qc2 and becomes low level. Accordingly, the output of the sixth inverter Qc2 becomes high level (9), and the input of the seventh inverter Qc3 becomes high level (10). Accordingly, the output of the seventh inverter Qc3 is low level (11), and the output of the eighth inverter Qc4, that is, the third pulse signal is high level (1).

As time elapses from time t1, charging operation of each capacitor is executed.
Focusing on the first monostable multivibrator 3, the first charging current Ia flows to the other end of the first capacitor Ca, and the first capacitor Ca is charged (see (3)). The charging speed of the first capacitor Ca (slope of voltage increase) is due to the magnitude of the first charging current Ia. Similarly, paying attention to the second monostable multivibrator 4, the second charging current Ib flows to the other end of the second capacitor Cb and the second capacitor Cb is charged (see (6)). The charging speed of the second capacitor Cb (slope of voltage increase) is due to the magnitude of the second charging current Ib.

  Of the first capacitor Ca and the second capacitor cb, the charge voltage of the capacitor to which the larger current is supplied first reaches the threshold voltage vth. For example, in the example of FIG. 4, since the first charging current Ia is larger than the second charging current Ib, the charging voltage of the first capacitor Ca becomes the threshold voltage before the charging voltage of the second capacitor Cb at time t2. Vth is reached (see (3) and (6)). That is, at time t2, the charging voltage of the second capacitor Cb has not reached the threshold voltage Vth. The threshold voltage is the threshold voltage of the second inverter Qa2 and the fourth inverter Qa4, and these threshold voltages are the same value. Therefore, at time t2, the output of the second inverter Qa2, that is, the first pulse signal OUTa is inverted from the high level to the low level (see (4)). The diode Da2 is turned off by being reverse-biased by the low-level first pulse signal OUTa.

  When the output of the second inverter Qa2 becomes low level, the output of the fifth inverter Qc1 is inverted from low level to high level in the clock signal generating monostable multivibrator 5 (see (8)), and the sixth inverter Qc2 The output is inverted from the high level to the low level (see (9)). Since the potential of the other end (10) of the third capacitor Cc was clamped by the diode Dc3 until this inversion occurred, the charge at the moment of inversion was 0, and from this point on, the second charge current Ib caused the third charge. The capacitor Cc is charged (see (10)). The charging speed (voltage increase slope) of the third capacitor Cc is caused by the magnitude of the second charging current Ib. Therefore, at time t2, the input of the seventh inverter Qc3 is at the low level (see (10)), the output is at the high level (see (11)), and the output of the eighth inverter Qc4 is at the low level ((1 )reference).

  When the output of the eighth inverter Qc4 is inverted to a low level, when attention is paid to the first monostable multivibrator 3, the diode Da1 is turned off. As a result, the input of the first inverter Qa1 is pulled down to the power supply line V2 (that is, the low level voltage) via the resistor Rb (since the diode Da2 is also turned off as described above). Therefore, the output of the first inverter Qa1 is inverted from the low level to the high level (see (2)). The voltage at the other end (3) of the first capacitor Ca rises to a high level due to an increase in the voltage at the one end (2), but the charge accumulated in the first capacitor Ca causes the diode Da3 at this moment. Therefore, the voltage does not rise above the power supply voltage V1. Thereby, the charging operation by the first charging current Ia of the first capacitor Ca is stopped.

  On the other hand, focusing on the second monostable multivibrator 4, the output of the eighth inverter Qc4 is inverted to a low level, whereby the diode Db1 is turned off. However, since the charging voltage of the second capacitor Cb has not yet reached the threshold voltage (see (6)), and the output of the fourth inverter Qb2 is maintained at the high level (see (7)), the diode Db2 continues to be in an ON state, and a high level signal continues to be supplied to the input of the third inverter Qb1, and no change occurs at this point.

  At time t3, since the charging voltage of the second capacitor reaches the threshold voltage Vth of the fourth inverter Qb2, the output of the fourth inverter Qb2, that is, the second pulse signal OUTb is inverted from the high level to the low level ((7) reference). The diode Db2 is reverse-biased by the low-level second pulse signal OUTb and is turned off. As described above, since the diode Db1 is also in the OFF state, the input of the third inverter Qb1 is pulled down to the power supply line V2 (low level) via the resistor Rb. Accordingly, the output of the third inverter Qb1 is inverted from the low level to the high level (see (5)). The voltage at the other end (6) of the second capacitor Cb rises to a high level due to an increase in the voltage at the one end (5), but the charge accumulated in the second capacitor Cb causes the diode Db3 at this moment. Therefore, the voltage does not rise above the power supply voltage V1. Thereby, the charging operation by the second charging current Ib of the second capacitor Cb is stopped.

  At time t4, since the charging voltage of the third capacitor C3 reaches the threshold voltage Vth of the seventh inverter Qc3 (see (10)), the output of the seventh inverter Qc3 is inverted from the high level to the low level ((11) reference). Therefore, the diode Dc2 is turned off when a low level signal is supplied to the anode. The eighth inverter Qc4 has an input at a low level and an output (clock signal) at a high level (see (1)). A high level clock signal is supplied to the input of the first inverter Qa1, the output of the first inverter Qa1 becomes low level (see (2)), and the output of the second inverter Qa2, that is, the first pulse signal OUTa is high. Level (see (4)), charging of the first capacitor Ca with the first charging current Ia is started. Similarly, a high level clock signal is supplied to the input of the third inverter Qb1, the output of the third inverter Qb1 becomes low level (see (5)), and the output of the fourth inverter Qb2, that is, the second pulse signal. OUTb becomes a high level (see (7)), and charging of the second capacitor Cb with the second charging current Ib is started.

  As the first pulse signal OUTa is inverted to the high level, the output of the fifth inverter Qc3 goes to the low level (see (8)), the diode Dc1 is turned off, and the input of the sixth inverter Qc2 is the power line. Pulled down to V2 (low level voltage), the output of the sixth inverter Qc2 becomes high level (see (9)). Therefore, the voltage at the other end (10) of the third capacitor Cc rises to a high level due to the increase in the voltage at the one end (9), but the charge accumulated in the third capacitor Cc becomes a diode at this moment. Since it is bypassed to the power supply line V1 via Dc3, it does not rise above the power supply voltage V1. Thereby, the charging operation is stopped at the second charging current Ib of the third capacitor Cc. After t4, the above operation is repeated.

  The output of the pulse width modulation circuit 1 can be regarded as a difference signal between the first pulse signal OUTa and the second pulse signal OUTb. For example, by subtracting the first pulse signal OUTa from the second pulse signal OUTb, a positive-phase output pulse width modulation signal can be output.

  FIG. 5 is a time chart showing the change in voltage waveform of each part when the input signal is changed in the pulse width modulation circuit 1 of the present embodiment. Since the first charging current Ia is larger than the second charging current Ib during the positive period of the input signal, the time during which the charging voltage of the first capacitor Ca reaches the threshold voltage is the threshold voltage of the second capacitor Cb. It takes less time to reach the voltage. Accordingly, the first pulse signal OUTa (see (4)) has a short high level period and a long low level period. The second pulse signal OUTb (see (7)) has a long high level period and a low level period. Therefore, when the output signal of the pulse width modulation circuit 1 is the second pulse signal OUTb−the first pulse signal OUTa, the pulse width modulation signal has a long high level period and a short low level period.

  Since the first charging current Ia is smaller than the second charging current Ib during the negative period of the input signal, the charging voltage of the first capacitor Ca is the threshold time until the charging voltage of the second capacitor Cb reaches the threshold voltage. It takes less time to reach the voltage. Therefore, the first pulse signal OUTa (see (4)) has a long high level period and a short low level period. The second pulse signal OUTb (see (7)) has a short high level period and a long low level period. Therefore, when the output signal of the pulse width modulation circuit 1 is second pulse signal OUTb-first pulse signal OUTa, the pulse width modulation signal is short in the high level period and long in the low level period.

  Since the first charging current Ia and the second charging current Ib are equal during the period when the input signal is 0, the time when the charging voltage of the first capacitor Ca reaches the threshold voltage and the charging voltage of the second capacitor Cb are the threshold voltage. The time to reach is equal. Therefore, the first pulse signal OUTa (see (4)) has the same high level period and low level period. The second pulse signal OUTb (see (7)) has the same high level period and low level period. Therefore, when the output signal of the pulse width modulation circuit 1 is second pulse signal OUTb−first pulse signal OUTa, the pulse width modulation signal is always 0.

A case where the MOSFETs 11 to 14 in FIG. 1 are driven by the first pulse signal OUTa and the second pulse signal OUTb will be described.
(Input signal is positive period)
When both the first pulse signal OUTa and the second pulse signal OUTb are at a high level, the MOSFETs 12 and 14 are on and the MOSFETs 11 and 13 are off, so that no current flows through the load 15. When the first pulse signal OUTa is at a low level and the second pulse signal OUTb is at a high level, the MOSFETs 11 and 14 are on and the MOSFETs 12 and 13 are off. Therefore, the power supply + VD, the MOSFET 11, the load 15, the MOSFET 14, and the power supply −VD. Current flows. When both the first pulse signal OUTa and the second pulse signal OUTb are at a low level, the MOSFETs 11 and 13 are on and the MOSFETs 12 and 14 are off, so that no current flows through the load 15.

(Input signal is negative)
When both the first pulse signal OUTa and the second pulse signal OUTb are at a high level, the MOSFETs 12 and 14 are on and the MOSFETs 11 and 13 are off, so that no current flows through the load 15. When the first pulse signal OUTa is at a high level and the second pulse signal OUTb is at a low level, the MOSFETs 12 and 13 are on and the MOSFETs 11 and 14 are off. Therefore, the power supply + VD, the MOSFET 13, the load 15, the MOSFET 12, and the power supply −VD. Current flows. When both the first pulse signal OUTa and the second pulse signal OUTb are at a low level, the MOSFETs 11 and 13 are on and the MOSFETs 12 and 14 are off, so that no current flows through the load 15.

(Period when input signal is 0)
When both the first pulse signal OUTa and the second pulse signal OUTb are at a high level, the MOSFETs 12 and 14 are on and the MOSFETs 11 and 13 are off, so that no current flows through the load 15. When both the first pulse signal OUTa and the second pulse signal OUTb are at a low level, the MOSFETs 11 and 13 are on and the MOSFETs 12 and 14 are off, so that no current flows through the load 15. Thus, since no current flows through the load at all times during the period when the input signal is 0, it is possible to prevent noise from occurring when there is no sound.

  The linearity of the pulse width modulation signal of the pulse width modulation circuit 1 of the present embodiment can be confirmed as follows. The capacitances of the first capacitor Ca, the second capacitor Cb, and the third capacitor Cc are all C, and the voltage required to charge these capacitors to the threshold voltage is Vt (= threshold voltage Vth−power supply voltage V2). The first charging current Ia = Io + i and the second charging current Ib = Io−i. As shown in FIG. 4, the high level period of the first pulse signal OUTa is Tah, the low level period of the first pulse signal OUTa is Tal, the high level period of the second pulse signal OUTb is Tbh, and the low level of the second pulse signal OUTb is low. The level period is Tbl, the high level period of the third pulse signal is Tch, the low level period of the third pulse signal is Tcl, the high level period of the pulse width modulation signal (see (12)) is Top, and the pulse width modulation signal is 0. Let Ton be the period.

  Since Tah = Tch, Tbh = Tcl, and Tah + Tal = Tbh + Tbl = Tch + Tcl, the high-level period Top of the pulse width modulation signal ((12)) is Top = Tbh−Tbl = Tbh−Tah.

  First, when the input signal is 0, since Ia = Ib = Io, the relationship C * Vt = Io * Tah = Io * Tbh = Io * Tcl is established. If this is modified, Tah = Tbh = Tcl = C * Vt / Io and Top is always 0, so that the pulse width modulation signal is 0 as described above, and no pulse waveform is output.

  Therefore, by driving the load connected between the two outputs with this output waveform, no current due to the switch operation of the switch element flows to the speaker as the load when the input signal is 0, so the radiation noise is greatly increased. In addition, the efficiency can be greatly increased by eliminating the power consumption due to the switch operation without inserting a low-pass filter between the load and the load.

On the other hand, when the input signal is not 0, since Tah = C * Vt / (I0 + i) and Tbh = C * Vt / (I0−i), the modulation factor of the pulse width modulation signal (12) is m. Then, m can be expressed by the following formula. m = (Top-Ton) / (Top + Ton) = (Tbh-Tah-Tbl-Tah) / (Tbh-Tah + Tbl + Tah) = (Tbh-3Tah) / (Tbh + Tah) = 2i / I0-1
Therefore, the change in the modulation factor m is proportional to the signal current component i. When i = 0, the modulation degree is −100%, which means that a low level pulse is always output, which is consistent with the above result. Also, the current change due to the input signal is the maximum Io (therefore, the maximum current value summed with the bias current Io is 2Io). At this time, the modulation degree is 100%, and a high level pulse is always output. Become.

  When the input signal current changes in the negative direction, the difference obtained by subtracting the first pulse signal from the second pulse signal is negative, so a pulse is output in the negative direction (see FIG. 5). Therefore, the modulation factor m is m = (Top−Ton) / (Top + Ton) = 2i / Io + 1, and a high level pulse is always output when the input signal is 0, and the maximum in the negative direction due to the input signal. When the current change is −Io (therefore, the minimum current value added to the bias current is 0), a low-level pulse is always output.

  In the pulse width modulation circuit of the present embodiment, when the input signal is 0, the switching output frequencies of the first pulse signal OUTa and the second pulse signal OUTb are the bias current value Io of the charging current generator 2, the capacitors Ca, It is determined by the capacity of Cb and the threshold voltage of the inverter that determines the charging end time, and is determined so as to operate at a sufficiently fast frequency with respect to the band of the input signal. In the integral type pulse width modulation circuit using the astable multivibrator disclosed in Patent Document 1, switching timing adjustment by an external trigger cannot be performed, and thus two types of the same circuit are used to output two types of pulse width modulation signals. But it is impossible to synchronize them. However, in this embodiment, two monostable multivibrators generate two types of pulse width modulation signals, and as their operation (charging) start trigger, a monostable for clock signal generation in which the pulse width changes according to the input signal Since the output of the multivibrator is used, it is possible to employ an integral type pulse width modulation method that is resistant to external noise and to synchronize two pulse width modulation signals.

  According to the present embodiment, high-efficiency and accurate output can be obtained without using ultrahigh-speed switching elements (MOSFETs) 11 to 14. This is largely related to the operation of the current source that determines the integration time as a reference of the pulse width, and is a system in which a predetermined bias current is distributed to the differential current according to the input. Will be twice as much as when there is no input. Therefore, since the minimum pulse width of the first pulse signal and the second pulse signal is half that when the input signal is 0 (frequency is twice), the switching element has switching performance sufficiently satisfying this. As a result, a highly accurate pulse can be efficiently generated even under a high modulation degree. On the load side, since the operation is performed by the differential pulse (phase shift) of the first pulse signal and the second pulse signal, even if each minimum pulse width changes only to half of when the input signal is 0, A very small pulse width can be expressed at both ends.

  Next, another preferred embodiment of the present invention will be described. 2B is a block diagram showing the pulse width modulation circuit 1B according to the present embodiment, and FIG. 3B is a detailed circuit diagram showing the pulse width modulation circuit 1B according to the present embodiment. In both figures, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is incorporated. In the pulse width modulation circuit 1B, the third capacitor Cc of the clock signal generating monostable multivibrator 5 is charged by the first charging current Ia instead of the second charging current Ib. Therefore, the charging current generator 2 supplies the collector current of the transistor Q4 as the first charging current Ia to the first capacitor Ca of the first monostable multivibrator 3, and also supplies the collector current of the transistor Q10 to the first charging current Ia. As well as the third capacitor Cc of the monostable multivibrator 5 for generating a clock signal. Further, the second pulse signal OUTb is supplied to the input of the fifth inverter Qc3 of the clock signal generating monostable multivibrator 5 instead of the first pulse signal OUTa. Other configurations are the same as those in FIGS.

  That is, the clock signal generating monostable multivibrator 5 according to the present embodiment has the third capacitor Cc, the second pulse signal OUTb is supplied as the clock signal, and the second pulse signal OUTb changes from one level to the other level. In response to the inversion (for example, the fall from the high level to the low level), the charging operation of the third capacitor Cc is started by the first charging current Ia. The clock signal generating monostable multivibrator 5 stops the charging operation of the third capacitor Cc when the charging voltage of the third capacitor Cc reaches a predetermined threshold voltage. The clock signal generating monostable multivibrator 5 outputs the third pulse signal as the clock signals of the first monostable multivibrator 3 and the second monostable multivibrator 4 in accordance with the charging operation of the third capacitor Cc. .

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. The first monostable multivibrator may start the charging operation of the first capacitor Ca by the first charging current Ia in response to the falling of the clock signal from the high level to the low level. The vibrator may start the charging operation of the second capacitor Cb by the second charging current Ib in response to the falling of the clock signal from the high level to the low level. The monostable multivibrator for clock signal generation may start the charging operation of the third capacitor Cc by the second charging current Ib in response to the rising of the clock signal from the low level to the high level.

  The present invention is suitably used for an audio amplifier (switching amplifier).

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Charging current generation part 3 1st monostable multivibrator 4 2nd monostable multivibrator 5 Monostable multivibrator for clock signal generation

Claims (4)

A first charging current generator that generates a first charging current that is a sum of a predetermined bias current and a current that varies in proportion to the input signal;
A second charging current generator that generates a second charging current that is a difference between the predetermined bias current and a current that varies in proportion to the input signal;
In response to inversion of the clock signal supplied from the clock signal generating monostable multivibrator from the other level to the other level, the first capacitor starts to charge the first capacitor with the first charging current. When the charging voltage of the first capacitor reaches a threshold voltage, the charging operation of the first capacitor is stopped, and a first pulse signal is output according to the charging operation of the first capacitor. A multivibrator,
A second capacitor, and charging the second capacitor by the second charging current in response to inversion of the clock signal supplied from the clock signal generating monostable multivibrator from the other level to the one level. The operation is started, and when the charging voltage of the second capacitor reaches a threshold voltage, the charging operation of the second capacitor is stopped, and a second pulse signal is output according to the charging operation of the second capacitor. 2 monostable multivibrators,
A third capacitor, wherein the first pulse signal is supplied as a clock signal, and the third capacitor is supplied by the second charging current in response to the inversion of the first pulse signal from the one level to the other level. And the charging operation of the third capacitor is stopped when the charging voltage of the third capacitor reaches a threshold voltage, and the first and the first and the A pulse width modulation circuit comprising: the clock signal generating monostable multivibrator that outputs the clock signals of the second monostable multivibrator. The first monostable multivibrator is:
When the clock signal or the first pulse signal is at a high level, a high level signal is supplied and a low level signal is supplied to one end of the first capacitor, thereby causing the first capacitor to pass through the first charging current. When the clock signal and the first pulse signal are at a low level, a low level signal is supplied and a high level signal is supplied to one end of the first capacitor to charge the first capacitor. A first inverter for stopping
When the charging voltage of the first capacitor does not reach the threshold voltage, the first pulse signal of a high level is output, and when the charging voltage of the first capacitor reaches the threshold voltage, the first of the low level is output. A second inverter that outputs a pulse signal;
The second monostable multivibrator is
When the clock signal or the second pulse signal is at a high level, a high level signal is supplied and a low level signal is supplied to one end of the second capacitor, thereby causing the second capacitor to pass through the second charging current. Charging the second capacitor by supplying a low level signal when the clock signal and the second pulse signal are low level and supplying a high level signal to one end of the second capacitor. A third inverter for stopping
When the charging voltage of the second capacitor has not reached the threshold voltage, the second pulse signal at a high level is output, and when the charging voltage of the second capacitor has reached the threshold voltage, the second at a low level. The pulse width modulation circuit according to claim 1, further comprising a fourth inverter that outputs a pulse signal. The monostable multivibrator for generating the clock signal is
A fifth inverter for inverting the first pulse signal;
When the pulse signal from the fifth inverter or the output signal of the seventh inverter is at a high level, a high level signal is supplied and a low level signal is supplied to one end of the third capacitor, whereby the third capacitor Is charged with the second charging current, and when the pulse signal from the fifth inverter and the output signal of the seventh inverter are at a low level, a low level signal is supplied, and a high level signal is supplied to the third capacitor. A sixth inverter for stopping charging of the third capacitor by supplying to one end;
A high level signal is output when the charging voltage of the third capacitor has not reached the threshold voltage, and the low level signal is output when the charging voltage of the third capacitor has reached the threshold voltage. 7 inverters,
The pulse width modulation circuit according to claim 1, further comprising an eighth inverter that inverts a signal from the seventh inverter and outputs the clock signal. A first charging current generator that generates a first charging current that is a sum of a predetermined bias current and a current that varies in proportion to the input signal;
A second charging current generator that generates a second charging current that is a difference between the predetermined bias current and a current that varies in proportion to the input signal;
In response to inversion of the clock signal supplied from the clock signal generating monostable multivibrator from the other level to the other level, the first capacitor starts to charge the first capacitor with the first charging current. When the charging voltage of the first capacitor reaches a threshold voltage, the charging operation of the first capacitor is stopped, and a first pulse signal is output according to the charging operation of the first capacitor. A multivibrator,
A second capacitor, and charging the second capacitor by the second charging current in response to inversion of the clock signal supplied from the clock signal generating monostable multivibrator from the other level to the one level. The operation is started, and when the charging voltage of the second capacitor reaches a threshold voltage, the charging operation of the second capacitor is stopped, and a second pulse signal is output according to the charging operation of the second capacitor. 2 monostable multivibrators,
A third capacitor, wherein the second pulse signal is supplied as a clock signal, and the third capacitor is supplied by the first charging current in response to inversion of the second pulse signal from the one level to the other level. And the charging operation of the third capacitor is stopped when the charging voltage of the third capacitor reaches a threshold voltage, and the first and the first and the A pulse width modulation circuit comprising: the clock signal generating monostable multivibrator that outputs the clock signals of the second monostable multivibrator.

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