JP5705185B2 - COMMUNICATION DEVICE, ITS CONTROL METHOD, AND COMPUTER PROGRAM - Google Patents

Description

The present invention relates to a communication apparatus, a control method therefor, and a computer program.

  In recent years, low power consumption is required in various information processing devices. Therefore, in order to reduce the power consumption of devices, apart from the normal mode in which normal application processing is performed, there are an increasing number of devices having a power saving mode in which the power consumption is reduced compared to the normal mode.

  There are various types of operations in the power saving mode. Generally, power consumption is reduced by lowering the operating voltage of some circuits and devices constituting the device or stopping the supply of power. Thereby, when a part of the function of the device is not used or during standby, the power consumption can be effectively reduced by putting the device in the power saving mode.

  As a technique for reducing power consumption in the power saving mode, a technique has been proposed in which a program arranged in an SRAM having a low operating voltage is executed in the power saving mode and other memories are put into a power saving state (Patent Literature). 1, see Patent Document 2).

  In these proposed techniques, the program and data arranged in the SDRAM are executed in the normal mode. In the power saving mode, the program for the power saving mode is executed using only the program and data arranged in the SRAM having an operating voltage lower than that of the SDRAM without accessing the SDRAM. As a result, the SDRAM can be put into a power saving state such as self-refreshing, so that power consumption in the power saving mode can be reduced.

On the other hand, multiprocessor / multicore systems equipped with a plurality of processors or a plurality of cores have been increasing in various embedded devices and PCs in recent years, and this trend is expected to accelerate in the future. Even in such a multiprocessor / multicore system, low power consumption is demanded.
JP 2000-105639 A JP 2005-117715 A

  In a multiprocessor / multicore system having a shared memory, the shared memory is accessed from a plurality of processors / cores. Therefore, when the shared memory is set to the power saving state in the power saving mode, it is necessary to stop the access to the shared memory from all the processors / cores at the time of shifting to the power saving mode and to set the power saving state. If there is a processor / core that has not stopped access to the shared memory, unauthorized access to the shared memory or data inconsistency may occur, and the system may not operate normally.

  Further, when returning from the power saving mode to the normal mode, each processor / core must start access to the shared memory after setting the shared memory to the normal state.

  Therefore, in a multiprocessor / multicore system, when shifting to the power saving mode or returning to the normal mode, power saving mode control for safely stopping / starting access to the shared memory is required.

Therefore, the present invention for solving the above problem is a communication device,
A first system having a first processor and realizing a predetermined application function;
A second system having a second processor and communicating with an external device even when the communication device is in a power saving state;
A first memory that the first system accesses without going through the second system , and the second system accesses without going through the first system ;
A second memory that the second system accesses without going through the first system ;
When the communication device shifts to a power saving state that involves stopping the first memory , the second system accesses the second memory from the first memory in accordance with an instruction from the first system. When the destination is switched, both the first system and the second system stop accessing the first memory ,
When the second system stops access to the first memory, a signal is sent to the first system notifying that the second system has stopped accessing the first memory. Send
The communication device shifts to the power saving state when the signal is transmitted .

  According to the present invention, it is possible to provide a power saving mode control for safely stopping / starting access to a shared memory when shifting to a power saving mode or returning to a normal mode in a multiprocessor / multicore system. Can do.

It is a figure which shows an example of a structure of the system in Embodiment 1 of this invention. It is a sequence diagram which shows an example of operation | movement of the main system 102 and the subsystem 103 at the time of power saving mode transfer in Embodiment 1 of this invention. It is a flowchart which shows an example of the operation | movement at the time of the power saving mode transition of the main system 102 in Embodiment 1 of this invention. It is a flowchart which shows an example of the operation | movement at the time of the power saving mode transition of the subsystem 103 in Embodiment 1 of this invention. It is a sequence diagram which shows an example of operation | movement of the main system 102 and the subsystem 103 at the time of normal mode return in Embodiment 1 of this invention. It is a flowchart which shows an example of the operation | movement at the time of the normal mode return of the main system 102 in Embodiment 1 of this invention. It is a flowchart which shows an example of the operation | movement at the time of the normal mode return of the subsystem 103 in Embodiment 1 of this invention. It is a flowchart which shows an example of operation | movement of the migration task of the subsystem 103 in Embodiment 2 of this invention. It is a flowchart which shows an example of operation | movement of the power saving mode task of the subsystem 103 in Embodiment 2 of this invention. It is a flowchart which shows an example of operation | movement of the return task of the subsystem 103 in Embodiment 2 of this invention.

<Embodiment 1>
FIG. 1 shows a configuration diagram of an information processing system in Embodiment 1 of the present invention. In FIG. 1, an information processing system 101 includes a main system 102, a subsystem 103, an SDRAM 104, an inter-CPU communication register 105, a ROM 106, an SRAM 107, and an SRAM 108.

  The main system 102 includes a main CPU 109 and an application function unit 113. The application function unit 113 is a hardware device controlled by the main CPU 109 in order to realize an application function.

  For example, if the information processing system 101 is a printing apparatus, printing is realized as an application function, and a print engine or the like corresponds to the application function unit 113. When the main CPU 109 executes a normal mode program arranged on the SDRAM 104 and controls the application function unit 113, the main system 102 realizes an application function in the normal mode.

  The sub system 103 includes a sub CPU 110 and a communication unit 111. The sub CPU 110 executes a normal mode program arranged in the SDRAM 104 and controls the communication unit 111, thereby communicating with other devices on the network 112.

  The SDRAM 104 is a first shared memory that can be accessed from the main system 102 and the subsystem 103. The SDRAM 104 has a normal state accessible from the main system 102 and the subsystem 103 and a power saving state in which power consumption is reduced instead of being inaccessible. When the information processing system 101 is in the normal mode, which is the first mode, the SDRAM 104 is supplied with normal power and takes a normal state. When the information processing system 101 is in the power saving mode, which is the second mode, the SDRAM 104 takes a power saving state. The main system 102 controls the state transition of the SDRAM 104 from the normal operation state to the power saving operation state and the state transition from the power saving operation state to the normal operation state.

  The power saving state of the SDRAM 104 may be a self-refresh mode or a state where no power is supplied. Hereinafter, the self-refresh mode will be described. In the SDRAM 104, programs and data for the normal mode of the main system 102 and the subsystem 103 are arranged.

  The inter-CPU communication register 105 relays inter-CPU communication between the main CPU 109 and the sub CPU 110. When one CPU writes a predetermined instruction in the inter-CPU communication register 105, an interrupt is generated in the other CPU, and the other CPU can read the predetermined instruction. The main system 102 and the subsystem 103 communicate via the inter-CPU communication register 105.

  The ROM 106 is a memory accessible from the main system 102. The ROM 106 stores programs and data of the main system 102 and the subsystem 103 that are expanded and executed in the SDRAM 104, the SRAM 107, and the SRAM 108 at the time of startup.

  The SRAM 107 is a memory accessible from the main system 102. The SRAM 107 stores a program and data for the power saving mode of the main system 102. The SRAM 108 is a second shared memory that can be accessed from the main system 102 and the subsystem 103. In the SRAM 108, the interrupt vector and interrupt handler of the subsystem 103, and the program and data for the power saving mode are arranged.

  First, processing at the time of starting the information processing system 101 will be described. The main system 102 first executes a program arranged on the ROM 106. When the main CPU 109 starts execution, first, the normal mode program and data of the main system 102 and the subsystem 103 arranged in the ROM 106 are expanded on the SDRAM 104. Subsequently, the program for the power saving mode of the main system 102 is expanded on the SRAM 107, and the program for the power saving mode of the subsystem 103 is expanded on the SRAM 108.

  After that, the main system 102 starts executing the program arranged on the SDRAM 104 and starts up the subsystem. When the sub system 103 is activated, the sub system 103 refers to the reset vector in the vector table arranged in the SRAM 108 and jumps to the normal mode program arranged in the SDRAM 104.

  When the sub-system 103 starts executing the normal mode program, the sub-system 103 notifies the main system 102 that the execution has started via the inter-CPU communication register 105. When these processes are completed, the main information processing system 101 and the subsystem 102 start the normal mode program, and the information processing system 101 performs the normal mode process.

  When the information processing system 101 is in the normal mode, the main system 102 and the subsystem 103 execute a normal mode program arranged in the SDRAM 104. The main system 102 implements application functions. The normal mode program of the subsystem 103 includes an embedded OS, a plurality of normal mode tasks, and a normal mode interrupt program. The embedded OS determines a task to be executed from among a plurality of normal mode tasks, and the subsystem 103 performs processing by switching the task to be executed by the embedded OS.

  When an interrupt occurs in the subsystem 103, the interrupt handler on the SRAM 108 jumps to the normal mode interrupt program on the SDRAM 104 to perform processing for the interrupt. An interrupt to the subsystem 103 is generated from the inter-CPU communication register 105 or the communication unit 111.

  The DMA transfer destination of the communication unit 111 uses an area on the SDRAM 104 in the normal mode. Further, the area of the SDRAM 104 is used as a stack pointer used when the sub CPU 110 executes a program in the normal mode.

  In the first embodiment of the invention, the information processing system 101 shifts to the power saving mode in accordance with an instruction from the main system 102. As a condition for shifting to the power saving mode, a case where a predetermined time has elapsed after the operation of the application function is stopped or a case where the user gives an instruction is assumed. When the information processing system 101 is in the power saving mode, the subsystem 103 operates the communication unit 111. When the communication unit 111 receives a specific packet from the network 112, the information processing system 101 returns from the power saving mode to the normal mode.

  Hereinafter, a method for shifting the information processing system 101 from the normal mode to the power saving mode and a method for returning the information processing system 101 from the power saving mode to the normal mode according to the first embodiment of the present invention will be described.

  First, a method for shifting from the normal mode to the power saving mode will be described. The sequence diagram of FIG. 2 shows the exchange of processing between the main system 102 and the subsystem 103 when the information processing system 101 shifts from the normal mode to the power saving mode. Communication between the main system 102 and the subsystem 103 is performed using an inter-CPU communication register 105. When the information processing system 101 shifts from the normal mode to the power saving mode, first, the main system 102 transmits a power saving mode shift request to the subsystem 103 in step S201.

  When the subsystem 103 receives the request for shifting to the power saving mode, in step S202, the subsystem 103 stops access to the SDRAM 104 and starts executing the power saving mode program arranged in the SRAM. After starting execution of the power saving mode program, the subsystem 103 notifies the main system 102 of the completion of the power saving mode transition as a response to the power saving mode transition request in step S203.

  Details of processing of the main system 102 and the subsystem 103 at this time will be described below. FIG. 3 is a flowchart when the main system 102 shifts to the power saving mode. As for the program for shifting to the power saving mode shown in FIG. 3, steps S301 to S303 are arranged in the SDRAM 104, and steps S304 to S306 are arranged in the SRAM 107.

  First, in step S301, the main system 102 transmits a power saving mode transition request to the subsystem 103 via the inter-CPU communication register 105. Thereafter, in step S302, the notification of completion of the power saving mode transition from the subsystem 103 is awaited. The main system 102 receives a notification of completion of the power saving mode transition from the subsystem 103 via the inter-CPU communication register 105 (first reception).

  After reception, the main system 102 jumps from the program arranged in the SDRAM 104 to the program arranged in the SRAM 107 in step S303 so that the SDRAM 104 can operate in the cell refresh mode. Since the main system 102 and the subsystem 103 thereafter do not access the SDRAM 104, memory control is performed in step S304 to place the SDRAM 104 in the self-refresh mode. In order to further reduce the power consumption, the main system 102 sets the application function unit in the power saving state in step S305, and further reduces the clock of the main CPU 109 in step S306. When the above power saving mode transition processing is completed, the execution of the power saving mode program is started to enter the power saving mode.

  The flowchart in FIG. 4 shows operations from when the subsystem 103 receives the power saving mode transition request until the transition to the power saving mode is completed. The processing from step S401 to step S408 shown in FIG. 4 is arranged on the SDRAM 104, and the processing from step S409 to step S410 is arranged in the SRAM. These processes are executed by a switching task including a program arranged in the SDRAM 104 and a program arranged in the SRAM 108.

  In step S401, the subsystem 103 receives the power saving mode transition request via the inter-CPU communication register 105 (second reception). Subsequently, in order to prevent access to the SDRAM 104 in the power saving mode, in steps S402 to S407, processing for stopping access to the SDRAM 104 is performed, and then the program arranged in the SRAM 108 is executed.

  In step S402, the task is not dispatched to the task arranged in the SDRAM 104 in the power saving mode. The subsystem stops the task arranged in the SDRAM 104 by stopping the task scheduling function of the embedded OS or sufficiently raising the priority of the switching task. In step S403, interrupts are also prohibited.

  In step S404, the DMA transfer destination of the communication unit 111 is changed from the SDRAM 104 to the SRAM 108. At this time, the DMA transfer of the communication unit 111 is temporarily stopped as necessary. In addition, when the packet before transmission remains in the communication unit 111, the information is old even if the packet is transmitted when the processing in the normal mode is resumed, so the packet before transmission is canceled.

  In step S405, the stack pointer is changed. First, the current stack pointer is stored on the SDRAM 104 so that the original stack pointer can be returned to the original position when returning to the normal mode. Then, the stack pointer is moved to a predetermined address on the SRAM 108. Thereby, switching control from the SDRAM 104 to which the subsystem 103 is accessed to the SRAM 108 can be realized.

  In step S406, the interrupt handler for the inter-CPU communication register 105 and the communication unit 111 is jumped to the power saving mode program and the SDRAM 104 is not accessed. If the data on the cache of the sub CPU 110 is not written to the SDRAM 104 before the SDRAM 104 becomes inaccessible, data inconsistency may occur when the normal mode is restored. Therefore, the cache is flushed in step S407, and a sufficient wait is made until the cache is flushed.

  In step S408, execution of the power saving mode program is started by jumping to the power saving mode program arranged on the SRAM 108 or calling a function arranged on the SRAM 108. As a result, access to the SDRAM 104 does not occur.

  When the processing up to step S408 is performed, the subsystem 103 notifies the main system 102 of the completion of the power saving mode transition via the inter-CPU communication register 105 in step S409. Finally, the subsystem 103 permits the interrupt between the inter-CPU communication register 105 and the communication unit 111 in step S410. As a result, the communication unit 111 can receive the packet again. When the DMA transfer is temporarily stopped in step S404, the DMA transfer of the communication unit 111 is resumed here.

  By performing these processes, the subsystem 103 can shift to the power saving mode. In the subsequent processing in the power saving mode, the subsystem 103 continues the processing by the switching task.

  Next, operations in the power saving mode of the main system 102 and the subsystem 103 in the first embodiment of the present invention will be described. The main system 102 waits until receiving a notification from the subsystem 103 that the condition for returning to the normal mode is satisfied.

  On the other hand, the subsystem 103 receives packets from other external devices via the network 112 by the communication unit 111. The reception continues until a specific packet is received. When the subsystem 103 receives the specific packet, the subsystem 103 starts normal mode return processing.

  Hereinafter, a process in which the information processing system 101 returns from the power saving mode to the normal mode will be described.

  FIG. 5 shows a sequence of the main system 102 and the subsystem 103 when the information processing system 101 returns from the power saving mode to the normal mode. Communication between the main system 102 and the subsystem 103 is performed via an inter-CPU communication register 105.

In the power saving mode, the subsystem 103 determines whether or not to return to the normal mode. When the subsystem 103 receives the specific packet as the return condition to the normal mode, the subsystem 103 transmits a normal mode return request to the main system 102 in step S501.
When the main system 102 receives the normal mode transition request, the main system 102 sets the SDRAM 104 to the normal state in step S502. By setting the SDRAM 104 to the normal state, the data stored in the SDRAM 104 can be accessed.

  When the main system 102 makes the SDRAM 104 accessible, the main system 102 notifies the subsystem 103 that the SDRAM 104 is in a normal state in step S503. When the subsystem 103 receives a notification that the SDRAM 104 has entered the normal state, the subsystem 103 switches from executing the program on the SRAM 108 to the program for the normal mode arranged in the SDRAM 104 in step S504.

  When the transition to the normal mode is completed, the subsystem 103 notifies the main system 102 of the completion of the transition to the normal mode in step S505, and the information processing system 101 completes the return to the normal mode.

  Details of processing of the main system 102 and the subsystem 103 at this time will be described below. FIG. 6 shows a flowchart when the main system 102 returns from the power saving mode to the normal mode. The program from step S601 to step S604 of the process shown in FIG. 6 is arranged in the SRAM 107, and the program from step S605 to step S607 is arranged in the SDRAM 104. Both programs are executed by the main CPU 109.

  When the main system 102 receives the normal mode return request from the subsystem 103 in step S601, it raises the clock of the main CPU 109 in step S602, and further sets the application function unit in the normal state in step S603. In step S604, the main system 102 returns the SDRAM 104 that is in the self-refresh mode to the normal state and enables access to the SDRAM 104.

  When the main system 102 becomes accessible to the SDRAM 104, in step S605, the main system 102 starts executing the program arranged on the SDRAM. In step S606, the main system 102 notifies the subsystem 103 that the SDRAM 104 has been brought into a normal state.

  Thereafter, in step S607, the main system 102 waits for notification of completion of the normal mode transition from the subsystem 103. When the main system 102 receives the normal mode shift completion from the subsystem 103 in step S607, the main system 102 executes the normal mode program, and the information processing system 101 completes the return to the normal mode.

  FIG. 7 shows a flowchart when the subsystem 103 returns from the power saving mode to the normal mode. The processing from step S701 to step S704 is arranged in the SRAM 108, and the processing from step S704 to step S710 is arranged in the SDRAM 104. These processes are also continued in the switching task.

  When the subsystem 103 receives the specific packet in the power saving mode and satisfies the return condition to the normal mode, first, the subsystem 103 transmits a normal mode return request to the main system 102 in step S701. Thereafter, in step S702, the subsystem 103 waits for notification from the main system 102 that the SDRAM 104 has been brought into the normal state.

  When the subsystem 103 receives a notification that the SDRAM 104 has been brought into the normal state from the main system 102 in step S702, the subsystem 103 switches to execution using the program and data arranged on the SDRAM 104 in steps S703 to S707.

  In step S703, interrupts relating to the inter-CPU communication register 105 and the communication unit 111 are prohibited. Thereafter, the subsystem 103 jumps from the program arranged in the SRAM 108 in step S704 to the program arranged on the SDRAM 104 or calls a function.

  In step S705, the stack pointer is returned to the address stored in the SDRAM 104 when the mode is shifted to the power saving mode. Further, the subsystem 104 switches the interrupt handler from the inter-CPU communication register 105 and the communication unit 111 to jump to the program for the normal mode in step S706, and sets the DMA transfer destination of the communication unit 111 on the SDRAM 104 in step S707. return. When changing the DMA transfer destination, the DMA transfer is temporarily stopped as necessary. As a result, communication preparation of the communication unit 111 is completed, and switching control from the SRAM 108 to which the subsystem 103 is accessed to the SDRAM 104 can be realized.

  After completing these switching processes, the subsystem 103 notifies the main system 102 that the return to the normal mode has been completed in step S708.

  Subsequently, in order to resume communication in the communication unit 111, the subsystem 103 permits interruption of the inter-CPU communication register 105 and the communication unit 111 in step S709. In step S710, scheduling of the task of the embedded OS is enabled. As a result, the switching task finishes its processing and another task is executed. As a result, the normal mode is restored and the processing in the normal mode is resumed.

<Embodiment 2>
A system configuration diagram of Embodiment 2 of the present invention is shown in FIG. The differences between the second embodiment and the first embodiment are the processing of the subsystem 103 when shifting from the normal mode to the power saving mode, and the processing of the subsystem 103 when shifting from the power saving mode to the normal mode. The exchange sequence between the main system 102 and the subsystem 103 and the processing of the main system 102 are the same as those in the first embodiment.

  A description will be given of processing in which the subsystem 103 transitions from the normal mode to the power saving mode, receives a predetermined packet in the power saving mode, and then returns to the normal mode from the power saving mode. Note that the description of the same points as in the first embodiment will be omitted.

  Transition to the power saving mode, processing in the power saving mode, and return to the normal mode in the subsystem 103 are executed by a migration task, a power saving mode task, and a return task. The respective flowcharts are shown in FIG. 8, FIG. 9, and FIG. The migration task and the return task are arranged in the SDRAM 104, and the power saving mode task is arranged in the SRAM.

  First, when shifting from the normal mode to the power saving mode, a shift task is executed in the subsystem 103. The migration task flowchart will be described with reference to FIG.

In step S801, the subsystem 103 receives the power saving mode transition request via the inter-CPU communication register 105. The processing from step S802 to step S805 is the same as that from step S403 to step S406 of the first embodiment.

After performing the processing up to step S805, the task execution is switched from the transition task to the power saving mode task in step S806 in order to start the execution of the program arranged in the SRAM 108. The power saving mode task is arranged in the SRAM 108.

The processing after switching to the power saving mode task will be described with reference to the flowchart of FIG. First, in step S901, the power saving mode task is not dispatched to a task arranged in the SDRAM 104 by stopping the task scheduling function of the embedded OS or sufficiently increasing the priority of the power saving mode task. In step S902, the cache is flushed, and a sufficient wait is made until flushing is completed. As a result, access to the SDRAM 104 can be stopped. If access to the SDRAM 104 can be stopped, the main system is notified of completion of the power saving mode transition in step S903.

As a final process for shifting to the power saving mode, an interrupt between the inter-CPU communication register 105 and the communication unit 111 is permitted in step S904. Thereby, similarly to the first embodiment, the communication unit 111 can resume the packet reception, and the transition to the power saving mode is completed. The information processing system 101 performs processing in the power saving mode.

In the power saving mode, the power saving mode task executed by the subsystem 103 waits for reception of a predetermined packet in step S905. When the power saving mode task receives a predetermined packet from the communication unit 111 via the network 112, the power saving mode task performs a return process from the power saving mode to the normal mode.

The return process will be described from step S906 in FIG. These processes are continuously performed in the power saving mode task. After receiving the predetermined packet, the power saving mode task transmits a normal mode return request to the main system 102 in step S906. Thereafter, in step S907, the subsystem 103 waits for notification from the main system 102 that the SDRAM 104 has been brought into the normal state.

After receiving the notification, the subsystem 103 prohibits interrupts relating to the inter-CPU communication register 105 and the communication unit 111 in step S908. Thereafter, the subsystem 103 resumes the task scheduling in step S909 and switches the task to the return task in step S910.

The continuation of the process for returning to the normal mode will be described with reference to FIG. FIG. 10 is a flowchart of the return task processing. The return task is arranged in the SDRAM 104.
The process of the return task, the process from step S1001 to step S1005, is the same as the process from step S705 to step S709 in the first embodiment. The process up to step S1005 is performed, the return task finishes the process, and the other task is executed to restart the normal mode program. Thereby, the information processing system 101 completes the return to the normal mode.

  According to each of the above embodiments, when the multiprocessor / multicore system shifts to the power saving mode, the shared memory can be saved without causing unauthorized access to the shared memory or inconsistent data in the shared memory. Can be in power state. In addition, even when shifting to the normal mode, access to the shared memory can be resumed without causing unauthorized access to the shared memory and inconsistency of data in the shared memory.

[Other Embodiments]
The object of the present invention can also be achieved by supplying a storage medium storing a computer program code for realizing the above-described functions to the system, and the system reading and executing the computer program code. In this case, the computer program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the computer program code constitutes the present invention. In addition, the operating system (OS) running on the computer performs part or all of the actual processing based on the code instruction of the program, and the above-described functions are realized by the processing. .

  Furthermore, you may implement | achieve with the following forms. That is, the computer program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer. Then, based on the instruction of the code of the computer program, the above-described functions are realized by the CPU or the like provided in the function expansion card or function expansion unit performing part or all of the actual processing.

  When the present invention is applied to the above storage medium, the computer program code corresponding to the flowchart described above is stored in the storage medium.

101 system 102 main system 103 subsystem 104 SDRAM
105 CPU communication register 106 ROM
107 SRAM
108 SRAM
109 Main CPU
110 Sub CPU
111 Communication unit 112 Network

Claims (15)

A communication device,
A first system having a first processor and realizing a predetermined application function;
A second system having a second processor and communicating with an external device even when the communication device is in a power saving state;
A first memory that the first system accesses without going through the second system , and the second system accesses without going through the first system ;
A second memory that the second system accesses without going through the first system ;
Have
When the communication device shifts to a power saving state that involves stopping the first memory , the second system accesses the second memory from the first memory in accordance with an instruction from the first system. When the destination is switched, both the first system and the second system stop accessing the first memory ,
When the second system stops access to the first memory, a signal is sent to the first system notifying that the second system has stopped accessing the first memory. Send
The communication apparatus shifts to the power saving state when the signal is transmitted .   The second system according to claim 1, wherein when the switching of the access destination from the first memory to the second memory is completed, the second system performs a predetermined notification to the first system. Communication device. If the communication device is shifted to the power saving state, the communication apparatus according to claim 1 or 2, wherein the first memory is characterized by stopping the operation. The second system determines whether to cancel the power saving state of the communication device,
When determining to cancel the power saving state of the communication device, the second system, sending a signal for releasing the stop of the operation of the first memory to the first system The communication device according to claim 3. The second system, on the basis of the data received from the external device, any one of claims 1 to 4, characterized in that determining whether to cancel the power saving state of said communication device The communication apparatus as described in. To cancel the power saving state of the communication device, the second system, any one of claims 1 to 5, characterized in that switching the access destination to the first memory from the second memory 1 The communication device according to item.   The communication device according to claim 1, further comprising a relay unit that relays communication between the first system and the second system. The said 2nd system prohibits dispatch to the program of a said 1st memory when the said communication apparatus transfers to the said power saving state, The any one of Claim 1 thru | or 7 characterized by the above-mentioned. Communication equipment. If the communication apparatus shifts to the power saving state, the second system, wherein after the first prohibited dispatch to the memory of the program starts execution of the second memory in the program The communication device according to any one of claims 1 to 8. If the communication apparatus shifts to the power saving state, the second system, the after starting the execution of the second memory program, characterized in that prohibiting dispatch to the first memory of the program The communication device according to any one of claims 1 to 8. If the communication apparatus shifts to the power saving state, the second system, the priority of the second memory program, characterized by higher than the priority of the first memory program The communication apparatus according to any one of claims 1 to 8. The said 2nd system stops the scheduling which determines the execution order of the program which the said 2nd system performs when the said communication apparatus transfers to the said power saving state, The 1st thru | or 8 characterized by the above-mentioned. The communication apparatus of any one of Claims.   9. The system according to claim 1, wherein when the communication apparatus shifts to the power saving state, the second system performs cache flushing of the second system. 10. Communication device. A first system having a first processor and realizing a predetermined application function;
A second system having a second processor and communicating with an external device even when the communication device is in a power saving state;
A first memory that the first system accesses without going through the second system , and the second system accesses without going through the first system ;
A control method for a communication device, wherein the second system has a second memory that is accessed without going through the first system ,
When the communication device shifts to a power saving state that involves stopping the first memory , the second system accesses the second memory from the first memory in accordance with an instruction from the first system. When the destination is switched, the first system and the second system both include a step of stopping access to the first memory ,
When the second system stops access to the first memory, a signal is sent to the first system notifying that the second system has stopped accessing the first memory. Send
The communication device control method, wherein the communication device shifts to the power saving state when the signal is transmitted . A first system having a first processor and realizing a predetermined application function;
A second system having a second processor and communicating with an external device even when the communication device is in a power saving state;
A first memory that the first system accesses without going through the second system , and the second system accesses without going through the first system ;
A second memory that the second system accesses without going through the first system ;
In a communication device having
When the communication device shifts to a power saving state that involves stopping the first memory , the second system accesses the second memory from the first memory in accordance with an instruction from the first system. When the destination is switched, the access to the first memory is stopped for both the first system and the second system ,
When the second system stops accessing the first memory, a signal is sent to the second system notifying that the second system has stopped accessing the first memory. Send to one system,
A computer program for causing the communication device to shift to the power saving state when the signal is transmitted .

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