JP5709682B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier, and more particularly to an operational amplifier that improves the reliability and stability of input offset voltage zero adjustment in a CMOS process.

In so-called operational amplifiers (operational amplifiers), it is one of the important problems to ensure that the input offset voltage is zero, and it is widely known that various circuits have been proposed and put to practical use. It is where you are.
FIG. 2 shows one conventional circuit for such zero adjustment of the input offset voltage.
In such a conventional circuit, resistors 48a to 48c and resistors 49a to 49c are connected in series between the collectors of the bipolar transistors 45 and 46, respectively, and the resistors 48a to 48c are turned on / off. The switches 50a to 50c are configured by connecting resistors 49a to 49c in parallel with on / off switches 51a to 51c, respectively.
In such a configuration, zero adjustment of the input offset voltage is enabled by appropriately setting on / off of the on / off switches 50a to 50c and 51a to 51c, and the input offset voltage Vos is expressed by the following equation (1). Can do.

  Vos = VT × (−ΔR / R−ΔIs / Is) Equation 1

Here, VT is a thermal voltage, Is is a saturation current of the bipolar transistor, ΔR is a mismatch amount of the resistance values of the resistors 48a to 48c and 49a to 49c, and ΔIs is a mismatch amount of the saturation current of the bipolar transistor.
From Equation 1, it can be understood that the input offset voltage can be adjusted by adjusting the term of ΔR / R.

  Further, the temperature variation of the input offset voltage can be expressed by the following equation 2.

  ∂Vos / ∂T = ∂VT / ∂T × (−ΔR / R−ΔIs / Is) = Vos / T Equation 2

From Equation 2, it can be understood that the initial input offset voltage and the input offset voltage temperature fluctuation are correlated, and theoretically, the input offset voltage temperature fluctuation can also be suppressed by suppressing the initial input offset voltage.
On the other hand, as shown in FIG. 3, in MOS transistors 53 and 54, a circuit configuration similar to that in the case of bipolar transistors is conventionally applied to input offset voltage zero adjustment. In FIG. 3, the same components as those in FIG. 2 are denoted by the same reference numerals.

  In the circuit shown in FIG. 3, the input offset voltage Vos can be expressed by the following equation 3.

  Vos = ΔVth + n · VT {(− ΔR / R) −Δ (W / L) / (W / L)} Expression 3

Here, Vth is a threshold voltage of the MOS transistor, n is expressed as n = (1 + Cjs / Cox), Cjs is a depletion layer region capacitance, and Cox is an oxide film capacitance. W is the gate width and L is the gate length.
A MOS transistor has a strong inversion region and a weak inversion region, and the current equation varies depending on the operation region of the transistor. However, in an actual operational amplifier, the transistor is often used in the vicinity of the weak inversion region. This represents the input offset voltage Vos in the transistor.
From Equation 3, it can be understood that the input offset voltage can be adjusted by adjusting the term of ΔR / R.
The zero adjustment of the input offset voltage of the operational amplifier as described above is disclosed in Non-Patent Document 1, for example.

IEEE journalof Solid-State Circuit, November 1975, Vol. SC-10, pp.412-416

  On the other hand, the input offset voltage temperature fluctuation can be expressed by the following Equation 4.

  ∂Vos / ∂T = ∂Vth / ∂T + n · VT / T {(− ΔR / R) −Δ (W / L) / (W / L)} = ∂Vth / ∂T + (Vos−ΔVth) / T · ..Formula 4

From Equation 4, it can be understood that, in the case of a MOS transistor, even if the initial offset voltage Vos is suppressed, the offset voltage temperature fluctuation cannot always be suppressed.
Actually, when the MOS transistor is used in the vicinity of the weak inversion region, the input offset voltage Vos is dominated by ΔVth which is the mismatch amount of the threshold voltage. Therefore, the input offset voltage adjustment is ΔVth in the ΔR / R term. Will be adjusted to cancel.

  As a result, the ΔR / R term is increased by the input offset voltage adjustment, and the second term in Equation 4 is increased. The first term and the second term in Equation 4 are independent parameters having no correlation, and an increase in the second term directly leads to a deterioration of ∂Vos / ∂T. That is, there is a problem that the input offset voltage temperature fluctuation is deteriorated by performing zero adjustment of the input offset voltage.

  The present invention has been made in view of the above circumstances, and provides an operational amplifier that enables zero adjustment of an input offset voltage without deteriorating input offset voltage temperature fluctuation.

In order to achieve the above object of the present invention, an operational amplifier according to the present invention comprises:
An operational amplifier having a differential amplifier circuit in which a first and second P-channel MOS transistors are differentially connected to form a differential pair,
A negative temperature characteristic current generation circuit that generates and outputs a current having a negative temperature characteristic with respect to a tail current supplied from a tail current source to the first and second P-channel MOS transistors;
An input offset voltage correction current generation circuit for supplying an input offset voltage correction current to each of the first and second P-channel MOS transistors,
The input offset voltage correction current generation circuit is configured to be capable of adjusting the output of the input offset voltage correction current based on the output current of the negative temperature characteristic current generation circuit.

  According to the present invention, the input offset voltage can be zero-adjusted by a current having a negative temperature characteristic with respect to the tail current supplied to the differential amplifier circuit. There is an effect that, after the zero adjustment, it is possible to contribute to the improvement of the stability and reliability of the circuit operation without causing the deterioration of the temperature fluctuation of the input offset voltage.

It is a circuit diagram of the operational amplifier in the embodiment of the present invention. It is a circuit diagram which shows the conventional circuit structural example for the zero adjustment of the input offset voltage in the operational amplifier using a bipolar transistor. It is a circuit diagram which shows the conventional circuit structural example for the zero adjustment of the input offset voltage in the operational amplifier using a MOS transistor.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the circuit configuration of the operational amplifier in the embodiment of the present invention will be described.
The operational amplifier according to the embodiment of the present invention includes a differential amplifier circuit 101 centered on first and second P-channel MOS transistors (hereinafter referred to as “PMOS transistors”) 1 and 2, and an input offset voltage. A correction current generation circuit 102 and a negative temperature characteristic current generation circuit 103 are provided.

The first PMOS transistor 1 and the second PMOS transistor 2 are connected to each other to form a differential connection, and the connection point is connected to the drain of the sixth PMOS transistor 6. A positive power supply voltage is applied to the source of the transistor 6 from a positive power supply (not shown).
On the other hand, a first constant current source 11 is provided in series between the drain of the first PMOS transistor 1 and a negative power source (not shown), and a connection point between the drain and the first constant current source 11. Is connected to the first output terminal 33.

In addition, a second constant current source 12 is provided in series between the drain of the second PMOS transistor 2 and a negative power source (not shown), and the connection between the drain and the second constant current source 12 is provided. A second output terminal 34 is connected to the point.
In the embodiment of the present invention, the ground is a negative power source.
The first input signal 31 is supplied to the gate of the first PMOS transistor 1 through the first input terminal 31, and the second input terminal 32 is supplied to the gate of the second PMOS transistor 2 through the second input terminal 32. The two input signals can be applied from the outside, and the differential amplifier circuit 101 is constituted by the first and second PMOS transistors 1 and 2.

The input offset voltage correction current generation circuit 102 mainly includes eighth to tenth PMOS transistors (first to third PMOS transistors for correction current generation) 8 to 10 and first and second variable resistors 25 and 26. It is configured as a component.
The eighth to tenth PMOS transistors 8 to 10 constitute a current mirror circuit.
That is, the gates of the eighth to tenth PMOS transistors 8 to 10 are connected to each other and to the drain of the eighth PMOS transistor 8.

  The source of the eighth PMOS transistor 8 is passed through the third resistor 23, the source of the ninth PMOS transistor 9 is passed through the first variable resistor 25, and the source of the tenth PMOS transistor 10 is Both are connected to a positive power supply (not shown) via the second variable resistor 26 so that a positive power supply voltage is applied.

On the other hand, the drain of the eighth PMOS transistor 8 is connected to the drain of the seventh NMOS transistor 7 of the negative temperature characteristic current generation circuit 103 described later.
The drain of the ninth PMOS transistor 9 is connected to the drain of the first PMOS transistor 1, and the drain of the tenth PMOS transistor 10 is connected to the drain of the second PMOS transistor 2.

The negative temperature characteristic current generation circuit 103 includes third and fourth N-channel MOS transistors (hereinafter referred to as “NMOS transistors”) 3, 4, a seventh NMOS transistor 7, and first and second constant current sources. 11 and 12 are the main components.
The negative temperature characteristic current generation circuit 103 generates a current having a negative temperature characteristic as a drain current of the seventh NMOS transistor 7 with respect to the third constant current source 13 as a tail current source, as will be described in detail later. Are configured to output.

Specifically, first, the third and fourth NMOS transistors (first and second NMOS transistors for generating negative temperature characteristic current) 3 and 4, and the seventh NMOS transistor (first for generating negative temperature characteristic current). 3 NMOS transistors) 7 are connected as described below to form a current mirror circuit.
That is, the gates of the third and fourth NMOS transistors 3 and 4 are connected to each other, and are connected to the drain of the third NMOS transistor 3 and the gate of the seventh NMOS transistor 7. The source of the seventh NMOS transistor 7 is connected to a negative power source, that is, the ground.

The source of the third NMOS transistor 3 is connected to the negative power source, that is, the ground through the first resistor 21 and the source of the fourth NMOS transistor 4 is connected through the second resistor 22 together. ing.
In the embodiment of the present invention, the first and second resistors 21 and 22 have the same temperature characteristics and both have negative temperature characteristics.

On the other hand, a third constant current source 13 as a tail current source is connected in series between the drain of the third NMOS transistor 3 and a positive power source (not shown). The drain of the fourth NMOS transistor 4 is connected to the drain of the fifth PMOS transistor 5.
The fifth and sixth PMOS transistors 5 and 6 constitute a tail current supply current mirror circuit.

That is, first, the fifth and sixth PMOS transistors 5 and 6 have gates connected to each other and connected to the drain of the fifth PMOS transistor 5.
On the other hand, a positive power supply voltage from a positive power supply (not shown) is applied to the sources of the fifth and sixth PMOS transistors 5 and 6.
The drain of the sixth PMOS transistor 6 is connected to the sources of the first and second PMOS transistors 1 and 2 as described above, and the fifth and sixth PMOS transistors 5 and 6 A current is supplied to the first and second PMOS transistors 1 and 2.

Next, the operation in this configuration will be described.
First, the differential amplification by the first and second PMOS transistors 1 and 2 is performed on the input signals applied to the first input terminal 31 and the second input terminal 32, respectively. The same as above.
Next, the operation of the negative temperature characteristic current generation circuit 103 will be described. First, by a current mirror circuit constituted by the third NMOS transistor 3, the seventh NMOS transistor 7, and the first resistor 21, The current of the third constant current source 13 is mirrored to the drain current of the seventh NMOS transistor 7.
At this time, the drain current of the seventh NMOS transistor 7 is expressed by Equation 5 below.

I2 = [{(W1 / L1) · I1 / (W2 / L2)} ^1/2 + R · I1 · {k ′ (W2 / L2) / 2)} ^1/2 ] ^2.

  Here, I1 is the current value of the third constant current source 13, I2 is the drain current of the seventh NMOS transistor 7, W1 / L1 is the ratio of the gate width W1 to the gate length L1 of the seventh NMOS transistor 7, and W2 / L2 is the ratio of the gate width W2 to the gate length L2 of the third NMOS transistor 3, and R is the resistance value of the first resistor 21. Further, k ′ is expressed as k ′ = μn × Cox, μn is the electron mobility, and Cox is the oxide film capacity per unit area.

According to Equation 5, a current having a negative temperature characteristic with respect to the constant current of the third constant current source 13 is generated and output by using the first resistor 21 having a negative temperature characteristic. I can understand.
The current having the negative temperature characteristic generated by the negative temperature characteristic current generation circuit 103 is supplied to the input offset voltage correction current generation circuit 102 described below.

The input offset voltage correction current generation circuit 102 supplies an input offset voltage correction current from the drains of the ninth and tenth PMOS transistors 9 and 10 to the drains of the first and second PMOS transistors 1 and 2. It has become.
Here, the currents flowing in the ninth and tenth PMOS transistors 9 and 10 pass through the ninth PMOS transistor 9 and the eighth PMOS transistor 8 which forms a current mirror circuit with the ninth PMOS transistor 9 and 10. 7 has a negative temperature characteristic flowing through the NMOS transistor 7.

The value of the correction current can be adjusted by the first and second variable resistors 25 and 26.
In the input offset voltage correction current generation circuit 102, the third resistor 23 and the first and second variable resistors 25 and 26 have the same temperature characteristics, and do not depend on the temperature. The current ratio is constant.

Here, suppression of the input offset voltage temperature fluctuation by the operational amplifier in the embodiment of the present invention described above will be described in comparison with the conventional circuit shown in FIG.
First, in the conventional circuit for zero adjustment of the input offset voltage shown in FIG. 3, the current flowing through the first PMOS transistor 53 is I1, the current flowing through the second PMOS transistor 54 is I2, and the difference is ΔID = I1−I2. Also, ID is defined as (I1-I2) / 2.
Further, the current output from the input offset voltage correction current source 52, the current supplied to the drain of the first PMOS transistor 53 is Itrm1, and the current supplied to the drain of the second pMOS transistor 54 is Itrm2. The difference ΔItrm is assumed to be ΔItrm = Itrm1-Itrm2.
Under this assumption, the input offset voltage in the conventional circuit shown in FIG.

  Vos = ΔVth + n · VT {−ΔID / ID−ΔItrm / ID−Δ (W / L) / (W / L)}

  On the other hand, in the operational amplifier of the embodiment of the present invention described above, zero adjustment of the input offset voltage is performed by the term of ΔItrm / ID in Equation 6. When ID and ΔItrm have the same temperature characteristic, ΔItrm / ID becomes a constant value regardless of the temperature, and the input offset voltage temperature fluctuation is expressed by the following equation (7).

  ∂Vos / ∂T = ∂ΔVth / ∂T + n · VT / T {−ΔID / ID−ΔItrm / ID−Δ (W / L) / (W / L)}

According to Equation 7, it can be understood that the input offset voltage temperature fluctuation is deteriorated by ΔItrm / ID of the second term, and that the problem of the conventional circuit cannot be solved only by the zero adjustment of the input offset voltage.
When ID and ΔItrm have different temperature characteristics, the input offset voltage temperature variation is as shown in Equation 8 below.

  ∂Vos / ∂T = ∂ΔVth / ∂T + n · VT / T {−ΔID / ID−ΔItrm / ID−Δ (W / L) / (W / L)} − n · VT · ∂ (ΔItrm / ID) / ∂T ... Formula 8

According to Equation 8, when ΔItrm / ID has a negative temperature characteristic, the third term becomes a positive value, whereby the second term (−ΔID / ID) and the third term (−ΔItrm / ID). Cancel each other, and the temperature fluctuation of the input offset voltage can be suppressed.
In this case, it does not matter whether the temperature characteristics of ΔItrm and ID are positive or negative, and ΔItrm has a relatively negative temperature characteristic with respect to ID, so that fluctuations in the temperature of the input offset voltage can be suppressed.
The operational amplifier according to the embodiment of the present invention is capable of suppressing the input offset voltage temperature fluctuation as described above by the circuit configuration as described above.

  The present invention can be applied to an operational amplifier in which reliable suppression of input offset voltage temperature fluctuation is desired.

DESCRIPTION OF SYMBOLS 13 ... 3rd constant current source 25 ... 1st variable resistor 26 ... 2nd variable resistor 101 ... Differential amplifier circuit 102 ... Input offset voltage correction current generation circuit 103 ... Negative temperature characteristic current generation circuit

Claims (2)

An operational amplifier having a differential amplifier circuit in which a first and second P-channel MOS transistors are differentially connected to form a differential pair,
A negative temperature characteristic current generation circuit that generates and outputs a current having a negative temperature characteristic with respect to a tail current supplied from a tail current source to the first and second P-channel MOS transistors;
An input offset voltage correction current generation circuit for supplying an input offset voltage correction current to each of the first and second P-channel MOS transistors,
The operational amplifier, wherein the input offset voltage correction current generation circuit is configured to be capable of adjusting the output of the input offset voltage correction current based on the output current of the negative temperature characteristic current generation circuit. The first and second P-channel MOS transistors are provided such that sources are connected to each other and a tail current is supplied to the connection point from the tail current source,
The negative temperature characteristic current generation circuit includes a current mirror circuit including first to third N channel MOS transistors for generating negative temperature characteristic current, and includes first to third N for generating negative temperature characteristic current. The gates of the channel MOS transistors are connected to each other and connected to the drain of the first N channel MOS transistor for generating the negative temperature characteristic current, and connected to the drain of the first N channel MOS transistor for generating the negative temperature characteristic current. The tail current source is connected, and the source of the first N channel MOS transistor for generating the negative temperature characteristic current is connected to the source of the second N channel MOS transistor for generating the negative temperature characteristic current through the first resistor. The sources are both connected to a negative power supply through a second resistor, the first resistor having a negative temperature characteristic, while The source of the third N-channel MOS transistor for the negative temperature characteristic current generation is connected to the negative power supply,
A current having a negative temperature characteristic with respect to the tail current can be output from the drain of the third N-channel MOS transistor for generating the negative temperature characteristic current,
A tail current supply current mirror circuit is provided between the sources of the first and second P-channel MOS transistors and the drain of the second N-channel MOS transistor for generating the negative temperature characteristic current. Enables tail current to be supplied to the second P-channel MOS transistor;
The input offset voltage correction current generation circuit includes a current mirror circuit including first to third correction channel generation P-channel MOS transistors, and the first to third correction channel generation P-channel MOS transistors. Is connected to the drain of the first P-channel MOS transistor for generating a correction current, and the source of the first P-channel MOS transistor for generating a correction current is connected through a third resistor. The source of the second P-channel MOS transistor for generating the correction current is passed through the first variable resistor, and the source of the third P-channel MOS transistor for generating the correction current is passed through the second variable resistor. And both are connected to the positive power source,
The drain of the first P-channel MOS transistor for generating the correction current is drained to the drain of the third N-channel MOS transistor for generating the negative temperature characteristic current, and the drain of the second P-channel MOS transistor for generating the correction current is The drain of the first P-channel MOS transistor is connected to the drain of the third P-channel MOS transistor for generating correction current, and the drain of the second P-channel MOS transistor is connected to the first and second P-channel MOS transistors, respectively. 2. The operational amplifier according to claim 1, wherein the input offset voltage can be zero-adjusted by adjusting a resistance value of the variable resistor.

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