JP5719682B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having means for avoiding destruction due to overvoltage.

  2. Description of the Related Art Conventionally, there is known a semiconductor integrated circuit equipped with an ESD / EOS protection circuit that prevents destruction of an internal circuit against ESD (Electrostatic Discharge) / EOS (Electrical Overtress).

  Although ESD and EOS are the same in that an excessive voltage that cannot be normally input is input, the phenomenon is classified as “current application” for ESD and “voltage application” for EOS. In other words, ESD does not have a low-resistance path through which current should flow, and as a result, the voltage rises and the device is destroyed. On the other hand, EOS is a phenomenon that causes breakdown because a high voltage is continuously applied in the order of several hundreds msec.

  FIG. 7 is a diagram showing a conventional example of an ESD / EOS protection circuit.

  Here, a power supply terminal 51, an input terminal 52, a ground terminal 53, an inverter 54 composed of a P-channel MOS transistor 541 and an N-channel MOS transistor 542, a resistor 55 that connects the input terminal 52 and the input portion 54 a of the inverter 54, A first protection element 56 disposed between the input terminal 52 and the ground terminal 53, and a second protection element 57 disposed between the input portion 54a of the inverter 54 and the ground terminal 53 are shown. Yes.

  A power supply of + 3.3V is connected to the power supply terminal 51 with reference to the ground terminal 53, and the inverter 54 operates at this + 3.3V. The inverter 54 is a protected element that should be protected from being destroyed by ESD / EOS. Here, the withstand voltage of the input portion 54a of the inverter 54 is set to + 14V. However, since ESD is a high voltage but the application time is as short as several hundred nsec, it is assumed that the withstand voltage against ESD of the input portion 54a of the inverter 54 is + 18V.

  Here, it is assumed that the first protection element 56 is turned on at + 15V, and the second protection element 57 is turned on at + 12V.

  Here, it is assumed that ESD is applied to the input terminal 52. Although a high voltage is applied when ESD is applied, since the first protection element 56 is turned on at + 15V and a high current flows, + 18V is not applied to the input portion 54a of the inverter 54 which is a protected circuit. Is not destroyed.

  Unlike ESD, EOS is applied with a constant voltage, and a relatively low voltage is applied as compared with ESD, but the application time may be as long as several hundred msec. Here, if + 14V is applied to the input terminal 52 as EOS, the current due to the applied voltage of EOS flows through the resistor 55 and passes through the second protection element that is turned on at + 12V. At this time, a voltage drop is generated by the resistor 55, and a voltage lower than + 14V is applied to the input portion 54a of the inverter 54. At this time, the inverter 54 is prevented from being broken.

  However, in the configuration of FIG. 7, the resistor 55 is disposed between the input terminal 52 and the input portion 54 a of the inverter 54. The resistor 55 requires a resistance value of about 200Ω, for example. Furthermore, there is a parasitic capacitance in the inverter 54 and the like. For this reason, when the signal input to the input terminal 52 becomes high speed in normal operation, a signal delay may occur due to the parasitic capacitance caused by the resistor 55 and the inverter 54 and the like, which may adversely affect the signal characteristics.

  Patent Document 1 discloses a configuration in which the gate and drain of an inverter serving as a protected circuit are connected by an electrostatic protection element, and the electrostatic protection element is interposed between the gate and drain of an N-channel MOS transistor constituting the inverter. Has been proposed. In this proposal, a current is passed through an N-channel MOS transistor that constitutes an inverter, which is a protected element, during protection operation. Especially in the case of a small and weak protected element, if a current is intentionally passed, There is a risk that it will be destroyed, and it is difficult to design with sufficient margins, which can lead to difficult design.

JP 2008-288251 A

  SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit that protects against overvoltage application while avoiding adverse effects on normal operation.

The semiconductor integrated circuit of the present invention that achieves the above object is as follows.
Input circuit having first and second input nodes connected to first and second terminals and an output node for outputting a signal corresponding to a potential difference between the first and second input nodes to an internal circuit When,
A first means for controlling the potential of the output node of the input circuit;
A first switch that is interposed between the second input node of the input circuit and the second terminal, and that maintains the connection between the second input node and the second terminal in a normal state; And
When the first overvoltage is applied to the first terminal and the potential of the first terminal rises, the first switch releases the connection between the second terminal and the second input node, and the first terminal The first means performs the first protection operation for increasing the potential of the output node to limit the increase in potential difference between the first input node and the output node.

  In the semiconductor integrated circuit of the present invention, when an overvoltage is applied, the connection between the input circuit and the second terminal is released by the first switch, so even if an overvoltage is applied to the first terminal, Current due to overvoltage is prevented from flowing to the second terminal via the input circuit. Further, when an overvoltage is applied to the first terminal, the first means raises the potential of the output part of the input circuit, so that the current flowing from the input part to the output part through the input circuit is also suppressed. According to the semiconductor integrated circuit of the present invention, destruction due to overvoltage is thus prevented.

Here, the semiconductor integrated circuit of the present invention is
Between the first and second terminals, when the second overvoltage is applied to the first terminal, the second protection operation is controlled to release the overcurrent caused by the second overvoltage to the second terminal. , Comprising overvoltage detection means for detecting application of the first overvoltage to the first terminal,
Providing overvoltage protection means for suppressing the second protection operation when the overvoltage detection means detects application of the first overvoltage;
When the overvoltage detection means detects the application of the first overvoltage, the first protection operation by the first switch and the first means is provided by supplying a detection signal to the first switch and the first means. It is preferable that the semiconductor device perform the above.

  In this case, the overvoltage detection means generates a detection signal that rises when the first overvoltage is applied to the first terminal. The first means outputs the detection signal to the output node. By supplying, the potential of the output node may be increased.

In the semiconductor integrated circuit of the present invention, an input circuit, a gate to the first input node, it may be constituted by a MOS transistor having a drain connected to the output node.

  According to the present invention described above, it is possible to configure a semiconductor integrated circuit in which protection against overvoltage application is achieved while avoiding adverse effects on signal characteristics during normal operation.

1 is a circuit block diagram of a first embodiment of a semiconductor integrated circuit according to the present invention. It is a circuit diagram of a second embodiment of the semiconductor integrated circuit of the present invention. FIG. 3 is a diagram showing the potential of each part when +14 V EOS is applied to the input terminal of the semiconductor integrated circuit shown in FIG. 2. FIG. 3 is a diagram showing the potential of each part of the input inverter when + 14V EOS is applied to the input terminal of the semiconductor integrated circuit shown in FIG. 2. It is the figure which showed GGNMOS by the symbol. It is the figure which showed the characteristic of GGNMOS. It is a figure which shows the prior art example of an ESD / EOS protection circuit.

  Embodiments of the present invention will be described below.

  FIG. 1 is a circuit block diagram of a first embodiment of a semiconductor integrated circuit according to the present invention.

  The semiconductor integrated circuit 10 shown in FIG. 1 includes an input circuit 13 having an input section 13a connected to the first terminal 11, first means 16 connected to the output section 13b of the input circuit 13, and an input. A first switch 15 connected between the circuit 13 and the second terminal 12 is provided. Further, in the present embodiment, the first means 16 is connected between the output unit 13 b of the input circuit 13 and the second terminal 12. The first switch 15 maintains a connection between the input circuit 13 and the second terminal 12 in a normal state, and releases the connection when an overvoltage input is detected.

  The first means 16 raises the potential of the output unit 13b when an overvoltage is applied to the first terminal 11, and reduces the potential difference with the input unit 13a to prevent the input circuit 13 from being destroyed.

  Further, the semiconductor integrated circuit shown in FIG. 1 is provided with overvoltage protection means 14 between the first terminal 11 and the second terminal 12. The overvoltage protection means 14 is means for protecting the input circuit 13 from ESD. The overvoltage protection means 14 includes a protection element 141 and a detection means 142 connected between the first terminal 11 and the second terminal 12. The detection unit 142 detects application of EOS to the first terminal 11. The detection means 142 is connected to the protection element 141, the first switch 15, and the first means 16, and a control signal generated when the detection means 142 detects the application of EOS is connected to the protection element 141 and the first switch 16. Switch 15 as well as the first means 16.

  When the protection element 141 is supplied with a control signal from the detection means 142, its operation is controlled. Accordingly, even when the turn-on voltage of the first protection element 141 is lowered, it is possible to prevent the protection element 141 from being destroyed when EOS having a long duration is applied.

The detecting means 142 detects an overvoltage applied to the first terminal 11 and
(1) Generate a signal for controlling the protection element 141 to suppress the operation of the protection element 141;
(2) Generate a signal for controlling the first switch 15 to disconnect the input circuit 13 and the second terminal 12;
(3) The destruction of the input circuit 13 is avoided by controlling the first means 16 and applying a voltage to the output unit 13b of the input circuit 13 to reduce the potential difference with the input unit 13a.

  Here, the first means 16 may apply a voltage to the output unit 13b of the input circuit 13 to reduce the potential difference from the input unit 13a. As a method of applying the voltage to the output unit 13b, for example, an applied overvoltage May be used, and another voltage may be used without using the overvoltage.

  In the semiconductor integrated circuit according to the first embodiment, when an overvoltage is applied to the first terminal 11, the connection between the input circuit 13 and the second terminal 12 is released by the first switch 15, and further the input Since a voltage is applied to the output unit 13b so that the potential difference between the input unit 13a and the output unit 13b of the circuit 13 is reduced, the input circuit 13 is prevented from being destroyed.

  Further, in the semiconductor integrated circuit 10 of the first embodiment, a protective resistor (see the resistor 55 shown in FIG. 7) is not required between the first terminal 11 and the input circuit 13, and the operation by the resistor is performed in the normal operation. There is no reduction in speed.

  FIG. 2 is a circuit diagram of a second embodiment of the semiconductor integrated circuit of the present invention.

  The semiconductor integrated circuit 20 is provided with a power supply terminal 21, an input terminal 22, and a ground terminal 23. Here, an input inverter 24 as a protected circuit is shown. The input inverter 24 includes a P-channel MOS transistor 241 and an N-channel MOS transistor 242, the source of the P-channel MOS transistor 241 is connected to the power supply terminal 21, and the drain of the P-channel MOS transistor 241 and the N-channel MOS transistor 242 The drain is connected. The source of the N channel MOS transistor 242 is connected to the drain of another N channel MOS transistor 29, and the source of the N channel MOS transistor 29 is connected to the ground terminal 23. The gates of the P channel MOS transistor 241 and the N channel MOS transistor 242 are connected to each other and to the input terminal 22. A connection point between the drains of the P-channel MOS transistor 241 and the N-channel MOS transistor 242 becomes an output portion 24 b of the inverter 24.

  Here, a protection circuit 25 is disposed between the input terminal 22 and the ground terminal 23. The protection circuit 25 includes two N-channel MOS transistors 251 and 252 connected in series. The drain of the N-channel MOS transistor 251 is connected to the input terminal 22, and the source of the N-channel MOS transistor 251 and the N-channel MOS transistor The drains of the transistors 252 are connected to each other, and the source of the N-channel MOS transistor 252 is connected to the ground terminal 23. The gate of the N channel MOS transistor 252 is also connected to the ground terminal 23. The connection destination of the gate of the N-channel MOS transistor 251 will be described later.

  The semiconductor integrated circuit shown in FIG. 2 is further provided with a detection circuit 26. The detection circuit 26 includes an N-channel MOS transistor 261 and a resistor 262. The drain of the N-channel MOS transistor 261 is connected to the input terminal 22, the source and gate are connected to one end of the resistor 262, and the other end of the resistor 262 is connected to the ground terminal 23. Further, the gate of the N-channel MOS transistor 251 constituting the protection circuit 25 is connected to a connection node 26 a between the N-channel MOS transistor 261 and the resistor 262 constituting the detection circuit 26.

  The semiconductor integrated circuit 20 is further provided with another inverter 27 and an N-channel MOS transistor 28. The inverter 27 includes a P channel MOS transistor 271 and an N channel MOS transistor 272. The source of the P channel MOS transistor 271 is connected to the power supply terminal 21, and the drains of the P channel MOS transistor 271 and the N channel MOS transistor 272 are connected to each other. The source of the N-channel MOS transistor 272 is connected to the ground terminal 23. Further, the gate of the P-channel MOS transistor 271 and the gate of the N-channel MOS transistor 272 are connected to each other to form an input part 27a of the inverter 27. The input part 27a is an N-channel MOS transistor 261 that constitutes the detection circuit 26. And the resistor 262 are connected to a connection node 26a. The output 27 b of the inverter 27, that is, the connection node between the drains of the P channel MOS transistor 271 and the N channel MOS transistor 272 is connected to the gate of the N channel MOS transistor 29.

  Further, the drain and source of the N-channel MOS transistor 28 are connected to a connection node 26 a between the N-channel MOS transistor 261 and the resistor 262 of the detection circuit 26 and an output part 24 b of the input inverter 24. Are also connected to a connection node 26 a between the N-channel MOS transistor 261 and the resistor 262 of the detection circuit 26.

  Here, when the semiconductor integrated circuit 20 according to the second embodiment of the present invention shown in FIG. 2 is compared with the semiconductor integrated circuit 10 according to the first embodiment shown in FIG.

  The input terminal 22 and the ground terminal 23 shown in FIG. 2 correspond to the first terminal 11 and the second terminal 12 shown in FIG. 1, respectively. The input inverter 24 corresponds to the input circuit 13. Further, the protection circuit 25 corresponds to the protection element 141, and the detection circuit 26 corresponds to the detection unit 142. Therefore, the combination of the protection circuit 25 and the detection circuit 26 corresponds to the overvoltage protection means 14. Further, the N channel MOS transistor 29 corresponds to the first switch 15, and the combination of the inverter 27 and the N channel MOS transistor 28 corresponds to the first means 16.

  Hereinafter, the operation of the semiconductor integrated circuit 20 shown in FIG. 2 will be described.

  3 is a diagram showing the potential of each part when + 14V EOS is applied to the input terminal of the semiconductor integrated circuit shown in FIG. 2, and FIG. 4 is a diagram showing + 14V EOS at the input terminal of the semiconductor integrated circuit shown in FIG. It is the figure which showed the electric potential of each part of an input inverter when is applied.

  Here, as a precondition, it is assumed that a power supply of + 3.3V is connected to the power supply terminal 21, and the semiconductor integrated circuit 20 operates with a power supply of + 3.3V. Further, as in the case of the conventional example described with reference to FIG. 7, it is assumed that the withstand voltage of the input unit 24a of the input inverter 24 is + 18V when ESD is applied and + 14V when EOS is applied. The voltage applied as EOS to the input terminal 21 is + 14V. In this semiconductor integrated circuit 20, the protection circuit 25 has a turn-on voltage of +15 V by adjusting the gate of the N-channel MOS transistor 251, and the N-channel MOS transistor 261 constituting the detection circuit 26 has a GGNMOS configuration and is turned on. Assume that the voltage is + 13V.

  Here, with reference to FIGS. 3 and 4, the GGNMOS configuration will be described.

  FIG. 5 is a diagram showing GGNMOS as a symbol, and FIG. 6 is a diagram showing characteristics of GGNMOS.

  The GGNMOS is an N-channel MOS transistor whose gate is connected to the ground, and is configured to flow an electrostatically applied current by a parasitic bipolar operation formed at the drain-P substrate-source of the N-channel MOS transistor.

  As shown in FIG. 6, this GGNMOS is a snapback in which when the drain-source voltage reaches a certain turn-on voltage, the parasitic bipolar transistor is turned on. It has a characteristic called. The N-channel MOS transistor 261 having the GGNMOS structure of the semiconductor integrated circuit 20 shown in FIGS. 2 and 3 is turned on at + 14V, and once turned on, it is lowered to a hold voltage of + 8V.

  Returning to FIG. 2 and FIG. 3, the description will be continued.

  Here, when ESD is applied to the input terminal 22, the protection circuit 28 is turned on at + 15V, so that the voltage exceeding + 18V is not applied to the input section 24a of the input inverter 24, which is a protected element, and the input inverter 24 Is not destroyed.

  When + 14V EOS is applied to the input terminal 22, the protection circuit 25 remains off at + 14V. On the other hand, the detection circuit 26 adopts a GGNMOS configuration as the N-channel MOS transistor 261 and is turned on at + 13V, and the hold voltage is lowered to 8V by snapback. By this turn-on, a current flows through the N-channel MOS transistor 261 and the resistor 262, so that the connection node 26a between the N-channel MOS transistor 261 and the resistor 262 rises to + 6V. This + 6V is applied to the input part 27a of the inverter 27. Since this inverter 27 is driven by a power supply of + 3.3V, the input part 27a becomes H level and the output part 27b becomes L level. This L level voltage is applied to the gate of the N-channel MOS transistor 29, the N-channel MOS transistor 29 is turned off, and the N-channel MOS transistor 28 is diode-connected and turned on.

  Here, referring to FIG. 4, the path from the connection node 26a between the N channel MOS transistor 261 and the resistor 262 of the detection circuit 26 to the ground, that is, the connection node 26a → the N channel MOS transistor 28 → the input inverter 24 → N. The channel MOS transistor 29 → ground path will be described.

N-channel MOS transistor 28 is diode-connected and is turned on. Veos = + 14V is applied to the input section 24a of the input inverter 24, and the N-channel MOS transistor 242 constituting the input inverter 24 is turned on. An L level voltage is inputted to the gate of the N channel MOS transistor 29, and the N channel MOS transistor 29 is turned off. Therefore, no current can flow through the N-channel MOS transistor 29, and the N-channel MOS transistor 242 constituting the N-channel MOS transistor 28 and the input inverter 24 reduces the drain-source voltage _VDS to reduce the current. It works so as not to flow. Here, it is assumed that the potential difference is V _DS = 1V. At this time, the voltage applied to the input section 24a of the input inverter 24 is 10.7V on the P-channel MOS transistor 241 side and 10V on the N-channel MOS transistor 242 side. Therefore, a protective resistor (see the resistor 55 shown in FIG. 7) is not required between the input terminal 22 and the input portion 24a of the input inverter 24.

  Further, according to the semiconductor integrated circuit 20, there is no portion where a high potential difference that causes destruction occurs in any part, and there is no fear of destruction.

  Further, a Zener diode may be employed in place of the protection circuit 25 and the N-channel MOS transistor 261 that constitute the detection circuit 26 shown in FIG.

  According to the semiconductor integrated circuit 20 described above, it is possible to avoid adverse effects on normal operation by eliminating the protective resistance between the input terminal 21 and the input inverter 24 which is a non-protection circuit, and the ESD / EOS is reduced. It is prevented from being destroyed when applied.

  As for the output of the input circuit, a voltage is applied to reduce the potential difference with the input terminal when EOS is applied, but the potential is lower than that of the input terminal. Therefore, it is not necessary to arrange a circuit for raising the potential at the output node of the next stage circuit to which the output of the input circuit is connected. On the other hand, even if the circuit of the present invention is added to the next-stage circuit, it functions similarly to EOS and ESD and does not adversely affect the characteristics.

DESCRIPTION OF SYMBOLS 10,20 Semiconductor integrated circuit 11 1st terminal 12 2nd terminal 13 Input circuit 13a, 24a, 27a, 54a Input part 13b, 24b, 27b Output part 14 Overvoltage protection means 15 1st switch 16 1st means 21 , 51 Power supply terminal 22, 52 Input terminal 23, 53 Ground terminal 24 Input inverter 25 Protection circuit 26 Detection circuit 26a Connection node 27, 54 Inverter 28, 29, 242, 251, 252, 261, 272, 542 N-channel MOS transistor 55 , 262 Resistor 56 First protection element 57 Second protection element 141 Protection element 142 Detection means 241, 271, 541 P-channel MOS transistor

Claims (4)

Input circuit having first and second input nodes connected to first and second terminals and an output node for outputting a signal corresponding to a potential difference between the first and second input nodes to an internal circuit When,
First means for controlling the potential of the output node of the input circuit;
A first switch interposed between the second input node of the input circuit and the second terminal and maintaining a connection between the second node and the second terminal in a normal state; Have
When a first overvoltage is applied to the first terminal and the potential of the first terminal rises, the first switch releases the connection between the second terminal and the second input node The first means performs a first protection operation for increasing the potential of the output node to limit an increase in potential difference between the first input node and the output node. Integrated circuit. Control of a second protection operation that releases an overcurrent due to the second overvoltage to the second terminal when a second overvoltage is applied to the first terminal between the first and second terminals And overvoltage detection means for detecting application of the first overvoltage to the first terminal,
Providing overvoltage protection means for suppressing the second protection operation when the overvoltage detection means detects application of the first overvoltage;
By supplying a detection signal to the first switch and the first means when the overvoltage detection means detects the application of the first overvoltage, the first switch and the first means by the first means. 2. The semiconductor integrated circuit according to claim 1, wherein one protection operation is performed.   The overvoltage detection means generates the detection signal that rises when the first overvoltage is applied to the first terminal, and the first means sends the detection signal to the output node. 3. The semiconductor integrated circuit according to claim 2, wherein the potential of the output node is raised by supplying the same. Wherein the input circuit, the first input node to the gate, a semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that the drain to the output node is constituted by the MOS transistors connected .

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