JP5750924B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that processes an input image mounted on an image forming apparatus (such as a copying machine, a printer, or a multifunction machine) into print output data. Even if bit expansion is performed in the processing process, an error occurs. The present invention relates to an image processing apparatus capable of suppressing an increase in memory capacity required for halftone processing by diffusion.

The image quality required for image forming apparatuses such as copiers, printers, and multifunction machines has been increasing year by year as colorization and multi-functionality increase.
Along with the progress of high image quality, various image processing techniques for performing bit expansion in the process of processing a processing target image into print output data have been proposed and implemented in various forms.
In data processing for print output, for example, the processing shown in FIG. 14 is common. In the processing process shown in FIG. 6, scanner input or PDL (page description language) data input from a host machine is performed, and an image generated through data processing on the input side is a target of print output.
In many cases, the data to be printed out is 8 bits for each of RGB, and color conversion 23 ′, printer γ correction 24 ′, halftone processing 25 ′, rendering & engine output are performed on the image data as output processing. Print output is performed through the process 26 '.

In the example of FIG. 14, the printer γ correction 24 ′ expands from 8 bits to 10 bits, and the downstream halftone processing 25 ′ requires 12 bits for internal processing (see FIG. 5, which will be described later), and stores the intermediate product. This leads to an increase in the cost, resulting in an increase in cost.
Patent Document 1 (Japanese Patent Laid-Open No. 2004-096709) can be cited as a conventional technique proposed for the purpose of reducing the memory capacity in response to such an increase in memory.
Japanese Patent Application Laid-Open No. 2004-133867 discloses that a small part of a generated quantization error is bit-coupled to the next input image for the purpose of reducing the required buffer memory capacity while reducing the influence of calculation errors during error diffusion processing. By doing so, it is described that it becomes unnecessary to hold a small part of the quantization error in the buffer memory.

However, the reduction in the capacity of the buffer memory in the above-described conventional example causes a problem of reducing the image quality because error diffusion is performed only on the upper bits of the quantization error and the lower bits are excluded.
The present invention takes into account the problems arising in the above-described conventional technique proposed to suppress the increase in the memory capacity of the buffer required for error diffusion in halftone processing, which is caused by bit expansion in the data processing process for print output. The purpose of this is to achieve both maintaining high image quality by suppressing the lower bits and reflecting them in the quantization process and suppressing enlargement of the memory capacity of the buffer.

The present invention adds the error data generated in the surrounding pixels and diffused to the processing target pixel to the multi-value data of the processing target pixel in the image composed of pixels of the multi-value data, and then compares it with the threshold value. Quantization means for outputting small value data, and a quantization error calculation means for calculating an error due to quantization by comparing the small value data quantized by the quantization means with the original multivalue data And weighting means for giving a weight for diffusing the error calculated by the quantization error calculating means to a plurality of target peripheral pixels, and the weighting means at the time of quantization error diffusion processing of the current line the error data is diffused in accordance granted weighting, for each pixel, and error addition means for adding the error data accumulated until a quantization error diffusion processing on the current line, depending on the error addition means In order to add the calculated error data to the input data to the quantization means of the pixel to be processed, the image processing apparatus includes a buffer that stores the pixel data according to the pixel arrangement in the processing order. Data separation means for separating the calculated error data of the next line into upper bits and lower bits, and error data of the lower bits separated by the data separation means at the time of quantization error diffusion processing of the current line for each pixel Are added to the error data of the lower bit of the next line accumulated up to the quantization error diffusion processing of the current line, and the lower bit error accumulation means for outputting a carry signal, and the upper bit separated by the data separation means Upper bit error data calculating means for adding a carry signal output from the lower bit error accumulating means to bit error data, and provided in the buffer The upper bit error data calculated and the next line error data storage unit for storing the error data of the upper bits calculated by means quantization error diffusion process of the error data stored in the next line error data storing unit current line When applying to the above, a left shifter for adjusting to the original number of bits is provided , and the data separating unit, the next line error data storage unit, and the error adding unit are separated by the following relational expression, that is, the data separating unit. The number of higher order bits ≦ the number of bits of error data stored in the next line error data storage unit <the number of bits of error data separated by the data separation means .

  According to the present invention, it is possible to suppress an increase in the memory capacity of a buffer required for error diffusion in halftone processing, which is caused by bit expansion in a data processing process for print output, and to reduce the quantization error diffusion target. By including bits, it is possible to maintain high image quality without losing gradation.

1 is a diagram illustrating an outline of a configuration of an MFP as an embodiment of the present invention. It is a block diagram which shows the outline | summary of the control system of MFP (FIG. 1) comprised under the controller which has a processing function of image data. It is a figure explaining the conversion characteristic of (gamma) conversion. It is a figure explaining the conversion characteristic of (gamma) conversion when the output bit number in FIG. 3 is expanded further. It is a figure which shows the basic composition of a halftone processing system with error diffusion. It is a table | surface which shows the relationship between the input of quantization (refer FIG. 5) which makes 12 bit data-> 2 bit data an example, and an output. It is a table | surface which shows the relationship between the input and output of inverse quantization (refer FIG. 5) which makes 2bit data-> 12bit data an example. It is a schematic diagram explaining the error diffusion performed by weighting in the example. FIG. 6 is a diagram illustrating a circuit configuration example of weighting and error storage / output in a halftone processing system (FIG. 5). It is a figure which shows the structural example of the halftone processing system with error diffusion which concerns on embodiment of this invention. It is a figure which shows the circuit structural example of the process in which the error added to the following pixel is output from the weighting of a halftone processing system (FIG. 10). FIG. 12 is a diagram showing details of a circuit configuration example in the process of storing data from the bit separation of FIG. 11 to the line buffer. 13 is a table showing an operation example in the circuit configuration of FIG. 12 in a data state of a flow sequentially performed in units of pixels. It is a figure which shows the process of the data processing for print output generally performed conventionally.

Embodiments of an image processing apparatus according to the present invention will be described below with reference to the accompanying drawings.
As an embodiment of the image processing apparatus according to the present invention, a multifunction peripheral (MFP) will be described below as an example.
The MFP according to the present embodiment receives a scanner input or print data from a host machine, and prints out according to output conditions instructed by a print request based on image data generated through data processing on the input side. Data processing is performed.
In halftone processing performed in the process of data processing for print output, an image composed of pixels of input multi-value data (here 10 bits) is processed into low-value data (here 2 bits) by quantization and output. Used. An error generated in each pixel by this quantization is diffused to peripheral pixels so that the image quality of the entire output image is maintained.

In the present invention, in order to suppress the enlargement of the memory capacity used for error diffusion processing, a method of separating the lower bits of the error data to be diffused and reflecting it in the quantization processing of the subsequent pixels is adopted. This is the gist of the invention.
However, the quantization process with error diffusion performed as a halftone process is an existing technology in the MFP. Therefore, first, an outline of the configuration of the MFP on which the present embodiment is based will be described with reference to FIGS. 1 and 2.
FIG. 1 is a diagram showing an outline of the configuration of an MFP as an embodiment of the present invention.
FIG. 2 is a block diagram showing an outline of the control system of the MFP (FIG. 1) configured under the controller having the image data processing function.

As shown in FIG. 1, the MFP 1 includes a controller board 2b, a scanner unit 3, a plotter unit 4, and an operation unit 5.
The host 7 is an external machine such as a personal computer (PC) that issues a print request or the like, and is connected to the controller board 2b via a communication unit.
The scanner unit 3 reads the document surface by main / sub two-dimensional scanning, converts the light amount of pixels arranged in accordance with the scanning line into a corresponding electrical signal, and outputs the signal to the controller board 2b. The scanner unit 3 may include an automatic document feeder (ADF) and may have a function of automatically reading a plurality of documents. Further, the conversion method of an original image into an electrical signal may be either a CCD (Charge Coupled Devices) method or a CIS (Contact Image Sensor) method.

The plotter unit 4 converts the image read by the scanner unit 3 or image data input from the host 7 or the like into CMYK (+ α) data that is a color component color through processing of print output data to be described later. Used to print on a recording medium (paper) and output paper. The printing method may be either an inkjet method or an electrophotographic method.
The operation unit 5 includes an input unit such as a key and a display, and accepts operation condition setting and command input such as operation mode setting by the user, and also notifies the user of device status and input screens. Etc. are displayed.
The controller board 2b is a unit on which elements constituting the controller 2 shown in FIG. 2 to be described later are mounted, and controls copy processing and print processing. In copying, the RGB multi-valued image input from the scanner unit 3 is converted into a format that can be output by the plotter unit 4. Additional functions such as changing the page order, accumulating images, and editing images when printing are implemented. Note that processing of image data for print output, particularly an embodiment of halftone processing characterizing the present invention will be described in detail later.

The control system shown in FIG. 2 is configured under the controller 2 having an image data processing function, and the scanner unit 3, the plotter unit 4, and the operation unit 5 are each controlled by the controller 2 under the control of the controller 2. The printer engine control 42 and the operation unit I / F 52 operate.
Here, the image data processing function of the controller 2 has a gist of image data processing for print output, and therefore the processing flow mainly for processing image data at the time of a copy request and at the time of a print request from the host 7. Since only the elements related to are illustrated, the description will be made based on the drawings.

The scanner image input unit 21 takes in RGB multi-value data input from the scanner unit 3. When the image signal is received as an analog signal, it is converted into digital data. Correction of variations in photoelectric conversion elements of the image, correction of differences in physical positions of the elements, fluctuations in illumination, and the like are performed.
The scanner image processing unit 22 performs processing for canceling the scanner characteristics and converts the data into a standard RGB data format.
The color converter 23 converts RGB multi-value data input from the scanner image processing unit into CMYK multi-value data.
The γ conversion 24 corrects the density characteristic of the image in order to cancel the deterioration of the image quality due to the nonlinearity of the output characteristic of the printer engine (plotter). As in the embodiment described later, when the number of output bits from the γ conversion 24 is made larger than the number of input bits to the γ conversion 24 (for example, 8 bits → 10 bits), it may lead to high image quality (described later, FIG. 3). And the description of 4).

The halftone processing 25 is a γ conversion 24 for the CMYK multivalued data converted by the color conversion 23, for example, 10-bit multivalued data, which is input and used for output by the plotter unit 4 by quantization. Convert to small value data of about 8 bits. The halftone processing 25 is based on processing unique to the present invention, and will be described in detail later.
The printer image output unit 26 transmits the image data subjected to the halftone processing 25 to the plotter unit 4 in the order and timing according to the specifications of the plotter unit 4.
The host I / F 72 receives a print request issued by a host 7 such as a PC, and stores it in a memory (not shown) for managing jobs.
The print image processing 27 analyzes PDL (page description language) data received as a print request and converts it into RGB multi-value data. Note that the image data for print output after color conversion 23 is processed in the same manner as the image data input by the scanner described above.
The CPU 20 manages various jobs that are requested to be processed and input to the MFP, and controls the operation of the entire control element in the controller 2.

By the way, the controller 2 includes hardware such as the CPU 20, a ROM (not shown) for storing a program (software) driven by the CPU 20, and a RAM (not shown) used as a work memory when the program is operated. The computer can be configured.
When the controller 2 is configured by a computer, for example, when processing image data for print output, a program for functioning as each of the above-described processing units or the like for executing this processing is recorded and installed in a ROM, and this program is The processing unit and the like are realized by being driven by a computer.
The medium for recording the program is not limited to ROM, and various storage media including disk types such as HDD (hard disk), CD-ROM, and MO (Magneto Optical Disk) can be used.

“Extended number of bits”
In the data processing for print output, it is necessary to store data so as not to cause deterioration of image quality, and therefore, it may be necessary to extend the number of bits.
Taking γ conversion as an example, in γ conversion, input density information is converted using a non-linear table, thereby performing processing to counteract deterioration in image quality due to non-linearity in engine output characteristics. .
FIG. 3 is a diagram for explaining the conversion characteristics of γ conversion. The γ conversion characteristic illustrated in the figure is a case where input 8 bits and output 8 bits (maximum value 255) are converted. If the nonlinearity of the γ characteristic is strong, the gradation of the input is lost as shown in the enlarged view. It becomes cause. That is, the output value becomes the same for each different input value (three points in the enlarged view are the same output value), resulting in a reduction in the number of densities that can be expressed.

Therefore, the number of output bits is expanded.
FIG. 4 is a diagram for explaining the conversion characteristics of γ conversion when the number of output bits in FIG. 3 is further expanded. In the figure, a state in which the input is 8 bits and the output is 10 bits (maximum value 1023) is shown. By expanding the number of output bits, a reduction in gradation can be suppressed even if strong nonlinearity exists. That is, for each different input value, the output value is different (the output values at three points in the enlarged view change smoothly), resulting in an increase in the number of densities that can be expressed.
In this way, when higher image quality is desired, characteristic data is saved by extending the output bits in table processing such as γ conversion, and deterioration of image quality can be prevented.
Here, the case where the output bit is expanded in the γ conversion is shown, but it is also conceivable that the number of bits is further expanded in the upstream image processing. The number of bits of the image data becomes larger.

[Halftone processing]
A halftone process for quantizing multivalued data of an image to be processed into low-value data for print output, that is, converting into multi-level data represented by low-value data used in the plotter unit 4 Will be described in detail.
Here, in halftone processing, the error caused by quantization is diffused to surrounding pixels, and the error diffusion method that adds the diffused error to the target pixel for quantization processing is used to mitigate the effects of quantization errors. Adopt the method to do.
FIG. 5 is a diagram showing a basic configuration of a halftone processing system with error diffusion.
As shown in the figure, the halftone processing system includes each element of addition 251, quantization 252, inverse quantization 253, addition 254, weighting 255, and error storage / output 256.

Here, the pixels of the image data that have been converted to 10 bits through the γ conversion 24 are processed for each pixel in the arrangement order. Also, the input 10 bits are reduced to 2 bits by quantization and output, but at this time, the quantization error is diffused.
When the image data is input, the addition 251 adds an error (a method for calculating the error and the like described later) generated in the peripheral pixels of the pixel to the data value of the processing target pixel. The data after the addition is 12-bit data.
Next, the quantization 252 performs a quantization process on the input data to which the error generated in the surrounding pixels by the addition 251 is added. This quantization process has a threshold value corresponding to (number of output gradations−1), and determines output data by comparing with the threshold value.
FIG. 6 is a table showing the relationship between the input and output of quantization (see FIG. 5) taking 12 bit data → 2 bit data as an example. In the example shown in the figure, 12-bit data is output as 4-level (2-bit) data by three-stage threshold processing.
The quantization 252 outputs the result of the quantization process to a processing unit (printer image output unit 26 in the example of FIG. 2) subsequent to the data processing for print output.

Next, as the internal processing of the halftone processing 25, the inverse quantization 253 performs inverse quantization on the quaternary (2-bit) data output from the quantization 252; that is, processing to return to 12-bit data before quantization.
FIG. 7 is a table showing the relationship between the input and output of inverse quantization taking 2 bit data => 12 bit data as an example. As shown in the figure, since the inverse quantization is performed on the 4-value (2-bit) output data of the quantization 252, the output obtained as a result of the processing of the inverse quantization 253 is naturally the input data to the quantization 252. Is never saved.
Next, the adder 254 adds the input data to which the error generated in the surrounding pixels before the quantization 252 is added as the + input, and the output data of the inverse quantization 253 as the -input, and adds these data. . By this addition, data representing a quantization error (hereinafter simply referred to as “error data”) is obtained. In the example of FIG. 5, the error data is output in 12 bits.

Next, the weighting 255 performs a process of diffusing error data generated by the process of the pixel to be processed, which is output from the addition 254, to surrounding pixels. In this diffusion process, diffusion is performed with a predetermined weight determined according to the position of each unprocessed peripheral pixel with respect to the pixel (also referred to as “target pixel”).
FIG. 8 is a schematic diagram for explaining error diffusion performed by weighting. According to the processing order indicated by arrows in the figure, that is, according to the line direction and the line arrangement order of the first line, the second line,... , With respect to the pixel of interest that is the target of the current quantization process, three unprocessed pixels in the current line being processed and four unprocessed pixels in the next line are set as peripheral pixels, and error diffusion to these pixels I do. For example, three weights on the current line are assigned to 4/16, 2/16, 2/16 in order from the closest to the pixel of interest, and four on the next line are assigned to the pixel of interest. In order from the nearest, 4/16, 2/16, 1/16, and 1/16. Note that the weights to be assigned are set so as to be 1 in total, and by doing so, it is possible to perform gradation expression with no error as a whole.

For the weighting 255, error data to be diffused with respect to a predetermined peripheral pixel is determined for each peripheral pixel in accordance with the above-described method, and the determined error data is used when a pixel to be diffused is a target of quantization processing. Are added to the input image data in the same manner as for the current pixel (see the above description of the processing performed by the addition 251).
For this purpose, each unprocessed pixel that is subjected to diffusion of error data is accumulated every time the quantization process is performed, and the error data that is diffused is accumulated for each pixel (hereinafter referred to as [weight addition]) A process for outputting the error data accumulated at the timing of the conversion processing to the addition 251 is required.

  This processing is performed by the error storage / output 256. The error storage / output 256 is a line buffer prepared for storing one line of error data which is diffused and accumulated in all unprocessed pixels of the next line. Each time the quantization process is performed on each pixel, error data obtained by weight addition using a buffer for the corresponding pixels (four pixels in the example of FIG. 8) is stored pixel by pixel. At the end of the current line, the error data stored and saved for one line in the line buffer is output in time with the quantization processing of the pixel in the next line. The means necessary for the weight addition will be described later with reference to FIG.

Further, the error storage / output 256 uses a buffer for pixels (3 pixels in the example of FIG. 8) as a diffusion destination in the current line, and separately by weight addition (means necessary for weight addition are shown in FIG. 9). The error data is obtained and output in time with the quantization processing of the pixel in the current line.
In the example of FIG. 5, in the process for diffusing the error data and reflecting it in the quantization process of the subsequent pixels, the input data +2 bits is generally used. Processing is in progress.
Thus, along with the weight addition operation, the memory capacity of the buffer for storing the result, particularly the line buffer, becomes considerably large because 12-bit error data is stored for each pixel of one line. This is a motivation that requires a halftone processing system in the present embodiment to be described later.

"Example circuit configuration for weighting and error storage / output"
FIG. 9 is a diagram showing a circuit configuration example of weighting and error storage / output in the halftone processing system shown in FIG.
In FIG. 9, weighting 255 indicates a configuration example of a circuit according to the weighting method illustrated in FIG.
In other words, the weights for the three unprocessed pixels at the current line being processed are 4/16, 2/16, and 2/16 in order from the pixel closest to the target pixel. Multiplication is performed, and the four diffusion destinations in the next line are multiplied by 4/16, 2/16, 1/16, and 1/16 in order from the closest point of interest pixel.

The error storage / output 256 stores the error data diffused by each pixel obtained by weighting multiplication by the weighting 255 in the buffer for each pixel. At this time, the error data diffused by the internal weight addition 256i is stored. Accumulate. The weight addition 256i includes a buffer for the number of pixels at the diffusion destination and an addition unit for the accumulated number as means necessary for the weight addition.
In other words, as shown in FIG. 9, for diffusion to the current line, each pixel becomes the diffusion destination three times, so a buffer for three pixels and an adding means for performing accumulation twice are provided, and quantization is performed. The buffer value is shifted according to the movement of the target pixel of processing, and error data to be diffused is accumulated twice until each pixel becomes the target pixel in the quantization processing of the current line. Output the error data to be added to the input data. Also, for diffusion to the next line, each pixel becomes the diffusion destination four times, so a buffer for four pixels and an adding means for performing accumulation three times are provided to move the target pixel of the quantization process. At the same time, the buffer value is shifted, and the error data diffused for each pixel of the next line is accumulated three times until the quantization process for the current line is completed, and the error data obtained by this accumulation is temporarily stored in the line. The data is stored in the buffer and output in time with the quantization processing of the pixel in the next line.

[Adoption of bit separation]
In the data processing for print output, the number of bits is expanded as described above by taking the γ conversion as an example, and in the halftone processing to be performed later, the error data to be diffused is processed as 12 bits as described above. If the specification is made so as to ensure the above, the memory capacity such as a line buffer (stores error data of each pixel for one line) used for this processing will be enlarged.
Therefore, in this embodiment, in order to suppress the enlargement of the memory capacity used for the error diffusion processing, the upper bits and the lower bits of the error data to be diffused are separated, and different processing is applied to each, followed by A method is adopted in which the line buffer used for reflecting the pixel quantization process is limited to the number of upper bits. In other words, a processing method is adopted that allows the lower-order bits that have been bit-separated to be reflected in the quantization process without being cut off, thereby maintaining both high image quality and suppressing the enlargement of the memory capacity of the buffer.

The bit separation performed in this embodiment is adopted in a system that uses a line buffer that stores error data of the next line, which works more effectively in suppressing the increase in memory capacity when the above processing method is employed. Therefore, regarding the handling of error data diffused to the current line, the above-described existing processing method (see FIGS. 5 and 9) is not changed.
In addition, when diffusing to the next line, the error data diffused for each pixel of the next line is calculated by weight addition 256i, and the process until the output is performed is also the above-described existing processing method (FIGS. 5 and 9). See).

FIG. 10 is a diagram showing a configuration example of a halftone processing system with error diffusion according to the embodiment of the present invention.
The halftone processing system shown in FIG. 10 has elements of bit separation 256s, accumulation 256a, addition 256m, error storage / output (2) 256b, and left shifter 256f as a system for processing diffusion error data to the next line. . Further, as a system for processing error data diffused to the current line, elements of the system that perform the same processing as the above-described existing processing (see FIGS. 5 and 9), that is, error storage / output (1) And 256n and an addition 256n for adding error data given by diffusion to the current line and the next line for the pixel to be quantized.

FIG. 11 is a diagram showing a circuit configuration example in the process of outputting an error to be added to the next pixel from the weighting of the halftone processing system (FIG. 10).
In the figure, the processing system and operation for weighting the generated quantization error and diffusing it to the surrounding pixels and adding the error weight to each diffusion destination pixel have been described with reference to FIG. It is as follows. Note that the weighting 255 shown in FIG. 11 includes a weight addition process as an element of the system for processing the diffusion error data to the next line. Therefore, the output from the weighting 255 is determined as an error for each pixel through the process of adding the weight of the error data diffused to the pixel of the next line during the quantization process of the current line, and the quantization process of the next line This is error data for taking over. This error data is the target of bit separation 256s.

Hereinafter, by employing bit separation that separates the upper and lower bits of the error data to be diffused, the processing is different from the processing system of the previous diffusion error data. The configuration and operation of the processing system up to the addition 256n that reflects the error to be performed will be described.
Bit separation 256 s is obtained by performing weight addition for accumulating error data diffused to the next line in the previous stage for each pixel, and dividing the obtained 12-bit error data into upper 8 bits (including sign bits) and lower 4 bits by bit separation. To do.
The separated upper 8 bits are input to the addition 256m, and the lower 4 bits are input to the accumulation 256a.

The accumulation 256a has a buffer and an adding means, and when there is a new 4-bit data input, it adds the input data to the data held in the buffer so far. When the buffer carries by adding the lower 4 bits of data input of the accumulation 256a, a carry signal is generated and this signal is input to the adder 256m.
Addition 256m adds +1 by the carry signal to the upper 8bit data by the input of the previously separated upper 8bit data.
The addition of the carry signal generated by the accumulation 256a to the upper 8-bit data makes it possible to save data lost when the lower 4-bit data is discarded, and to reflect the stored data in the quantization process. To do.

The result is added to the upper 8 bit data of the carry signal, and the addition result is input to the line buffer of error storage / output (2) 256b which stores error data of the next line and manages its output.
However, an abnormality may occur in the data of the line buffer that receives the addition result of the carry signal. In this case, when the upper 8 bit data is 0x7F (+127) and the carry signal is +1, 0x80 (-127) as the addition result is stored in the line buffer.

In order to prevent this, the following 1. ~ 3. It can be solved by taking any of the following measures.
1. In the bit separation, the upper bits in the separation and the number of bits in the line buffer are set to different numbers so that the following relationship is satisfied.
Number of upper bits separated by bit separation 256s <number of bits in line buffer <number of bits of data separated by bit separation 256s In the case of the embodiment of FIG. 11, the number of bits of data separated by bit separation 256s is 12 bits. Therefore, for example, by setting the number of upper bits separated by bit separation 256s to 7 bits and the bit number of the line buffer to 8 bits, the above relationship can be satisfied.
2. When the upper 8 bits data separated by the bit separation 256s is 0x7F (+127), for example, a function for ignoring the carry signal (+1) is provided in the addition 256m, and the addition result 0x80 (-127) is It is possible to prevent being stored in the line buffer. Although this method has a merit that can be easily configured, it restricts error diffusion and may cause deterioration in image quality.
3. When the upper 8bit data separated by bit separation 256s is 0x7F (+127), the carry signal (+1) is suspended, and when the overflow condition is not satisfied in the subsequent processing, the suspension is canceled, and the next For example, a function to be added to the pixel is provided in the addition 256m, so that 0x80 (−127) of the addition result can be prevented from being stored in the line buffer. This method is the same as that described in 3. Compared with the method of ignoring the carry signal due to, image quality is less likely to deteriorate.

Error storage / output (2) Since the 8-bit error data stored in the 256b line buffer is used in the next line, it is stored until it is used, and is added to the pixel to be processed when the quantization process moves to the next line. Will be. When the 8-bit error data stored in the line buffer is used, the number of bits does not match that of the 12-bit input pixel to be added, so it is necessary to return to 12 bits.
The left shifter 256f is means for converting the 8-bit error data output from the error buffer / output (2) 256b line buffer into 12 bits.
The error data output in 12 bits from the left shifter 256f is added by the diffusion error data to the pixels of the current line of the pixel output through the weight addition 256r and the addition 256n after the quantization process is performed, and is added to the input pixel. Output for appending.

With the above processing, it is possible to reduce the number of bits in the line buffer of error storage / output (2) 256b that stores error data of the next line, leading to suppression of enlargement of the line buffer capacity.
Also, since the lower 4 bits of error data separated by bit separation is added to the pixel array line order and the carry signal is added to the upper 8 bits of error data, it is reflected in the quantization process of the input pixel. Image quality can be maintained without losing gradation.

Here, the process of storing data from the bit separation to the line buffer will be described in more detail. In this case, the above-described 3. An example in which the prevention means shown in FIG.
FIG. 12 is a diagram showing details of a circuit configuration example in the process of storing data from the bit separation of FIG. 11 to the line buffer.
As shown in FIG. 12, the bit separation 256s separates the 12-bit signal of the input error data into upper 8 bits and lower 4 bits excluding the sign bit. Here, since the original error data itself is signed, the upper 8 bit data is signed, but the lower 4 bits are treated as unsigned 4 bit data.
This is the lower 4 bits
[Input data]-[Data obtained by shifting the upper 8bit data by 4bit left]
This is because the following relationship is always established.
[Data obtained by left-shifting the upper 8-bit data by 4 bits] ≤ [Input data]

The accumulation 256a receives the lower bit input obtained from the above relational expression from the bit separation 256s, and adds it with the lower bit data accumulated in the buffer 256d so far by addition 256c.
When the addition result exceeds 0xF (15), the addition 256c generates a carry signal and outputs the generated carry signal to the delay 256g. The delay 256g is one of means for realizing an overflow prevention function described later.
Of the data obtained as the addition result of the addition 256c, the portion excluding the carry portion is stored in the buffer 256d and is sent to the next processing.
Although the data stored in the buffer 256d is not shown when the next line data is processed by line switching, it is desirable to prevent the unexpected error diffusion by resetting the buffer 256d.

When adding the carry signal which is the addition result of the upper 8 bits (signed) output from the bit separation 256s and the lower 4 bit signal output from the adder 256c, based on the value of the upper 8 bit data and the value of the carry signal , To limit the addition (corresponding to 3 of the above overflow prevention measure).
That is, when the upper 8 bit data is 0x7F (+127) and the carry signal is +1, the addition 256m overflows, and as a result, the abnormal data 0x80 (-127) is stored in the line buffer 256h. In order to prevent this operation, the decision 256e predicts the occurrence of overflow based on the value of the upper 8 bit data and notifies the delay 256g of this.
The delay 256g receives the prediction of the occurrence of overflow from the decision 256e, outputs a delay signal, and delays the addition of the carry signal by one time. Here, this function is realized by outputting a signed 2-bit signal from the delay 256g to the addition 256m. Further, when the same condition is satisfied, this signal is sent and delayed until the condition is not satisfied. When it is not satisfied, the release of the delay is notified by a signed 2-bit signal.

FIG. 13 is a table showing an operation example in the circuit configuration of FIG. 12 in a data state of a flow sequentially performed for each pixel.
In FIG. 13, the processing from the first pixel to the fourth pixel shows a case where the error data (input data) input to the bit separation 256s is positive, and the input data is negative in the fifth to seventh pixels. Shows the case.
In the addition of the lower bit data of the input in the addition 256c of the third pixel and the data accumulated in the buffer 256d, the addition result exceeds 0xF, and therefore, addition of a carry of +1 is performed on the upper bit 0x78. The stored data of 256h is 0x79.

In the addition of the input lower bit data in the addition 256c of the fourth pixel and the data stored in the buffer 256d, a carry is generated in the same manner, but the upper bit is 0x7F (+127). In order to prevent this, the carry signal is delayed by one cycle.
The conditions when the input data is negative at the sixth pixel and the seventh pixel are shown, but the addition of the lower 4 bits in the addition 256c is the same processing regardless of whether the input signal is positive or negative.
In addition, in the seventh pixel, since the carry is generated with respect to the input upper bit data 0x8F (−1), it is 0x00 (0). However, since this addition is not an overflow, it is normal. Add carry signals.

By the way, the number of bits of input data, the number of bits of upper and lower bits in bit separation, the number of bits of the line buffer, and the like shown in this embodiment show values as one example.
Therefore, application conditions when the image processing apparatus of the present invention is implemented in the embodiment configured by the above-described elements will be described below.
First, the following condition is satisfied. That is,
The number of upper bits separated by bit separation 256s ≦ the number of bits in the line buffer <the number of data bits separated by bit separation 256s. If this condition is satisfied, the operation of the above embodiment can be realized.
Further, by performing the operation under the following conditions, it is possible to make the processing equivalent to the existing halftone processing (see FIGS. 5 and 9).
Number of upper bits separated by bit separation 256s = number of bits in line buffer = number of bits of data separated by bit separation 256s

In addition, it is possible to switch at least one of the number of high-order bits separated by bit separation 256s, the number of bits in the line buffer, and the number of bits of data separated by bit separation 256s between different bit numbers, and dynamically The circuit may be switched in the number of bits and may be implemented by a method configured to realize the above inequality and equation as application conditions.
By carrying out like this, it can be set as embodiment which included the existing halftone process (refer FIG.5 and FIG.9).
In this embodiment, as the number of upper bits in the bit separation is reduced, the error diffusion is likely to spread over a wide range, and the edge or the like may be blurred.

“Implementation of line buffer”
Further, the implementation of the above-described line buffer will be described. When a dedicated memory such as an SRAM (Static Random Access Memory) is used, a part of a main memory such as a DRAM (Dynamic Random Access Memory) is shared. It is conceivable to reduce the overall circuit scale.
When the main memory is used, the multiple of 8 bits (= 1 Byte) is optimal considering the ease of access and the like. Conventionally, 16 bits were used. However, by applying the present invention, 8 bits is used. It is possible to reduce the memory capacity and the access time by half.
When a dedicated memory is used, since the number of bits can generally be customized, it can be flexibly adapted to the size. According to the dedicated memory, there is no problem that it takes a long time to access when the main memory is used.

Further, since the line buffer stores error data of each pixel of the next line, it is necessary to prepare one line, and the total size is affected by the number of pixels of one line. For example, as the resolution increases or the paper size increases, the size required for the line buffer increases.
Conventionally, it has been necessary to prepare a line buffer in accordance with the maximum environment to be used. In this embodiment, as described above, the number of upper bits to be separated by bit separation and the number of bits in the line buffer are dynamically set. Since this function is used, when the resolution is increased or the paper size is increased, the line buffer size is reduced by reducing the number of bits of the line buffer accordingly. Can do.

The following (1) to (4) are separated by bit separation based on the set resolution and paper size, taking as an example the case where the input data to the halftone processing block is 10 bits and the number of generated error bits is 12 bits. In this embodiment, the number of upper bits and the number of bits in the line buffer are dynamically switched to suppress the size of the line buffer. Note that (1) below is an operation mode equivalent to the conventional one without any suppression.
(1) "A4, 600dpi" ... "Upper bit number in bit separation: 12bit", "Line buffer bit number: 12bit"
(2) "A4, 1200dpi" ... "Upper bit number in bit separation: 6bit", "Line buffer bit number: 6bit"
(3) "A3, 600dpi" ... "Upper bit number in bit separation: 8bit", "Line buffer bit number: 8bit"
(4) "A3, 1200dpi" ... "Upper bit number in bit separation: 4bit", "Line buffer bit number: 4bit"

  1 .. MFP (multifunction machine) 2 .. Controller 3. Scanner unit 4.. Plotter unit 25.. Halftone processing 252 ... Quantization 253 ... Inverse quantization 255 Error storage / output 256a Accumulation 256r Error storage / output (1) 256b Error storage / output (2) 256h Line buffer 256i Weight addition 256s Bit separation, 256d, buffer, 20 CPU.

JP 2004-096709 A

Claims (8)

To the multi-value data of the pixel to be processed in the image composed of pixels of the multi-value data, error data generated in the peripheral pixels and diffused to the pixel to be processed are added, and then compared with the threshold value. Quantization means for outputting value data;
Quantization error calculation means for calculating an error due to quantization by comparing the low-value data quantized by the quantization means and the original multi-value data;
Weighting means for assigning a weight for diffusing the error calculated by the quantization error calculating means to a plurality of target peripheral pixels;
In the quantization error diffusion process of the current line, the error data diffused according to the weight given by the weighting unit is added to the error data accumulated until the quantization error diffusion process of the current line for each pixel. Error adding means;
A buffer for storing the error data calculated by the error adding means in accordance with a pixel arrangement in a processing order in order to add to the input data to the quantization means of the pixel to be processed,
Data separating means for separating the error data of the next line calculated by the error adding means into upper bits and lower bits;
In the quantization error diffusion process of the current line, the error data of the lower bits of the next line accumulated until the quantization error diffusion process of the current line is obtained for each pixel by using the error data of the lower bits separated by the data separation unit. Low-order bit error accumulation means for adding to the data and outputting a carry signal;
Upper bit error data calculating means for adding a carry signal output from the lower bit error accumulating means to the upper bit error data separated by the data separating means;
A next line error data storage unit for storing upper bit error data calculated by the upper bit error data calculation means provided in the buffer;
When the error data stored in the next line error data storage unit is applied to the quantization error diffusion processing of the current line, a left shifter for adjusting to the original number of bits is provided .
The data separation means, the next line error data storage unit, and the error addition means are expressed by the following relational expression:
The number of upper bits separated by the data separation means ≦ the number of error data bits saved by the next line error data storage unit <the number of error data bits separated by the data separation means
An image processing apparatus configured based on the above . To the multi-value data of the pixel to be processed in the image composed of pixels of the multi-value data, error data generated in the peripheral pixels and diffused to the pixel to be processed are added, and then compared with the threshold value. Quantization means for outputting value data;
Quantization error calculation means for calculating an error due to quantization by comparing the low-value data quantized by the quantization means and the original multi-value data;
Weighting means for assigning a weight for diffusing the error calculated by the quantization error calculating means to a plurality of target peripheral pixels;
In the quantization error diffusion process of the current line, the error data diffused according to the weight given by the weighting unit is added to the error data accumulated until the quantization error diffusion process of the current line for each pixel. Error adding means;
A buffer for storing the error data calculated by the error adding means in accordance with a pixel arrangement in the processing order in order to add to the input data to the quantization means of the pixel to be processed;
An image processing apparatus comprising:
Data separating means for separating the error data of the next line calculated by the error adding means into upper bits and lower bits;
In the quantization error diffusion process of the current line, the error data of the lower bits of the next line accumulated until the quantization error diffusion process of the current line is obtained for each pixel by using the error data of the lower bits separated by the data separation unit. Low-order bit error accumulation means for adding to the data and outputting a carry signal;
Upper bit error data calculating means for adding a carry signal output from the lower bit error accumulating means to the upper bit error data separated by the data separating means;
A next line error data storage unit for storing upper bit error data calculated by the upper bit error data calculation means provided in the buffer;
When applying the error data stored in the next line error data storage unit to the quantization error diffusion processing of the current line, a left shifter for adjusting to the original number of bits
With
The data separation means, the next line error data storage unit, and the error addition means are expressed by the following relational expression:
The number of upper bits separated by the data separation means <the number of error data bits of the upper bits saved by the next line error data storage unit <the number of error data bits separated by the data separation means. A featured image processing apparatus. The image processing apparatus according to claim 1 ,
The number of upper bits separated by the data separation means, the number of bits of error data of the upper bits stored by the next line error data storage unit, and the number of bits of error data separated by the data separation means An image processing apparatus characterized in that it can be switched between different numbers of bits. In the image processing device according to claim 1 or 3 ,
An image processing apparatus, comprising: means for ignoring a carry signal of an input low-order bit when a condition for overflowing a high-order bit is satisfied by addition of a carry signal of a low-order bit in the high-order bit error data calculation means. In the image processing device according to claim 1 or 3 ,
When the condition that the upper bit overflows by the addition of the lower bit carry signal in the upper bit error data calculation means is satisfied, the input of the lower bit carry signal is suspended and the overflow condition is not satisfied in the subsequent processing. An image processing apparatus comprising means for releasing the hold when the image is held. The image processing apparatus according to any one of claims 1 to 5 ,
The image processing apparatus is characterized in that the buffer is configured using a memory dedicated to quantization processing accompanied by error diffusion. The image processing apparatus according to any one of claims 1 to 5 ,
The image processing apparatus characterized in that the buffer is configured to share a main memory used in a system that controls the entire image processing apparatus. The image processing device according to claim 7 ,
An image processing apparatus, wherein the number of bits of the buffer is 8 bits.

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