JP5752962B2 - Charge amplifier used in the chopper method - Google Patents

Description

The present invention relates to a charge amplifier that uses a circuit in which a pair of MOS transistors are connected in series as a feedback resistor and uses the circuit in a chopper method .

The maximum current flowing between the drain and source of the MOS transistor is determined by the voltage applied between the gate and source of the MOS transistor. By adjusting the voltage applied between the gate and the source, the current flowing between the drain and the source of the MOS transistor can be limited. When a MOS transistor is used, it is possible to obtain a phenomenon that the energization current does not increase even when the drain-source voltage increases (the energization current is saturated).
For example, as shown in FIG. 9A, an NMOS transistor 4 whose voltage applied between the gate and the source is adjusted by the gate-source voltage adjustment circuit 5 is connected between the input terminal 2 and the output terminal 8. If it is inserted, the current flowing from the input terminal 2 to the output terminal 8 can be limited to a certain current or less.
Similarly, as shown in FIG. 10 (1), the PMOS transistor 6 whose voltage applied between the gate and the source is adjusted by the gate-source voltage adjusting circuit 7 is connected to the output terminal 8 and the input terminal 2. If inserted between them, the current flowing from the output terminal 8 to the input terminal 2 can be limited to a predetermined current or less.

However, the above phenomenon is limited by the energization direction. This is because the source and drain of the MOS transistor are not determined by the structure of the MOS transistor, and change depending on the energization direction. In the case of FIG. 9, when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8 and current flows from the input terminal 2 to the output terminal 8, the output of the NMOS transistor 4 is output as shown in (1). Since the electrode 48 on the terminal 8 side becomes the source S, the voltage between the gate G and the source S does not increase even if the voltage at the input terminal 2 increases, and the value of the saturation current flowing between the drain D and the source S increases. There is nothing to do.
However, when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2 and a current flows from the output terminal 8 toward the input terminal 2, as shown in (2), the input terminal 2 side of the NMOS transistor 4 Therefore, if the voltage at the output terminal 8 rises, the voltage between the gate G and the source S rises. The voltage adjusting circuit 5 functions as a voltage adjusting circuit between the gate G and the source S in the case of (1), but does not function as a voltage adjusting circuit between the gate G and the source S in the case of (2). . In the case shown in (2), when the voltage at the output terminal 8 increases, the voltage between the gate G and the source S increases, and the value of the saturation current flowing between the drain D and the source S increases. When the voltage at the output terminal 8 is higher than the voltage at the input terminal 2, even if the NMOS transistor 4 is inserted, the energization current value increases following the increase in the voltage difference.

In the case of FIG. 10, when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2 and current flows from the output terminal 8 toward the input terminal 2, the output of the PMOS transistor 6 is output as shown in (1). Since the electrode 68 on the terminal 8 side becomes the source S, the voltage between the gate G and the source S does not increase even if the voltage at the output terminal 8 increases, and the value of the saturation current flowing between the drain D and the source S increases. There is nothing to do.
However, when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8 and a current flows from the input terminal 2 toward the output terminal 8, the input terminal 2 side of the PMOS transistor 6 is connected as shown in (2). Therefore, if the voltage at the input terminal 2 increases, the voltage between the gate G and the source S increases. The voltage adjustment circuit 7 functions as a voltage adjustment circuit between the gate G and the source S in the case of (1), but does not function as a voltage adjustment circuit between the gate G and the source S in the case of (2). In the case shown in (2), if the voltage at the input terminal 2 increases, the voltage between the gate G and the source S increases, and the value of the saturation current flowing between the drain D and the source S increases. When the voltage at the input terminal 2 is higher than the voltage at the output terminal 8, even if the PMOS transistor 6 is inserted, the energization current value increases following the increase in the voltage difference.

  FIG. 4 shows a circuit in which the feedback capacitors 12a and 12b and the feedback resistors 10a and 10b are connected between the input and output of the operational amplifier 14, and a charge amplifier is realized by the operational amplifier 14. In this case, if the capacitances of the feedback capacitors 12a and 12b are constant, the higher the resistance values of the feedback resistors 10a and 10b, the lower the operating frequency band in which the operational amplifier 14 functions as a charge amplifier can function. The phenomenon that the output voltage of the operational amplifier 14 changes with time can be suppressed. If an NMOS transistor or a PMOS transistor is used, feedback resistors 10a and 10b having a high resistance value can be realized. In order to form a high resistance value required by the feedback resistors 10a and 10b with normal wiring resistance, a large area is required on the substrate. On the other hand, an NMOS transistor or a PMOS transistor can be formed in a very small area. There is a great merit that the feedback resistors 10a and 10b can be realized by an NMOS transistor or a PMOS transistor which can be downsized. Patent Document 1 discloses a technique for realizing a feedback resistor with an NMOS transistor or a PMOS transistor.

JP 2002-185298 A

In the case illustrated in FIG. 4, the magnitude relationship between the output voltage of the operational amplifier 14 and the input voltage is not determined. The input voltage may be greater than the output voltage, or the input voltage may be less than the output voltage.
As shown in FIG. 9, when the voltage between the electrode 48 on the output terminal 8 side of the NMOS transistor 4 and the gate G is adjusted by the gate-source voltage adjusting circuit 5, as described above, the input voltage> the output voltage. For some time, it functions as a feedback resistor 10a that provides a large resistance value. However, when the input voltage is smaller than the output voltage, the resistance value decreases. In the circuit of FIG. 9, the feedback resistor 10a that provides a constant resistance value is not obtained regardless of the magnitude relationship between the output voltage and the input voltage.
Similarly, as shown in FIG. 10, when the voltage between the electrode 68 on the output terminal 8 side of the PMOS transistor 6 and the gate G is adjusted by the gate-source voltage adjustment circuit 7, as described above, the input voltage < While it is the output voltage, it functions as a feedback resistor 10a that provides a large resistance value. However, when the input voltage is greater than the output voltage, the resistance value decreases. In the circuit of FIG. 10, the feedback resistor 10a that provides a constant resistance value is not obtained regardless of the magnitude relationship between the output voltage and the input voltage.
The same problem occurs when the feedback resistor 10b is realized by an NMOS transistor or a PMOS transistor.
A circuit that can limit the energization current between the input terminal 2 and the output terminal 8 to a predetermined current or less without depending on the magnitude relationship between the voltage at the input terminal 2 and the voltage at the output terminal 8 shown in FIG. 9 and FIG. There is a need for technology to form.

In the technique disclosed in this specification, a pair of MOS transistors forming a feedback resistor are connected in series between an input terminal and an output terminal of an operational amplifier. The operational amplifier used in the present technology has two inputs and two outputs. A series circuit of an NMOS transistor and a PMOS transistor is also inserted between the first input terminal and the first output terminal, and the second input terminal and the second output terminal are connected. A series circuit of an NMOS transistor and a PMOS transistor is also inserted between them. In addition, a gate-source voltage that limits the current flowing between the drain and source of each MOS transistor to a certain current or less is applied between the electrode on the output terminal side of each MOS transistor and the gate electrode. That is, a voltage regulating circuit between the gate and the source, to connect to the electrode and the gate electrode of the output terminal side of each MOS transistor.

When an NMOS transistor and a PMOS transistor of opposite conductivity type are connected in series and the potential difference between the output terminal side electrode and the gate electrode of each MOS transistor is controlled, if the input terminal voltage> the output terminal voltage, then the NMOS transistor When the gate-source voltage is controlled to be high resistance and the input terminal voltage is smaller than the output terminal voltage, the gate-source voltage of the PMOS transistor is controlled to be high resistance. A high feedback resistance can be obtained in both directions.

  (A1) of FIG. 1 is connected to the gate outside electrode (electrode which is not the gate G) 48 of the NMOS transistor 4R connected to the gate-source voltage adjusting circuit 5R and the gate-source voltage adjusting circuit 7R. In the illustrated example, the outer gate electrodes 68 of the PMOS transistors 6R are connected in a direction facing the output terminal 8 side. Even in (a2), the gate outer electrode 68 of the PMOS transistor 6R connected to the gate-source voltage adjusting circuit 7R and the gate outer electrode 48 of the NMOS transistor 4R connected to the gate-source voltage adjusting circuit 5R are provided. Both face the output terminal 8 side. In FIG. 1, the subscript R indicates that the outer gate electrode connected to the gate-source voltage adjustment circuit faces the output terminal 8 side.

  (A3) in FIG. 1 shows the gate outside electrode 42 of the NMOS transistor 4L connected to the gate-source voltage adjusting circuit 5L and the gate outside of the PMOS transistor 6L connected to the gate-source voltage adjusting circuit 7L. The case where both the electrodes 62 are connected in the direction facing the input terminal 2 is illustrated. Even in (a4), the gate outer electrode 62 of the PMOS transistor 6L connected to the gate-source voltage adjusting circuit 7L and the gate outer electrode 42 of the NMOS transistor 4L connected to the gate-source voltage adjusting circuit 5L are provided. Both face the input terminal 2 side. In FIG. 1, the subscript L indicates that the outer gate electrode connected to the gate-source voltage adjusting circuit faces the input terminal 2 side.

In the case of FIG. 1A1, when the input voltage> the output voltage, the electrode 48 of the NMOS transistor 4R serves as the source, the gate-source voltage adjustment circuit 5R adjusts the gate-source voltage, and the drain-source connection Limit saturation current. The gate-source voltage adjustment circuit 5R is a circuit that applies a gate-source voltage that limits the current flowing between the drain and source of the NMOS transistor 4R to a predetermined current or less. When the input voltage <the output voltage, the electrode 68 of the PMOS transistor 6R serves as the source, and the gate-source voltage adjustment circuit 7R adjusts the gate-source voltage to limit the saturation current between the drain and source. The gate-source voltage adjustment circuit 7R is a circuit that applies a gate-source voltage that limits the current flowing between the drain and source of the PMOS transistor 6R to a predetermined current or less.
The same applies to (a2).

In the case of FIG. 1A3, when the output voltage> the input voltage, the electrode 42 of the NMOS transistor 4L serves as the source, the gate-source voltage adjustment circuit 5L adjusts the gate-source voltage, and the drain-source connection Limit saturation current. The gate-source voltage adjustment circuit 5L is a circuit that applies a gate-source voltage that limits the current flowing between the drain and source of the NMOS transistor 4L to a predetermined current or less. When the input voltage> the output voltage, the electrode 62 of the PMOS transistor 6L serves as the source, and the gate-source voltage adjustment circuit 7L adjusts the gate-source voltage to limit the saturation current between the drain and source. The gate-source voltage adjustment circuit 7L is a circuit that applies a gate-source voltage that limits the current flowing between the drain and source of the PMOS transistor 6L to a predetermined current or less.
The same applies to (a4).

As shown in (a1) to (a4) of FIG. 1, when a current limiting circuit is configured by a series circuit of an NMOS transistor 4 and a PMOS transistor 6 having opposite conductivity types, a series circuit of 4R and 6R (into a1 and a2) Or a series circuit of 4L and 6L (illustrated by a3 and a4). A series circuit of 4R and 6L and a series circuit of 4L and 6R are inappropriate.
When (a1) to (a4) in FIG. 1 are observed along the current flow, a pair of gate outer electrodes (48 and 68, 42 and 62) connected to the pair of gate-source voltage adjusting circuits 5 and 7 are observed. ) Are connected in the same direction.

When a pair of NMOS transistors are connected in series, the outer gate electrodes connected to the gate-source voltage adjusting circuit are connected in the opposite direction.
In (b1) of FIG. 1, the gate external electrode 48R connected to the gate-source voltage adjustment circuit 5R is connected to the NMOS transistor 4R facing the output terminal 8 side and the gate-source voltage adjustment circuit 5L. A current limiting circuit is configured by a series circuit of NMOS transistors 4L in which the outer gate electrode 42L faces the input terminal 2 side. Also in FIG. 1 (b2), the gate external electrode 42L connected to the gate-source voltage adjustment circuit 5L is connected to the NMOS transistor 4L facing the input terminal 2 side and the gate-source voltage adjustment circuit 5R. A current limiting circuit is constituted by a series circuit of NMOS transistors 4R in which the gate outer electrode 48R faces the output terminal 8 side.
1 (b1) and (b2), when the input voltage> the output voltage, the electrode 48R of the NMOS transistor 4R serves as the source, the gate-source voltage adjustment circuit 5R adjusts the gate-source voltage, Limit saturation current between sources. When the input voltage <the output voltage, the electrode 42L of the NMOS transistor 4L serves as the source, and the gate-source voltage adjustment circuit 5L adjusts the gate-source voltage to limit the saturation current between the drain and source.
As shown in (b1) and (b2) of FIG. 1, when a current limiting circuit is constituted by a series circuit of a pair of NMOS transistors 4, it is constituted by a series circuit of 4R and 4L. A series circuit of 4R and 4R and a series circuit of 4L and 4L are inappropriate. When (b1) and (b2) in FIG. 1 are observed along the current flow, the pair of gate-outer electrodes (48R and 42L) connected to the pair of gate-source voltage adjusting circuits 5R and 5L are opposite to each other. It can be seen that they are connected in the direction facing the direction.

In (c1) of FIG. 1, the gate-outer electrode 68R connected to the gate-source voltage adjusting circuit 7R is connected to the PMOS transistor 6R facing the output terminal 8 and the gate-source voltage adjusting circuit 7L. A current limiting circuit is configured by a series circuit of PMOS transistors 6L in which the external gate electrode 62L faces the input terminal 2 side. Also in FIG. 1C2, the gate external electrode 62L connected to the gate-source voltage adjustment circuit 7L is connected to the PMOS transistor 6L facing the input terminal 2 side and the gate-source voltage adjustment circuit 7R. A current limiting circuit is constituted by a series circuit of PMOS transistors 6R in which the outer gate electrode 68R faces the output terminal 8 side.
In the case of FIGS. 1C1 and 2C2, when the input voltage> the output voltage, the electrode 62L of the PMOS transistor 6L serves as the source, the gate-source voltage adjustment circuit 7L adjusts the gate-source voltage, Limit saturation current between sources. When the input voltage <the output voltage, the electrode 68R of the PMOS transistor 6R serves as the source, and the gate-source voltage adjustment circuit 7R adjusts the gate-source voltage to limit the saturation current between the drain and source.
As shown in (c1) and (c2) of FIG. 1, when a current limiting circuit is constituted by a series circuit of a pair of PMOS transistors 6, it is constituted by a series circuit of 6R and 6L. A series circuit of 6R and 6R and a series circuit of 6L and 6L are inappropriate. When (c1) and (c2) in FIG. 1 are observed along the current flow, the pair of gate-outer electrodes (68R and 62L) connected to the pair of gate-source voltage adjusting circuits 7R and 7L are opposite to each other. It can be seen that they are connected in the direction facing the direction.

  For example, in the case of (a1), if the input voltage> the output voltage, the electrode 48 of the NMOS transistor 4R becomes the source. Therefore, even if the voltage at the input terminal 2 rises, the gate-source voltage of the NMOS transistor 4R is adjusted by the gate-source voltage adjustment circuit 5R, and the current flowing between the drain and source of the NMOS transistor 4R is • The saturation current determined by the source-to-source voltage cannot be exceeded. When input voltage> output voltage, the electrode 62 on the input terminal 2 side of the PMOS transistor 6R serves as a source. Therefore, if the voltage at the input terminal 2 increases, the voltage between the gate and source of the PMOS transistor 6R increases and the saturation current increases. When the input voltage> the output voltage, the current value cannot be limited in the PMOS transistor 6R. Since the NMOS transistor 4R is connected in series, the current value can be limited by the NMOS transistor 4R when the input voltage> the output voltage.

If the output voltage> the input voltage, the electrode 68 of the PMOS transistor 6R becomes the source. Therefore, even if the voltage at the output terminal 8 rises, the gate-source voltage of the PMOS transistor 6R is adjusted by the gate-source voltage adjustment circuit 7R, and the current flowing between the drain and source of the PMOS transistor 6R is • The saturation current determined by the source-to-source voltage cannot be exceeded. When output voltage> input voltage, the electrode 42 on the input terminal 2 side of the NMOS transistor 4R serves as the source. Therefore, when the voltage at the output terminal 8 increases, the gate-source voltage of the NMOS transistor 4R increases and the saturation current increases. When the output voltage> the input voltage, the current value cannot be limited in the NMOS transistor 4R. Since the PMOS transistor 6R is connected in series, the current value can be limited by the PMOS transistor 6R when the output voltage> the input voltage.
The same applies to (a2).

In the case of (a3), if the input voltage> the output voltage, the electrode 62 of the PMOS transistor 6L becomes the source, so that the gate-source voltage adjustment circuit 7L adjusts the gate-source voltage to a constant value. The source-to-source current is regulated below a certain value. If the output voltage is greater than the input voltage, the gate-source voltage adjustment circuit 5L adjusts the gate-source voltage to a constant value because the electrode 42 of the NMOS transistor 4L is the source, and the drain-source current is a constant value. It is regulated as follows.
The same applies to (a4).

In the case of (b1), if the input voltage is greater than the output voltage, the gate-source voltage adjustment circuit 5R adjusts the gate-source voltage to a constant value because the electrode 48R of the NMOS transistor 4R serves as the source. The source-to-source current is regulated below a certain value. If the output voltage is greater than the input voltage, the gate-source voltage adjustment circuit 5L adjusts the gate-source voltage to a constant value because the electrode 42L of the NMOS transistor 4L is the source, and the drain-source current is a constant value. It is regulated as follows.
The same applies to (b2).
In the case of (c1), if the input voltage is greater than the output voltage, the gate-source voltage adjustment circuit 7L adjusts the gate-source voltage to a constant value because the electrode 62L of the PMOS transistor 6L serves as the source. The source-to-source current is regulated below a certain value. If the output voltage> the input voltage, since the electrode 68R of the PMOS transistor 6R becomes the source, the gate-source voltage adjustment circuit 7R adjusts the gate-source voltage to a constant value, and the drain-source current becomes a constant value. It is regulated as follows.
The same applies to (c2).

  In the case of FIG. 1, the body of the MOS transistor is connected to an outer gate electrode connected to a gate-source voltage adjusting circuit. However, that connection is not essential. As shown in FIG. 2, the body of the NMOS transistor may be grounded to the GND potential. That is, the body may be connected to the low voltage terminal side of the power supply for the gate-source voltage adjustment circuit. Also in this case, the current flowing between the drain and source of the NMOS transistor can be limited by adjusting the gate-source voltage of the NMOS transistor. The body of the PMOS transistor may be connected to the Vcc potential. That is, the body may be connected to the high voltage terminal side of the power supply for the gate-source voltage adjustment circuit. Also in this case, the current flowing between the drain and source of the PMOS transistor can be limited by adjusting the gate-source voltage of the PMOS transistor.

  As shown in FIGS. 1 and 2 (a1) to (a4), when the pair of MOS transistors are of the opposite conductivity type, a pair connected to the pair of gate-source voltage adjustment circuits 5, 7 By connecting the outer gate electrodes (48 and 68, 42 and 62) in the same direction, a bidirectional current limiting circuit is obtained. As shown in FIGS. 1 and 2 (b1) to (c2), when a pair of MOS transistors have the same conductivity type, a pair of gate-source voltage adjustment circuits (5R and 5L, 7R and 7L) A pair of outer gate electrodes (48R and 42L, 68R and 62L) connected to each other are connected in directions opposite to each other, thereby forming a bidirectional current limiting circuit.

As is clear from FIGS. 1 and 2 (a1) and (a2), the connection order of the NMOS transistor 4R and the PMOS transistor 6R is not limited. The NMOS transistor 4R may be disposed on the input terminal 2 side, and the PMOS transistor 6R may be disposed on the output terminal 8 side, or vice versa. As illustrated in (a1), when the NMOS transistor 4R is arranged on the input terminal 2 side, the gate external electrode of the NMOS transistor 4R (among the two electrodes connected to the gate-source voltage adjustment circuit) 48, which is the non-gate electrode, the same applies hereinafter) 48 is connected to the output terminal 8 via the PMOS transistor 6R, and the gate outer electrode 68 of the PMOS transistor 6R is directly connected to the output terminal 8. In the present specification, “the outer gate electrode is connected in the same direction” includes the above relationship. Further, as illustrated in (a2), when the PMOS transistor 6R is disposed on the input terminal 2 side, the gate outside electrode 68 of the PMOS transistor 6R is connected to the output terminal 8 via the NMOS transistor 4R, and the NMOS transistor The 4R gate outer electrode 48 is directly connected to the output terminal 8. In the present specification, “the outer gate electrode is connected in the same direction” also includes the above connection relation.
As illustrated in (a3), when the NMOS transistor 4L in which the outer gate electrode 42 faces the input terminal 2 is arranged on the input terminal 2 side, the outer gate electrode 62 of the PMOS transistor 6L passes through the NMOS transistor 4L. Connected to the input terminal 2. As illustrated in (a4), when the PMOS transistor 6L in which the outer gate electrode 62 faces the input terminal 2 is arranged on the input terminal 2 side, the outer gate electrode 42 of the NMOS transistor 4L passes through the PMOS transistor 6L. Connected to the input terminal 2. These connection relationships are also included in “the outer gate electrodes are connected in the same direction” in the present specification.

Even when a pair of MOS transistors of the same conductivity type connected in a direction in which the outer electrode of the gate faces in the opposite direction is connected in series, the connection order is not limited. As illustrated in (b1), the NMOS transistor 4R in which the outer gate electrode 48R faces the output terminal 8 side is arranged on the input terminal 2 side, and the NMOS transistor 4L in which the outer gate electrode 42L faces the input terminal 2 side. May be disposed on the output terminal 8 side, or, as illustrated in FIG. 2B, an NMOS transistor 4L having the outer gate electrode 42L facing the input terminal 2 is disposed on the input terminal 2 side, and the outer gate electrode The NMOS transistor 4R in which 48R faces the output terminal 8 side may be arranged on the output terminal 8 side. As illustrated in (c1), the PMOS transistor 6R in which the outer gate electrode 68R faces the output terminal 8 side is arranged on the input terminal 2 side, and the PMOS transistor 6L in which the outer gate electrode 62L faces the input terminal 2 side. May be arranged on the output terminal 8 side. Alternatively, as illustrated in (c2), a PMOS transistor 6L in which the outer gate electrode 62L faces the input terminal 2 side is arranged on the input terminal 2 side, and a PMOS in which the outer gate electrode 68R faces the output terminal 8 side. The transistor 6R may be disposed on the output terminal 8 side.
In this specification, “the outer gate electrode is connected in the opposite direction” includes (b1), (b2), (c1), and (c2) in FIGS.

As illustrated in FIG. 2, the body of the NMOS transistor is connected to the low voltage (GND) terminal of the power supply for the gate-source voltage adjustment circuit, and the body of the PMOS transistor is connected to the high voltage (Vcc) terminal of the power supply. It may be connected. Even in this case, the current can be limited.
As illustrated in FIG. 1, the body of a pair of MOS transistors has a gate / source via the above-described outer gate electrode (an electrode connected to the gate-source voltage adjusting circuit but not the gate). It is preferable to be connected to an inter-voltage adjustment circuit. In this case, the threshold voltage does not increase due to the bias effect of the substrate, and a wide voltage range in which the circuit operates normally can be secured. On the other hand, in the case of FIG. 2, the threshold voltage rises because a voltage is applied between the source and the body (substrate bias effect), and the voltage range in which the circuit operates normally is narrowed.

When a current limiting circuit realized by a pair of MOS transistors is inserted between the input terminal and the output terminal of the operational amplifier, the pair of MOS transistors are of opposite conductivity type, and the outer gate electrode of each MOS transistor is It is preferable to connect in a direction facing the output terminal side. As illustrated in FIG. 4, when the feedback resistor 10a inserted between the input terminal 2a and the output terminal 8a of the operational amplifier 14 is realized by a current limiting circuit composed of a pair of MOS transistors, b1) (b2) (c1) (c2) is not the type using the same conductivity type MOS transistor as illustrated in FIG. 1, but the opposite conductivity type MOS transistors illustrated in (a1) to (a4) of FIG. It is preferable to use it. Moreover, the direction illustrated in FIGS. 1A3 and 1A4, that is, the gate outer electrode does not face the input terminal side, but the direction illustrated in (a1) and (a2), that is, outside the gate. It is preferable that the electrode is directed to the output terminal side.
The same applies to the feedback resistor 10b inserted between the input terminal 2b and the output terminal 8b of the operational amplifier 14.

When the above conditions are satisfied, the body of the NMOS transistor and the body of the PMOS transistor are connected to the output terminal side via the outer gate electrode that is conducted to the body. In this case, noise applied to the substrate of the NMOS transistor or PMOS transistor or a leak current flowing through the substrate is not transmitted to the input side of the operational amplifier. This stabilizes the output of the operational amplifier. In addition, the current supplied to the MOS transistor from the gate-source voltage adjustment circuit can be prevented from flowing to the input terminal of the operational amplifier, and the voltage of the input terminal of the operational amplifier can be shifted by the current flowing. Can be prevented.
Even in the case of the method of FIG. 2, if the outer gate electrode is connected to the output terminal side, noise applied to the MOS transistor and leak current flowing through the MOS transistor are not transmitted to the input side of the operational amplifier. This stabilizes the output of the operational amplifier.
The above description is limited to the case of using the feedback resistor of the operational amplifier. Various types illustrated in FIGS. 1 and 2 can be used for the current limiting circuit used for other applications.

  As illustrated in FIG. 4, a feedback resistor 10a is inserted between the first input terminal 2a and the first output terminal 8a of the operational amplifier 14 having two inputs and two outputs, and between the second input terminal 2b and the second output terminal 8b. When the feedback resistor 10b is inserted into each, and each of the feedback resistors 10a and 10b is formed by connecting a pair of opposite conductivity type MOS transistors in series, the external gate electrode of each MOS transistor is connected in a direction facing the output terminal side. In addition, the connection order of the pair of opposite conductivity type MOS transistors is preferably the same.

  FIG. 6 shows a case where the feedback resistors 10a and 10b are configured by the series connection listed in FIG. As described above, when used as a feedback resistor of an operational amplifier, a type using both the NMOS transistor 4 and the PMOS transistor 6 which are opposite conductivity types is preferable. Further, it is preferable that the outer gate electrode of the MOS transistor is directed to the output terminal side. That is, it is preferable to employ a series connection having the subscript R in FIG. FIG. 6 illustrates only the serial connection that satisfies the above two conditions.

  6A and 6B, the connection order of the NMOS transistor 4R and the PMOS transistor 6R constituting the feedback resistor 10a and the connection order of the NMOS transistor 4R and the PMOS transistor 6R constituting the feedback resistor 10b are the same. The case is illustrated. On the other hand, FIGS. 6C and 6D show the connection order of the NMOS transistor 4R and the PMOS transistor 6R constituting the feedback resistor 10a, and the connection of the NMOS transistor 4R and the PMOS transistor 6R constituting the feedback resistor 10b. The case where the order is reversed is illustrated. When used as a feedback resistor of an operational amplifier having two inputs and two outputs, it is preferable to adopt the connection order of (A) and (B) in FIG.

For example, in the case of the circuit configuration of FIG. 6C, on the feedback resistor 10a side, a current flows from the gate-source voltage adjustment circuit 5R to the input terminal 2a via the NMOS transistor 4R (the direction of current flow). NMOS transistor 4R has a low resistance), and on the feedback resistor 10b side, no current flows from the gate-source voltage adjusting circuit 7R to the input terminal 2b via the PMOS transistor 6R (the PMOS transistor 6R is in the energizing direction). Is high resistance). Similarly, when the circuit configuration of FIG. 6D is taken, on the feedback resistor 10a side, no current flows from the gate-source voltage adjusting circuit 7R to the input terminal 2a via the PMOS transistor 6R, whereas the feedback resistor 10a On the 10b side, a current flows from the gate-source voltage adjustment circuit 5R to the input terminal 2b via the NMOS transistor 4R. The difference affects the output voltage from the first output terminal 8a and the output voltage from the second output terminal 8b differently. As a result, when the operational amplifier 14 is used as a chopper amplifier, the output voltage from the first output terminal 8a and the output voltage from the second output terminal 8b become unbalanced, and the output voltage from the first output terminal 8a When the output voltage from the output terminal 8b is demodulated, the unevenness difference of the demodulated voltage generated every ½ period of the chopper clock becomes large.
In contrast, as illustrated in FIGS. 6A and 6B, when the connection order of the NMOS and the PMOS is the same, the above imbalance does not occur. For this reason, it is possible to suppress the unevenness difference generated every half cycle of the chopper clock when demodulating the output voltage from the first output terminal 8a and the output voltage from the second output terminal 8b.
However, the above description is limited to the case where the feedback resistor of the operational amplifier with 2 inputs and 2 outputs is used. Various types illustrated in FIGS. 1 and 2 can be used for the current limiting circuit used for other applications.

  According to the technique disclosed in this specification, a circuit that limits the energization current to a predetermined current or less can be realized by a MOS transistor without depending on the magnitude relationship between the input voltage and the output voltage. Since the MOS transistor can be miniaturized, the current limiting circuit can be miniaturized.

The schematic circuit structure of the current limiting circuit of an Example is illustrated. The schematic circuit configuration of the current limiting circuit of another embodiment is illustrated. The voltage / current characteristics of a pair of MOS transistors used in combination are shown. 1 shows an application example of the current limiting circuit according to the embodiment. The circuit structure of the gate-source voltage adjustment circuit of an Example is shown. The current limiting circuit used for the application example 1 is shown. 2 shows an application example 2 of the current limiting circuit of the embodiment. 3 shows an application example 3 of the current limiting circuit of the embodiment. 1 shows a current limiting circuit using a conventional NMOS transistor. 1 shows a current limiting circuit using a conventional PMOS transistor.

The main features of the embodiments described below are exemplified below.
(Feature 1) A gate-source voltage adjustment circuit is connected to each of the first MOS transistor and the second MOS transistor connected in series. Each MOS transistor has two electrodes in addition to the gate, and one of the two electrodes serves as a drain and the other serves as a source depending on the energization direction. In the first MOS transistor, a first gate-source voltage adjusting circuit is connected to an electrode and a gate that become a source in the first energization direction. In the second MOS transistor, a second gate-source voltage adjusting circuit is connected to an electrode and a gate which become a source in the second energizing direction. The first gate-source voltage adjustment circuit is not a gate-source voltage adjustment circuit in the second energization direction, but is a gate-source voltage adjustment circuit in the first energization direction. The second gate-source voltage adjustment circuit is not a gate-source voltage adjustment circuit in the first energization direction, but is a gate-source voltage adjustment circuit in the second energization direction.
The gate-source voltage adjustment circuit referred to in this specification means a circuit that does not become a gate-source voltage adjustment circuit depending on the energization direction, and does not always adjust the gate-source voltage.
A first MOS transistor in which a first gate-source voltage adjustment circuit is connected to the gate and source electrode in the first energizing direction, and a second gate in the source electrode and gate in the second energizing direction -If it is a series circuit of the 2nd MOS transistor to which the voltage adjustment circuit between sources is connected, it will become an intended current limiting circuit.
(Feature 2) A series circuit of an NMOS transistor and a PMOS transistor and a capacitor are connected in parallel between the input terminal and the output terminal of the operational amplifier, thereby forming a charge amplifier. A gate and an outer gate electrode are connected to the gate-source voltage adjusting circuit. In both the NMOS transistor and the PMOS transistor, the outer gate electrode is connected to the output terminal side. In both the NMOS transistor and the PMOS transistor, the body is electrically connected to the outer gate electrode. Since the body of the NMOS transistor and the PMOS transistor are connected to the output terminal side, noise applied to the substrate of the NMOS transistor or PMOS transistor or a leakage current flowing through the substrate can greatly affect the output voltage of the charge amplifier. Absent. Further, since the body is connected to the output terminal side, the parasitic capacitance is small, and the parasitic capacitance does not greatly affect the gain of the charge amplifier. The gain of the charge amplifier is mainly determined by the capacitance ratio of the capacitor. In the case of a charge amplifier, a phenomenon occurs in which the output voltage changes even when the input voltage does not change. When the charge amplifier is used in the chopper method, noise of 1/2 period of the chopper clock is generated in the demodulated output voltage. The rate of change of the output voltage is determined by the product of the capacitor capacity and the feedback resistance, and the slower the product, the greater the product. When the capacitance of the capacitor is constant, the change rate of the output voltage decreases as the feedback resistance increases. According to the series circuit of the NMOS transistor and the PMOS transistor in which the gate-source voltage is adjusted, a large feedback resistance value can be realized, and the noise of 1/2 period of the chopper clock superimposed on the output voltage after demodulation is A small chopper charge amplifier can be realized.
(Feature 3) A current supply circuit and a current mirror circuit constitute a gate-source voltage adjustment circuit that applies a voltage between the gate and the source that limits the drain-source current to a certain value or less. .
(Feature 4) The current mirror circuit reduces the energization current at a predetermined ratio.

FIG. 1 illustrates an example of a bidirectional current limiting circuit that limits both the current flowing from the input terminal 2 to the output terminal 8 and the current flowing from the output terminal 8 to the input terminal 2 to a certain current or less.
In FIG. 1 (a), a series circuit of an NMOS transistor 4 and a PMOS transistor 6 having opposite conductivity types is formed. FIG. 1B shows a series circuit of an NMOS transistor 4R and an NMOS transistor 4L having the same conductivity type. In FIG. 1C, a PMOS transistor 6R and a PMOS transistor 6L having the same conductivity type are configured in series. The connection direction of the non-gate electrode (outer gate electrode) connected to the gate-source voltage adjustment circuit 5 is different between the NMOS transistor 4R and the NMOS transistor 4L. The same applies to the PMOS transistor 6R and the PMOS transistor 6L. It is. In this specification, when a subscript is omitted, it indicates that the description is common to a plurality of events distinguished by the subscript. For example, the case of FIG. 1 (a) indicates that the description is common to FIGS. 1 (a1), (a2), (a3), and (a4). The case of the NMOS transistor 4 is common to the NMOS transistor 4R and the NMOS transistor 4L. Indicates an explanation.

  A voltage at which a predetermined current flows between the drain and source of the NMOS transistor 4R is applied between the gate G and the outer gate electrode 48 of the NMOS transistor 4R by the gate-source voltage adjustment circuit 5R. More precisely, when the outer gate electrode 48 is the source, the gate-source voltage adjustment circuit 5R adjusts the gate-source voltage of the NMOS transistor 4R, and the current flowing between the drain and source of the NMOS transistor 4R. Is limited to a predetermined current. Similarly, a voltage at which a predetermined current flows between the drain and the source of the NMOS transistor 4L is applied between the gate G and the outer gate electrode 42 of the NMOS transistor 4L by the gate-source voltage adjusting circuit 5L. Similarly, a voltage at which a predetermined current flows between the drain and the source of the PMOS transistor 6R is applied between the gate G and the outer gate electrode 68 of the PMOS transistor 6R by the gate-source voltage adjusting circuit 7R. Similarly, a voltage at which a predetermined current flows between the drain and the source of the PMOS transistor 6L is applied between the gate G and the outer gate electrode 62 of the PMOS transistor 6L by the gate-source voltage adjusting circuit 7L.

As shown in FIG. 1, the body B of the NMOS transistor 4R is connected to the gate-source voltage adjustment circuit 5R via the outer gate electrode 48, and the body B of the NMOS transistor 4L is gated via the outer gate electrode 42. The body B of the PMOS transistor 6R is connected to the gate-source voltage adjustment circuit 7R via the outer gate electrode 68, and the body B of the PMOS transistor 6L is outside the gate. The electrode 62 is connected to the gate-source voltage adjusting circuit 7L.

  As shown in FIG. 2, the body of the NMOS transistor 4 is connected to the ground voltage (the voltage at the low voltage side terminal of the power supply for the gate-source voltage adjustment circuit), and the body of the PMOS transistor 6 is connected to the Vcc (gate-source voltage). You may connect to the voltage of the high voltage side terminal of the power supply for adjustment circuits.

1A and 2A, a pair of MOS transistors (4R and 6R, or 4L and 6L) are connected in series between an input terminal 2 and an output terminal 8, A voltage adjustment circuit for applying a gate-source voltage for applying a constant current between the drain and the source is connected to the gate and the outer electrode of the transistor. The pair of transistors are of the opposite conductivity type, and the gate outer electrodes of the pair of transistors are connected in a direction facing the same direction. That is, in the cases (a1) and (a2), the gate outer electrodes 48 and 68 are both connected to the output terminal 8 side, and in the cases (a3) and (a4), the gate outer electrodes 42 and 62 are both input terminals. It is connected to the 2 side.
1B and 2B, a pair of NMOS transistors 4R and 4L are connected in series between an input terminal 2 and an output terminal 8, and the gate and the outer gate electrode of each transistor are connected. In addition, a voltage adjustment circuit for applying a gate-source voltage for applying a constant current between the drain and the source is connected. The pair of transistors 4R and 4L are of the same conductivity type, and the gate outer electrodes 48R and 42L of the pair of transistors 4R and 4L are connected in the opposite direction. That is, the outer gate electrode 48R is connected to the output terminal 8 side, and the outer gate electrode 42L is connected to the input terminal 2 side.
In the current limiting circuit of FIG. 1C and FIG. 2C, a pair of PMOS transistors 6R and 6L are connected in series between the input terminal 2 and the output terminal 8, and the gate and the outer gate electrode of each transistor. In addition, a voltage adjustment circuit for applying a gate-source voltage for applying a constant current between the drain and the source is connected. The pair of transistors 6R and 6L are of the same conductivity type, and the outer gate electrodes 68R and 62L of the pair of transistors 6R and 6L are connected in the opposite direction. That is, the outer gate electrode 68R is connected to the output terminal 8 side, and the outer gate electrode 62L is connected to the input terminal 2 side.
The current limiting circuit illustrated in FIGS. 1 and 2 limits both the current flowing from the input terminal 2 to the output terminal 8 and the current flowing from the output terminal 8 to the input terminal 2 to a certain current or less. Functions as a bidirectional current limiting circuit.

FIG. 3A shows the relationship between the voltage and current between the drain and source of the NMOS transistor 4R in which a constant voltage is applied between the gate and the outer electrode, and the outer electrode is connected to the output terminal side. ing.
FIG. 3B shows the relationship between the voltage and current between the drain and source of the PMOS transistor 6R in which a constant voltage is applied between the gate and the outer electrode, and the outer electrode is connected to the output terminal side. ing.
As shown by the straight line b1 in FIG. 3B, when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2, the PMOS transistor 6R reduces the energization current below a certain value even if the voltage difference increases. It has the characteristic to limit to. On the other hand, when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2 as indicated by the straight line a2 in FIG. 3A, the conduction current value cannot be limited by the NMOS transistor 4R.
On the other hand, as indicated by the straight line a1 in FIG. 3 (1), the NMOS transistor 4R has an energization current value even when the voltage difference increases when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8. It has a characteristic that limits it below a certain value. On the other hand, when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8, as shown by the straight line b2 in FIG. 3B, the conduction current value cannot be limited by the PMOS transistor 6R.
If the outer gate electrodes of the NMOS transistor 4R and the PMOS transistor 6R are connected in series with the same orientation (in this case, both toward the output terminal side), the voltage at the input terminal 2 becomes higher than the voltage at the output terminal 8. Whether the current is high or low, the energization current value can be limited to a certain current or less.
The same phenomenon can be obtained with the current limiting circuit of FIG.

FIG. 3 (1) also shows the relationship between the drain-source voltage and current of the PMOS transistor 6L in which the outer gate electrode is connected to the input terminal side, and FIG. The relationship between the voltage and current between the drain and source of the NMOS transistor 4L connected to the input terminal side is also shown.
As shown by the straight line b1 in FIG. 3 (2), the NMOS transistor 4L has an energization current below a certain value even when the voltage difference increases when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2. It has the characteristic to limit to. As indicated by the straight line a1 in FIG. 3A, when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8, the PMOS transistor 6L has a constant current value even if the voltage difference increases. It has the following characteristics. If the PMOS transistor 6L and the NMOS transistor 4L are connected in series, the energization current value can be limited to a certain current or less regardless of whether the voltage at the input terminal 2 is higher or lower than the voltage at the output terminal 8. The same phenomenon can be obtained with the current limiting circuit of FIG.
As is apparent from the example of the series connection of the NMOS transistor 4R and the PMOS transistor 6R and the example of the series connection of the NMOS transistor 4L and the PMOS transistor 6L, when the opposite conductivity type MOSs are connected in series, the pair of MOS gate electrodes are the same. The outer electrode may be directed to the input terminal side or may be directed to the output terminal side. Further, the NMOS transistor 4 may be arranged on the input terminal 2 side, or the PMOS transistor 6 may be arranged.

FIG. 3 (1) shows the relationship between the voltage and current between the drain and source of the NMOS transistor 4R in which the outer gate electrode is connected to the output terminal side, and FIG. The relationship between the voltage and current between the drain and source of the NMOS transistor 4L connected to the terminal side is also shown.
As shown by the straight line b1 in FIG. 3 (2), the NMOS transistor 4L has an energization current below a certain value even when the voltage difference increases when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2. It has the characteristic to limit to. As indicated by the straight line a1 in FIG. 3A, the NMOS transistor 4R has a constant current value even when the voltage difference increases when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8. It has the following characteristics. If the outer gate electrodes of the NMOS transistor 4R and the NMOS transistor 4L are connected in series in the opposite direction, the current value can be kept constant regardless of whether the voltage at the input terminal 2 is higher or lower than the voltage at the output terminal 8. The following can be limited.

FIG. 3 (1) also shows the relationship between the drain-source voltage and current of the PMOS transistor 6L in which the outer gate electrode is connected to the input terminal side, and FIG. The relationship between the voltage and current between the drain and source of the PMOS transistor 6R connected to the output terminal side is shown.
As shown by the straight line b1 in FIG. 3B, when the voltage at the output terminal 8 is higher than the voltage at the input terminal 2, the PMOS transistor 6R reduces the energization current below a certain value even if the voltage difference increases. It has the characteristic to limit to. As indicated by the straight line a1 in FIG. 3A, when the voltage at the input terminal 2 is higher than the voltage at the output terminal 8, the PMOS transistor 6L has a constant current value even if the voltage difference increases. It has the following characteristics. If the outer gate electrodes of the PMOS transistor 6R and the PMOS transistor 6L are connected in series in the opposite direction, the energization current value is kept constant regardless of whether the voltage at the input terminal 2 is higher or lower than the voltage at the output terminal 8. The following can be limited.

  The MOS transistor having the characteristics shown in FIG. 3A may be connected to the input terminal side, and the MOS transistor having the characteristics shown in FIG. 3B may be connected to the output terminal side. Conversely, the MOS transistor having the characteristics shown in FIG. 3A may be connected to the output terminal side, and the MOS transistor having the characteristics shown in FIG. 3B may be connected to the input terminal side. In any case, a bidirectional current limiting circuit is obtained.

FIG. 4 shows an application example in which the current limiting circuit 10 of the embodiment is used as the feedback resistor of the operational amplifier 14. In the case of FIG. 4, a two-input two-output operational amplifier 14 is illustrated, and both the feedback resistors 10a and 10b are configured by the current limiting circuit 10 of FIG. In this case, as described with reference to FIG. 6, (Condition 1) the current flows between the NMOS transistor 4R with the outer gate electrode facing the output terminal 8 and the PMOS transistor 6R with the outer gate electrode facing the output terminal 8. It is preferable that the limiting circuits 10 and 10a are configured, and (Condition 2) the connection order of the NMOS transistor 4R and the PMOS transistor 6R in the feedback resistor 10a and the connection order of the NMOS transistor 4R and the PMOS transistor 6R in the feedback resistor 10b be matched. That is, it is preferable to use the current limiting circuit shown in FIGS.
The operational amplifier 14 to which the feedback capacitors 12a and 12b are connected functions as a charge amplifier. When the resistance values of the feedback resistors 10a and 10b are high, the rate at which the output voltage of the charge amplifier 14 changes with the elapsed time can be reduced. For this reason, it is possible to suppress the magnitude of the noise of 1/2 period of the chopper clock generated in the output voltage after demodulation.
If the feedback resistors 10a and 10b are realized by the series circuit of the PMOS transistor 4 and the NMOS transistor 6, the resistance can be adjusted to a high resistance. Therefore, when the charge amplifier 14 is used as a chopper amplifier, noise (chopper) appearing in the output voltage after demodulation. A post-amplification voltage can be obtained that can suppress a change in voltage in synchronization with a half cycle of the clock. In addition, when the NMOS transistor 4R and the PMOS transistor 6R having the outer gate electrode connected to the body facing the output terminal 8 are used, a chopping amplifier that is less susceptible to noise can be realized. Further, when the feedback resistors 10a and 10b are realized by the series circuit of the PMOS transistor 4R and the NMOS transistor 6R connected in the same connection order, the gate-source voltage adjusting circuits 5 and 7 etc. are connected via the MOS transistors 4R and 6R etc. Different currents do not flow through the two input terminals 2 a and 2 b of the operational amplifier 14. For this reason, an unbalanced voltage is not output from the two output terminals 8a and 8b of the operational amplifier 14. When an unbalanced voltage is output from the two output terminals 8a and 8b of the operational amplifier 14, irregularities appearing in the demodulated voltage that fluctuate in a half cycle of the chopper clock. When the feedback resistors 10a and 10b are realized by a series circuit of the NMOS transistor 4R and the PMOS transistor 6R connected in the same connection order, the size of the unevenness generated in the demodulated voltage can be reduced.

FIG. 5 shows the circuit configuration of the gate-source voltage adjusting circuits 5 and 7. Reference numeral 22 denotes a current circuit for supplying a reference current. The gate-source voltage of PMOS (P4) and PMOS (P5) and the gate-source voltage of NMOS (N4) and NMOS (N5) are represented by The current flowing through the resistor R between the drain and source of the PMOS (P4), between the drain and source of the NMOS (N4) becomes the reference value Iref, between the drain and source of the PMOS (P5), and the drain of the NMOS (N5) -Adjust the gate-source voltage so that the current flowing between the sources becomes the reference value Iref. The circuit 22 constitutes a constant current circuit that adjusts the voltage between the gate and the source so that the reference current Iref flows between the drain and the source of the MOS transistor. As will be described later, reference numeral 20 is an activation circuit, and reference numeral 24 is a current mirror circuit.
For the feedback resistors 10a and 10b in FIG. 3, one set of the starting circuit 20 and the constant current circuit 22 in FIG. 5 is used. Further, one current mirror circuit 24 is used for the feedback resistor 10a of FIG. 3, and another current mirror circuit 24 is used for the feedback resistor 10b.

PMOS (P5) and PMOS (P6) constitute a current mirror circuit, and NMOS (N6) and NMOS (N9) constitute a current mirror circuit. FIG. 5B shows the ratio of W / L when the channel width of each MOS transistor is W and the channel length is L. In the current mirror circuit of PMOS (P5) and PMOS (P6), the ratio of W / L is 20: 1, and in the current mirror circuit of NMOS (N6) and NMOS (N9), the ratio of W / L is 1: 0.2. Eventually, a current 1/100 of the current flowing between the drain and source of the PMOS (P5) flows between the drain and source of the NMOS (N9). Since the current flowing between the drain and source of the PMOS (P5) is limited to the reference current Iref by the constant current circuit 22, the current flowing between the drain and source of the NMOS (N9) is also limited to a constant current. . However, the current flowing through the NMOS (N9) is as weak as 1/100 of the reference current Iref flowing through the PMOS (P5). The NMOS (N9) functions as a resistance element having a substantially very large resistance value.
The W / L ratio can be selected as necessary. For example, the W / L ratio of MOS (P5), PMOS (P6), NMOS (N6), and NMOS (N9) may be 20: 0.2: 0.2: 0.2.

PMOS (P5) and PMOS (P6) constitute a current mirror circuit, PMOS (P6) and PMOS (P7) constitute a current mirror circuit, and PMOS (P7) and PMOS (P8) constitute a current mirror circuit. PMOS (P8) and PMOS (P9) constitute a current mirror circuit. In the current mirror circuit of PMOS (P5) and PMOS (P6), the W / L ratio is 20: 1, and in the current mirror circuit of PMOS (P6) and PMOS (P7), the W / L ratio is 1: 1. In the current mirror circuit of PMOS (P7) and PMOS (P8), the W / L ratio is 1: 1, and in the current mirror circuit of PMOS (P8) and PMOS (P9), the W / L ratio is 1: 0.2. Eventually, a current 1/100 of the current flowing between the drain and source of the PMOS (P5) flows between the drain and source of the PMOS (P9). Since the current flowing between the drain and source of the PMOS (P5) is limited to the reference current Iref by the constant current circuit 22, the current flowing between the drain and source of the PMOS (P9) is also limited to a constant current. However, the current flowing through the PMOS (P9) is as weak as 1/100 of the reference current Iref flowing through the PMOS (P5). The PMOS (P9) functions as a resistance element having a substantially very large resistance value.
Again, the W / L ratio can be selected as needed. The current flowing through the PMOS (P9) can be made very weak, and the resistance value of the PMOS (P9) can be increased.

  The circuit 20 is a startup circuit. If the starter circuit 20 is not provided, the gate-source voltage of the PMOS (P4) and PMOS (P5) of the constant current circuit 22 is stabilized at the power supply voltage Vcc when the power is turned on, and the constant current circuit 22 operates in the original operation mode. Don't enter. When the starter circuit 20 is prepared, an operation in which the transistors in the starter circuit 20 are sequentially turned on is obtained, and the gate-source voltage of the PMOS (P4) and PMOS (P5) of the constant current circuit 22 when the power is turned on. Does not stabilize at the power supply voltage Vcc. When the constant current circuit 22 starts to operate in this state, the constant current circuit 22 can enter the original operation mode in which the current flowing through the constant current circuit 22 is adjusted to a constant current.

  In the case of the current limiting circuit shown in FIG. 2, the gate-source voltage adjusting circuit shown in FIG. 5 needs to be modified. In the case of the current limiting circuit shown in FIG. 2, the body of the NMOS transistor N9 shown in FIG. 5 is dropped to the GND voltage. In that case, the body of the NMOS transistor N6 that forms a mirror with N9 is also dropped to the GND voltage. In the case of the current limiting circuit shown in FIG. 2, the body of the PMOS transistor P9 shown in FIG. In this case, the body of P9 and the PMOS transistor P8 constituting the mirror is also set to the Vcc voltage.

As described above, the current limiting circuit of this embodiment can be used to provide a feedback resistor of an operational amplifier, but the application example is not limited thereto. For example, FIG. 7 illustrates a case where a low-pass filter circuit is configured using the current limiting circuit of this embodiment. By using the current limiting circuit, a low-pass filter circuit that outputs from the output terminal 8 a voltage obtained by removing a high frequency from the input voltage at the input terminal 2 can be configured. Reference numeral 30 is a reference voltage line, and 32 is a capacitor.
FIG. 8 illustrates a case where a high-pass filter circuit is configured using the current limiting circuit of this embodiment. A high-pass filter circuit that outputs from the terminal 38 a voltage obtained by removing low frequencies from the input voltage input to the terminal 34 can be configured. Reference numeral 40 is a reference voltage line, and 36 is a capacitor.
4, 7, and 8 exemplify application examples of the current limiting circuit of the present embodiment, and the present invention is not limited to these. Further, when used in the applications of FIGS. 7 and 8, various current limiting circuits illustrated in FIG. 1 can be used. When used in the application of FIG. 4, various current limiting circuits illustrated in FIGS. 6A and 6B can be used.

The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.
The technical scope of the claims described below is not limited to the examples. The examples are merely illustrative.

2: Input terminal 4: NMOS
5: Gate-source voltage adjustment circuit 6: PMOS
7: Voltage adjustment circuit between gate and source 8: Output terminal 10: Feedback resistor 12: Feedback capacitor 14: Operational amplifier

Claims (2)

An NMOS transistor and a PMOS transistor are connected in series between the first input terminal and the first output terminal of the two-input / two-output operational amplifier used in the chopper method, and between the second input terminal and the second output terminal of the operational amplifier. Connected to
Connection order of the NMOS transistor and the PMOS transistor connected between the first input terminal and the first output terminal, and the NMOS transistor and the PMOS connected between the second input terminal and the second output terminal The transistor connection order is the same,
Wherein the output terminal side of the electrodes and the gate electrodes of the MOS transistors, each MOS transistor gate-source voltage adjusting circuit for applying a gate-source voltage to limit the current flowing between the drain and source below a predetermined current charge amplifier but wherein the connected Tei Rukoto. 2. The charge amplifier according to claim 1, wherein the body of each MOS transistor is connected to the gate-source voltage adjustment circuit via the electrode on the output terminal side .

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