JP5754341B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device.

  In a general DRAM, a memory cell is arranged at the intersection of a word line and a bit line, and has a capacitor for storing information and a transistor for reading and writing information. The transistor has a gate connected to the word line, a source connected to the bit line, and a drain connected to the storage node of the capacitor. The capacitor accumulates charges corresponding to stored data in the storage node, and stores the storage. The electrode that opposes the node and the cell plate electrode receive a predetermined voltage. At the time of reading, the electric charge accumulated in the capacitor is transferred to the bit line through the transistor turned on by the selected and driven word line, and the sense amplifier amplifies a minute voltage generated on the bit line.

Also, typical bit line structures of DRAM include an open bit line system and a folded bit line system, and the arrangement of bit lines and sense amplifiers is different. The folded bit line system, a pair of bit lines extending on one side of the sense amplifier, the area of each memory cell 8F ² is the limit. On the other hand, in the open bit line system, a pair of bit lines extend in opposite directions around the sense amplifier, and the area of each memory cell can be 6F ² . The open bit line system is more advantageous than the folded bit line system in that the cell area can be reduced. For example, Patent Documents 1 and 2 adopt the open bit line system.

  On the other hand, when information is read from or refreshed to such a DRAM, malfunction due to noise or the like in the bit line or cell plate electrode is a problem, and countermeasures against noise according to Patent Documents 3 and 4 have been studied. It was.

JP 2010-157289 A JP 2000-260885 A Re-published patent WO00 / 051184 JP 2002-298576 A

  The open bit line method is generally less susceptible to noise than the shielded method. In the amplification operation of the sense amplifier during reading, if the sense amplifier is separated from the supply power source by a long distance, the driven sense amplifier causes the bit line potential to be set to the high potential internal voltage and the low potential due to the internal resistance of the power supply line. When amplifying to the internal voltage, the high-potential internal voltage tends to decrease and the low-potential internal voltage tends to increase due to the drive current. For this reason, the operation margin of the sense amplifier is reduced due to the imbalance of the drive voltages, and a malfunction may occur.

  Therefore, an object of the present invention is to provide a semiconductor memory device in which the influence of power supply noise in the open bit line system is reduced.

The first aspect of the semiconductor memory device is
A plurality of sense amplifiers connected to a pair of bit lines extending on both sides in the column direction, arranged in a row direction orthogonal to the column direction;
A plurality of sense amplifier groups are arranged in the column direction, and a plurality of bit lines connected to the respective sense amplifier groups adjacent to each other in the column direction are arranged in parallel to each other, and the sense amplifier groups are arranged at both ends in the column direction. A plurality of unused bit lines arranged in parallel to a plurality of bit lines at both ends in the column direction of the pair of bit lines connected to each other, a plurality of word lines are wired in a row direction, A memory cell array in which memory cells are arranged at intersections of a plurality of bit lines and the plurality of unused bit lines and the plurality of word lines;
An internal power supply circuit disposed at one end of the memory cell array in the column direction and supplying an internal power supply to the plurality of sense amplifier groups via an internal power supply line;
A semiconductor memory device in which a plurality of unused bit lines arranged at the other end in the column direction of the memory cell array are connected to the internal power supply wiring.

  According to the first aspect of the semiconductor memory device, it is possible to reduce power supply noise generated during the bit line amplification operation by the sense amplifier.

It is a block diagram which shows the structure of DRAM in this Embodiment. 1 is a diagram showing an open bit line type memory cell array in the present embodiment; FIG. It is a diagram showing a layout and a circuit of an open bit line type memory cell in the present embodiment. It is a diagram showing a sense amplifier circuit in the present embodiment. It is a figure which shows the sense amplifier driver circuit in this Embodiment. It is a figure which shows the waveform of the voltage of the bit line in the normal mode in this Embodiment, and a word line. It is a figure which shows the waveform of the voltage of the bit line in the overdrive mode in this Embodiment, and a word line. 1 is a diagram showing an open bit line type memory cell array and an internal power supply circuit in the present embodiment. FIG. 1 is a diagram illustrating a memory cell array in a first embodiment. FIG. It is a figure which shows the waveform of the voltage of the bit line and word line in 1st Embodiment. It is a figure which shows the memory cell array in 2nd Embodiment. It is a figure which shows the memory cell array in 3rd Embodiment. It is a figure which shows the memory cell array in 4th Embodiment. It is a figure which shows the memory cell array in 5th Embodiment. It is a figure which shows the memory cell array in 6th Embodiment. It is a figure which shows the memory cell array in 7th Embodiment. It is a figure which shows the memory cell array in 8th Embodiment. It is a figure which shows the memory cell array in 9th Embodiment. It is a figure which shows the memory cell array in 10th Embodiment. It is a figure which shows the switch circuit in 10th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a DRAM according to the present embodiment. 1 has a clock buffer 2, a command decoder 3, an address buffer 4, an I / O buffer 5, an address controller 6, a burst controller 7, a memory core controller 8, and banks 9-1 to 9-4 on a chip 1. Have

  Each of the banks 9-1 to 9-4 includes a memory cell array 10 in which a plurality of memory cells are arranged in a matrix, a row address controller 11, a column address controller 12, a read amplifier 13, and a write amplifier 14.

  The clock buffer 2 supplies an internal clock signal to each functional block based on the clock signal CLK and the clock enable signal CKE.

  The command decoder 3 is supplied with command signals such as a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and the like according to the command signal active, read, write, refresh, etc. An operation control signal is output to the core controller 8.

  Address buffer 4 receives address signal AD and bank address signal BA in response to a signal from command decoder 3, and outputs an internal address signal and an internal bank address signal.

  The I / O buffer 5 receives write data WD supplied to the data terminal DQ, outputs data CWD described later, and receives data CRD described later and outputs a read signal RD to the data terminal DQ.

  The address controller 6 outputs a row address signal to the row address controller 11 and a column address signal to the burst controller 7 based on the internal address signal from the address buffer 4. Further, the address controller 6 outputs the internal address signal and the internal bank address signal from the address buffer 4 to the memory core controller 8.

  The burst controller 7 uses the column address signal from the address controller 6 as an initial column address, and outputs a column address signal obtained by sequentially incrementing the initial column address according to the burst length to the column address controller 12.

  The memory core controller 8 controls the selection of the bank, the write operation and the read operation of the memory cell array 10 in accordance with the command signal from the command decoder 3, the internal address signal from the address controller 6, and the internal bank signal. Output a signal.

  The row address controller 11 decodes a row address signal from the address controller 6 in order to select a word line of the memory cell array 10.

  The column address controller 12 decodes a column address signal from the burst controller 11 in order to select a bit line of the memory cell array 10.

  The read amplifier 13 reads data in the memory cell in response to a timing signal from the memory core controller 8 and outputs read data CRD.

  The write amplifier 14 receives the output data CWD from the I / O buffer 5 and outputs a write data signal to the memory cell array in response to a timing signal from the memory core controller 8.

  FIG. 2 is a diagram showing an open bit line type memory cell array according to the present embodiment, and corresponds to the memory cell array 10 of FIG.

  In the open bit line system, as shown in FIG. 2, a pair of bit lines BL, / BL are arranged extending in both directions around the sense amplifier unit SA103 in the column direction (horizontal direction in the figure). A plurality (four in the figure) of sense amplifier groups 104 in which the sense amplifier units 103 are arranged in the row direction (vertical direction in the figure) are arranged in the column direction. Each sense amplifier group 104 is supplied with a high potential internal voltage VBLH, a low potential internal voltage VBLL, and an overdrive voltage VOD through a sense amplifier driver SAD102 from a plurality of internal power supply circuits in the memory. Each sense amplifier group 104 is supplied with a precharge voltage VBLP from a precharge voltage generation circuit. The precharge voltage VBLP is, for example, an intermediate voltage between the high potential internal voltage VBLH and the low potential internal voltage VBLL, and the overdrive voltage VOD is a boosted voltage higher than the high potential internal voltage VBLH. The sub word decoder (SWD) 101 decodes the decode signal from the row address controller 11 and drives the sub word line SWL. At both ends 105 and 106 in the column direction of the memory cell array 103, among the bit lines BL and / BL connected to the sense amplifier group 104, a plurality of unused bit lines (dotted lines) parallel to the plurality of bit lines on both ends, respectively. DBL1 and DBL2 are arranged.

  Unused bit lines DBL 1 and DBL 2 at both ends 105 and 106 in the column direction of the memory cell array 10 are not connected to the sense amplifier group 104.

  FIG. 3 is a diagram showing a layout and circuit of an open bit line type memory cell in the present embodiment.

  FIG. 3 (1) is an enlarged view of a part of the left end region 105 of the memory cell array 10 of FIG. Bit lines BL10 to 13 connected to each sense amplifier unit SA103 of the sense amplifier group 104 and unused bit lines DBL14 to 17 that are not connected to the sense amplifier unit SA103 are arranged extending in the column direction (horizontal direction). The sub word lines SWL10 to SWL13 and the dummy word lines ISOWL14 and 15 are arranged extending in the row direction (vertical direction). Memory cells having the region 201 as a unit cell are arranged at intersections of the bit lines BL10 to 13 and the unused bit lines DBL14 to 17 and the sub word lines SWL10 to SWL13. The dummy word lines ISOWLs 14 and 15 are arranged to electrically isolate the source and drain regions of memory cells adjacent in the horizontal direction and are always maintained at the L level.

In (1) of FIG. 3, since there is no sense amplifier group 104 at the left end of the memory cell array, the bit lines BL10 to 13 and the unused bit lines DBL14 to 17 are alternately arranged. However, also in the region between adjacent sense amplifier groups 104, bit lines connected to the respective sense amplifier groups 104 are alternately arranged as shown in the shape of (1) in FIG. By disposing the unit cell regions 201 at all the intersection positions, the size of each memory cell can be 6F ² , thereby realizing a large capacity.

  FIG. 3B is a circuit diagram of the unit cell region 201. The unit cell region 201 includes an N-type cell transistor TR21 and a capacitor 202. The gate of the N-type cell transistor TR21 is connected to the sub word line SWL10, the N-type cell transistor TR21 and the capacitor 202 are connected by the storage node contact 203, and the N-type cell transistor TR21 and the bit line BL10 are connected to the bit line. Connect at 204. A cell plate voltage VCP is applied to the cell plate electrode 205 of the capacitor 202.

  For example, when reading data from the memory cell array 10, when the sub word line SWL10 is selected by the sub word decoder 101, all the N-type cell transistors TR21 at the crossing positions are turned on, and the charges accumulated in the capacitor 202 are transferred to the bit lines BL10-13. And the voltages of the bit lines BL10 to BL13 are increased or decreased by a minute voltage ΔV depending on the presence or absence of charge in the capacitor.

  FIG. 4 is a diagram showing a sense amplifier circuit in the present embodiment. The sense amplifier unit 103 in FIG. 4 includes a sense amplifier circuit 401, a precharge circuit 402, and a column gate circuit 403, and a pair of bit lines BL and / BL extend in the opposite direction with the sense amplifier unit 103 as a center.

  The sense amplifier circuit 401 has P-type transistors TR41 and 42 and N-type transistors TR43 and 44 constituting a latch circuit. The P-type transistors TR41 and TR42 are overdriven voltage VOD or high potential internal voltage VBLH from the sense amplifier driver 102. Is supplied as the sense amplifier drive signal PSA, and the N-type transistors TR43 and 44 are supplied with the low potential internal voltage VBLL as the sense amplifier drive signal NSA. When a minute voltage difference ΔV is generated in the bit lines BL and / BL in response to the rise of the sub word line, the sense amplifier circuit 401 uses the sense amplifier drive signal PSA to change the voltage of the bit line on the higher potential side to the overdrive voltage. It is driven to VOD or the high potential internal voltage VBLH, and the voltage on the lower bit line is driven to the low potential internal voltage VBLL by the sense amplifier drive signal NSA to amplify the voltage difference.

  The precharge circuit 402 includes N-type transistors TR45 to 47, and is supplied with the precharge voltage VBLP from the precharge voltage generation circuit. The equalize signal EQL is supplied to the gates of the N-type transistors TR45 to 47, and the precharge circuit 402 short-circuits the bit lines BL and / BL in response to the equalize signal EQL at the H level and the precharge voltage. Maintain at VBLP.

  The column gate circuit 403 has column selection gates TR48 and 49 composed of N-type transistors, and a column selection signal CL is supplied to each gate. In addition, the column gate circuit 403 turns on the column selection gates TR48 and 49 in response to the column selection signal CL at the H level and supplies the amplified bit line voltage to the read amplifier 13 via the local data buses LDB and / LDB. Output to.

  FIG. 5 is a diagram showing a sense amplifier driver circuit in the present embodiment. (1) in FIG. 5 is a sense amplifier driver 102 when the high potential internal voltage VBLH and the low potential internal voltage VBLL are used (hereinafter referred to as a normal operation mode). On the other hand, (2) in FIG. 5 shows the sense amplifier driver 102 when the overdrive method is adopted (hereinafter referred to as an overdrive mode).

  In FIG. 5A, the sense amplifier driver 102 includes an inverter 501, a P-type transistor TR51, and an N-type transistor TR52. In response to the H level of the sense amplifier enable signal SAEZ, the sense amplifier drive signal PSA is driven to the H level with the high potential internal voltage VBLH, and the sense amplifier drive signal NSA is driven to the L level with the low potential internal voltage VBLL.

  In FIG. 5 (2), the sense amplifier driver 102 includes a high voltage drive circuit 502 and a low voltage drive circuit 503. The high voltage drive circuit 502 includes N-type transistors TR54 and 55, and the N-type transistors TR54 and 55 are supplied with sense amplifier enable signals SAEOZ and SAEAZ at their gates, respectively. In response to the H level of the sense amplifier enable signal SAEOZ, the N-type transistor TR54 is turned ON to drive the sense amplifier drive signal PSA with the overdrive voltage VOD, and after a predetermined time has passed, the N-type transistor TR54 is turned OFF to sense In response to the H level of the amplifier enable signal SAEAZ, the N-type transistor TR55 is turned on to drive the sense amplifier drive signal PSA with the high voltage VBLH. On the other hand, the low voltage drive circuit 503 has an N-type transistor TR56, and a sense amplifier enable signal SAEZ is supplied to the gate of the N-type transistor TR56. The low voltage drive circuit 503 drives the sense amplifier drive signal NSA with the low potential internal voltage VBLL in response to the H level of the sense amplifier enable signal SAEZ. In addition, this is an example of a structure and is not limited to this. For example, TR54 may be a P-type transistor, and SAEOZ may be a reverse phase signal.

  FIG. 6 is a diagram showing the voltage waveforms of the bit line and the word line in the normal mode in this embodiment. The waveforms in FIG. 6 show changes in the voltages of the bit line and the word line when data is read from the memory cell array shown in FIGS.

  Waveforms BL10-1 and / BL10-1 shown by solid lines in FIG. 6 are in the normal operation mode using the high potential internal voltage VBLH and the low potential internal voltage VBLL by the sense amplifier driver 102 of FIG. Is a waveform of a pair of bit lines BL10-1 and / BL10-1. First, the sub-word line SWL10 of the voltage VWLL in the non-selected state is driven by the sub-word driver 101, the N-type cell transistor TR21 of the memory cell in (2) of FIG. 3 is turned on, and the charge accumulated in the capacitor 202 is transferred to the bit line. It is distributed to BL10-1. As a result, a voltage difference ΔV occurs at time T1 between the bit lines BL10-1 and / BL10-1 that were both at the precharge voltage VBLP at time T0. Further, in response to the rise of the sense amplifier enable signal SAEZ at time T1, the sense amplifier drive signal PSAn driven to the H level by the high potential internal voltage VBLH from the sense amplifier driver 102 in FIG. The sense amplifier drive signal NSA driven to the L level by the internal voltage VBLL is supplied to the sense amplifier circuit 401 in FIG. 4, and the sense amplifier circuit 401 starts an amplification operation. As a result, the bit line BL10-1 is driven to the high potential internal voltage VBLH, and the bit line / BL10-1 is driven to the low potential internal voltage VBLL. The column gate circuit 403 outputs the voltage difference between the amplified bit lines BL and / BL to the read amplifier 13 via the local data buses LDB and / LDB. When the sense amplifier enable signal SAEZ falls to the L level at time T3 after the sub word line SWL10 is lowered, in response to the rise of the equalize signal EQL, the precharge circuit 402 causes the pair of bit lines BL10-1,. BL10-1 is short-circuited and precharged to the precharge voltage VBLP.

  FIG. 7 is a diagram showing voltage waveforms of the bit line and the word line in the overdrive mode in the present embodiment. Waveforms BL10-2 and / BL10-2 represented by solid lines in FIG. 7 are waveforms of a pair of bit lines BL10-2 and / BL10-2 in the overdrive mode, and a waveform PSAo represented by a broken line is 6 is a waveform corresponding to the PSA in FIG. 5B in the overdrive mode. Unlike the normal operation mode, in this case, the sense amplifier drive signal PSA driven to the H level by the overdrive voltage VOD from the sense amplifier driver 102 in response to the sense amplifier enable signals SAEOZ and SAEZ at time T1, and the low potential The sense amplifier drive signal NSA driven to the L level by the internal voltage VBLL is supplied to the sense amplifier circuit 401, and the sense amplifier circuit 401 starts amplification of the minute voltage ΔV. Thereby, the sense amplifier circuit 401 drives the bit line BL10-2 to the overdrive voltage VOD and drives the bit line / BL10-2 to the low potential internal voltage VBLL faster than in the normal operation mode. When the sense amplifier enable signal SAEOZ falls to L level and the sense amplifier enable signal SAEAZ rises to H level at time T2, the sense amplifier drive signal PSA is driven to the high potential internal voltage VBLH by the sense amplifier driver 102, and the bit line BL10 -2 is driven to the high potential internal voltage VBLH.

  In this way, when one of the sub word lines arranged in the row direction of the memory cell array 10 is driven by the sub word driver 101, the sense amplifier group 104, that is, the sub word line connected to the bit line crossing the sub word line is set. The two sense amplifier groups 104 sandwiched respectively perform the voltage line amplifying operation in the normal operation mode or the overdrive mode.

  However, in this amplification operation, an imbalance occurs in the drive voltage supplied from the internal power supply circuit in the memory to the sense amplifier group 104, that is, VOD-VBLP or VBLH-VBLP and VBLP-VBLL due to power supply noise. As described above, when the sub word line SWL10 is selected by the sub word driver 101 and the bit line BL is boosted by a minute voltage ΔV from / BL, the amplification operation is performed in the sense amplifier unit 103 supplied with the sense amplifier drive signals PSA and NSA. Is called. Specifically, since the gate-source voltage of the PMOS transistor TR42 of the sense amplifier circuit 401 of FIG. 4 is higher than TR41, the internal power supply of the overdrive voltage VOD or the high potential internal voltage VBLH is supplied via the sense amplifier driver 102. A drive current flows from the circuit to the bit line BL, and the voltage of the bit line BL rises. Further, since the gate-source voltage of the N-type transistor TR43 is higher than TR44, the drive current flows from the bit line / BL to the internal power supply circuit of the low potential internal voltage VBLL via the sense amplifier driver 102, and the bit line The voltage of / BL drops. At this time, as the distance between each internal power supply circuit and the sense amplifier driver 102 increases, the resistance of the internal power supply wiring connecting each internal power supply circuit and the sense amplifier driver 102 increases. Therefore, internal power supply noise that temporarily decreases the overdrive voltage VOD or the high potential internal voltage VBLH supplied to the sense amplifier circuit 401 becomes large, and the low potential internal voltage VBLL temporarily increases. Internal power supply noise increases. As an example, FIG. 8 will be described.

  FIG. 8 is a diagram showing an open bit line type memory cell array and an internal power supply circuit in the present embodiment. In the memory cell array 10 of FIG. 8, internal power supply circuits 701 and 703 for generating a low potential internal voltage VBLL and a high potential internal voltage VBLH are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. Low potential internal voltage VBLL and high potential internal voltage VBLH are supplied to each sense amplifier driver 102 via internal power supply wirings 702 and 704, respectively.

  The sense amplifier group 104 at the left end in the column direction of the memory cell array 10 is farthest from the internal power supply circuit 703 and has a large resistance because the internal power supply wiring 704 is long. As a result, at the time of amplification operation, the high potential internal voltage VBLH supplied to the leftmost sense amplifier group 104 via the internal power supply wiring 704 temporarily decreases greatly. On the other hand, the leftmost sense amplifier group 104 is closest to the internal power supply circuit 701, and the internal power supply wiring 702 is short and has a low resistance. Therefore, the low potential internal power supplied via the internal power supply wiring 702 is low. The noise of the voltage VBLL is small. Therefore, in the sense amplifier group 104 at the left end, the boost level (VBLH) with respect to the precharge voltage VBLP is smaller than the step-down level (VBLL) with respect to the precharge voltage VBLP. Is likely to malfunction in reverse logic.

  Similarly, the sense amplifier group 104 at the right end in the column direction of the memory cell array 10 has small power supply noise of the high potential internal voltage VBLH, but large power supply noise of the low potential internal voltage VBLL, and similarly has an imbalance in the drive voltage. May cause malfunction.

  As described above, the drive voltage imbalance is caused by the power supply noise, so that the operation margin of the sense amplifier is reduced. If the bit line BL or / BL is further affected by the coupling noise of the bit line adjacent in the row direction of the memory cell array 10 during the amplification operation, the voltage levels of the bit lines BL and / BL are reversed to cause the malfunction of the DRAM. Is likely to be caused.

  Therefore, in the following embodiments, a semiconductor memory device with reduced power supply noise will be described in view of the above.

[First Embodiment]
FIG. 9 is a diagram showing the memory cell array in the first embodiment. In the memory cell array 10 of FIG. 9, internal power supply circuits 801 and 803 for generating a low potential internal voltage VBLL and a high potential internal voltage VBLH are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. Low potential internal voltage VBLL and high potential internal voltage VBLH are supplied to each sense amplifier driver 102 via internal power supply lines 802 and 804, respectively. The leftmost unused bit line DBL1 is connected to the internal power supply wiring 804 of the rightmost internal power supply circuit 803, and the rightmost unused bit line DBL2 is connected to the internal power supply wiring 802 of the leftmost internal power supply circuit 801. With this configuration, the wiring capacities of the unused bit lines DBL1 and DBL2 at the opposite ends of the internal power supply circuits 803 and 801 from the internal power supply circuits 803 and 801 through the internal power supply wirings 804 and 802 are respectively set to the high potential internal voltage VBLH, Charged to the low potential internal voltage VBLL, operates as a power supply capacitor for each internal voltage VBLH, VBLL, and absorbs power supply noise at both ends of each internal voltage VBLH, VBLL.

  As an example of the operation of the memory cell array shown in FIG. 9, the operation in the normal operation mode will be described. FIG. 10 is a diagram showing the voltage waveforms of the bit line and the word line in the first embodiment.

  10, in the normal operation mode, a pair of bit lines BL10-3 connected to the leftmost sense amplifier group 104 when the sub word line SWL10 in the leftmost memory cell array in the column direction (horizontal direction) of FIG. 9 is selected. , / BL 10-3, the unused bit line DBL 1 and the high potential internal voltage VH supplied to the sense amplifier group 104. The solid line is the waveform of the bit lines BL10-3 and / BL10-3, the thick line is the waveform of the unused bit line DBL1, and the broken line is the waveform of the high potential internal voltage VH supplied to the sense amplifier group 104.

  When the sub-word line SWL10 is driven by the sub-word driver 101 at time T10 and rises from the non-selection voltage VWLL to the boost voltage VWLH, the N-type cell transistor TR21 of the memory cell (2) in FIG. The charged charges are distributed to the bit line BL10-3. As a result, a voltage difference ΔV occurs at time T11 between the bit lines BL10-3 and / BL10-3, both of which are at the precharge voltage VBLP. Further, since the sub-word line SWL10 is driven, the N-type cell transistor TR21 of the unused cell disposed at the intersection of the unused bit line DBL1 and the sub-word line SWL10 is turned on. Charge flows into the capacitor 202 of the unused cell via 804 and the unused bit line DBL1. Under this influence, the voltage of the unused bit line DBL1 and the internal power supply wiring 804 connected thereto slightly drops from the high potential internal voltage VBLH when the sub word line SWD10 rises, but the electric power is supplied from the internal power supply circuit 803. Therefore, the high potential internal voltage VBLH is obtained again.

  At time T11, in response to the rise of the sense amplifier enable signal SAEZ, the sense amplifier driver signal 102 in FIG. 5 (1) causes the sense amplifier drive signal PSA to rise to the high potential internal voltage VBLH, and the sense amplifier drive signal NSA becomes low potential. Falling to the internal voltage VBLL, the amplification operation of the sense amplifier circuit 401 in FIG. 4 starts. At this time, the voltage supplied from the internal power supply wiring 804 to the leftmost sense amplifier group 104 in FIG. 9 by the current due to the driving operation of the sense amplifier circuit 401 decreases as shown by the waveform N (chain line). The drive voltages VBLH-VBLP 401 and VBLP-VBLL 401 may be unbalanced and the operation may be reversed. However, in the example according to the present embodiment, the sense amplifier group is connected from the internal power supply wiring 804 to the unused bit line DBL1 adjacent to the leftmost sense amplifier group 104 and the capacitor 202 of the unused cell at time ΔT. A decrease in the internal voltage supplied to 104 is reduced, and malfunction of the sense amplifier is suppressed. The voltage of the unused bit line DBL1 is slightly lower than the high potential internal voltage VBLH during the time ΔT, but since the charge is supplied from the internal power supply 803, the voltage becomes the high potential internal voltage VBLH again.

  At time T12, the sub word line SWL10 is deselected, and at time T13, the N-type cell transistor TR21 of the unused cell is turned off. Even after the sub-word line SWL10 is in a non-selected state, the unused bit line DBL1 is connected to the internal power supply circuit 803 via the internal power supply wiring 804, and thus remains driven to the high potential internal voltage VBLH.

  When the sense amplifier enable signal SAEZ falls to the L level at time T14, the operation of the sense amplifier circuit 401 stops, and in response to the rise of the equalize signal EQL, the precharge circuit 402 causes the pair of bit lines BL10-3, / BL10-3 is precharged to the precharge voltage VBLP.

  As described above, in the memory cell array 10 of FIG. 9, the unused bit line DBL1 is supplied from the unused bit line DBL1 and the unused cell capacitor 202 from time T10 to T13 before the time T10 and after the time T13. Acts as a stabilizing capacity.

  Therefore, when the voltage supplied from the internal power supply wiring 804 is reduced by the drive current when the sense amplifier unit 103 drives the bit line pair due to the rise of the sense amplifier enable signal SAEZ, the unused bit line DBL1 and the unused cell capacitor 202 acts as a power stabilization capacitor, and the voltage drop can be suppressed.

  The unused bit line DBL2 at the right end of the memory cell array 10 and the capacitor 202 of the unused cell connected to the internal power supply circuit 801 of the low potential internal voltage VBLL also act as a power stabilization capacitor on the same principle as described above. In addition, it is possible to reduce power supply noise (rising of the low potential internal voltage VBLL) generated when the bit line / BL10-3 is stepped down to the low potential internal voltage VBLL.

  As described above, by using the unused bit line or the capacitor 202 of the unused cell as the power source stabilization capacitor, the power source noise can be reduced and the drive voltage imbalance of the sense amplifier unit 103 can be prevented.

[Second Embodiment]
When the low potential internal voltage VBLL is a ground power supply, the low potential internal voltage VBLL is usually used not only for the sense amplifier driver 102 but also for other functional circuits such as the row address controller 11. The internal power supply wiring of the internal power supply circuit that generates the voltage VBLL is stretched over the chip 1. Therefore, the resistance of the internal power supply wiring of the internal power supply circuit that generates the low potential internal voltage VBLL is low, and the power supply noise when the sense amplifier circuit 401 of FIG. 4 amplifies the bit line / BL to the low potential internal voltage VBLL is small.

  On the other hand, the high-potential internal voltage VBLH and the overdrive voltage VOD have limited uses, and the internal power supply wiring of each internal power supply circuit is arranged in a limited area. Therefore, compared with the low potential internal voltage VBLL, the resistance of the internal power supply wiring of the internal power supply circuit that generates the high potential internal voltage VBLH and the overdrive voltage VOD is large, and the sense amplifier circuit 401 in FIG. The power supply noise when amplifying to the internal voltage VBLH or the overdrive voltage VOD is also large. Therefore, in the second embodiment, an internal power supply circuit having a high potential internal voltage VBLH or an overdrive voltage VOD is used.

  FIG. 11 is a diagram illustrating a memory cell array according to the second embodiment. In the memory cell array 10 of FIG. 11, internal power supply circuits 1001 and 1003 for generating a high potential internal voltage VBLH and an overdrive voltage VOD are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. A high potential internal voltage VBLH and an overdrive voltage VOD are supplied to each sense amplifier driver 102 via power supply lines 1002 and 1004, respectively. The leftmost unused bit line DBL1 is connected to the internal power supply wiring 1004, and the rightmost unused bit line DBL2 is connected to the internal power supply wiring 1002. With this configuration, the wiring capacities of the unused bit lines DBL1 and DBL2 at the opposite ends of the internal power supply circuits 1003 and 1001 from the internal power supply circuits 1003 and 1001 through the internal power supply wirings 1004 and 1002, respectively, are overdrive voltage VOD, high It is charged to the potential internal voltage VBLH, operates as a power supply capacitor of each internal voltage VOD, VBLH, and absorbs power supply noise of each internal voltage VOD, VBLH. In FIG. 11, the internal power supply wiring of the low potential internal voltage VBLL is omitted.

  As described above, in the second embodiment, the power supply noise of the high potential internal voltage VBLH and the overdrive voltage VOD can be reduced, and the drive voltage imbalance can be prevented.

[Third Embodiment]
FIG. 12 is a diagram illustrating a memory cell array according to the third embodiment. In the memory cell array 10 of FIG. 12, internal power supply circuits 1101 and 1103 for generating a low potential internal voltage VBLL and an overdrive voltage VOD are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. Low potential internal voltage VBLL and overdrive voltage VOD are supplied to each sense amplifier driver 102 via power supply wirings 1102 and 1104, respectively. The leftmost unused bit line DBL1 is connected to the internal power supply wiring 1104 of the rightmost internal power supply circuit 1103, and the rightmost unused bit line DBL2 is connected to the internal power supply wiring 1102 of the leftmost internal power supply circuit 1101. With this configuration, the wiring capacities of the unused bit lines DBL1 and DBL2 at the opposite ends of the internal power supply circuits 1103 and 1101 from the internal power supply circuits 1103 and 1101 through the internal power supply wirings 1104 and 1102 are respectively overdrive voltage VOD and low. It is charged to the potential internal voltage VBLL, operates as a power supply capacitor for each internal voltage VOD, VBLL, and absorbs power supply noise at both ends of each internal voltage VOD, VBLL.

  As described above, in the third embodiment, it is possible to reduce the power supply noise of the low potential internal voltage VBLL and the overdrive voltage VOD and prevent the drive voltage from being unbalanced. Therefore, unlike the second embodiment, the power supply noise of the low potential internal voltage VBLL is large, and the sense amplifier circuit 401 in FIG. 4 amplifies the voltage levels of the bit lines BL and / BL quickly in the overdrive mode. In the case where priority is given to doing this, the third embodiment is suitable.

[Fourth Embodiment]
FIG. 13 shows a memory cell array according to the fourth embodiment. In the memory cell array 10 of FIG. 13, internal power supply circuits 1201 and 1202 for generating an overdrive voltage VOD and a high potential internal voltage VBLH are arranged at the left end in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. An internal power supply circuit 1204 for generating a low potential internal voltage VBLL is arranged in each sense amplifier driver, and the overdrive voltage VOD, the high potential internal voltage VBLH, and the low potential internal voltage VBLL are supplied to the sense amplifier drivers via the internal power supply lines 1205, 1203, and 1206, respectively. 102. The leftmost unused bit line DBL1 is connected to the internal power supply wiring 1206 of the rightmost internal power supply circuit 1204, and the rightmost unused bit line DBL2 is connected to the internal power supply wiring 1205 of the leftmost internal power supply circuit 1201 and The unused bit line DBL3 is connected to the internal power supply wiring 1203 of the leftmost internal power supply circuit 1202. That is, since the internal power supply circuits 1201 and 1202 are arranged at the left end, the unused bit lines at the right end are divided into two sets of DBL2 and DBL3, and are connected to the internal power supply circuits 1201 and 1202, respectively.

  With this configuration, the wiring capacity of the unused bit lines DBL1, DBL2, DBL3 at the opposite ends of the internal power supply circuits 1204, 1201, 1202 from the internal power supply circuits 1204, 1201, 1202 via the internal power supply wirings 1206, 1205, 1203. Are respectively charged to a low potential internal voltage VBLL, an overdrive voltage VOD, and a high potential internal voltage VBLH, and operate as power capacitors of the internal voltages VBLL, VOD, and VBLH. Absorbs power supply noise.

  As described above, in the fourth embodiment, all the power supply noises of the high potential internal voltage VBLH, the overdrive voltage VOD, and the low potential internal voltage VBLL can be reduced to prevent the drive voltage from being unbalanced.

  Further, the arrangement of the internal power supply circuits of the overdrive voltage VOD, the high potential internal voltage VBLH, and the low potential internal voltage VBLL is not limited to that shown in FIG. 13, and the internal power supply circuit is changed according to the power noise level of each internal voltage. It can also be arranged. For example, when the power supply noise of the overdrive voltage VOD is larger than the power supply noise of the high potential internal voltage VBLH and the low potential internal voltage VBLL, the internal power supply circuit of the overdrive voltage VOD uses the power stabilization capacitance of the unused bit line. It is desirable to obtain the most advantageous effects. Therefore, in such a case, an internal power supply circuit of the high potential internal voltage VBLH and the low potential internal voltage VBLL is arranged at the left end, and an internal power supply circuit of the overdrive voltage VOD is arranged at the right end. The internal power supply circuit of the high potential internal voltage VBLH and the low potential internal voltage VBLL is connected to the unused bit line on the right end, and the internal power supply circuit of the overdrive voltage VOD is connected to all the unused bit lines on the left end.

  In FIG. 13, the unused bit lines DBL2 and DBL3 at the right end of the memory cell array 10 have DBL3, / BL, DBL2, / BL, DBL3, / BL, DBL2. Although it intersects with the sub word line SWL alternately, it is not limited to this. For example, DBL2, / BL, DBL2, / BL, DBL2, / BL, DBL3, / BL, DBL3, / BL, DBL3, etc. are arranged so that unused bit lines DBL2 and DBL3 are switched every other number. Alternatively, an unused bit line DBL2 may be arranged in the upper half in the row direction (vertical direction) of the memory cell array 10, and an unused bit line DBL3 may be arranged in the lower half. .

[Fifth Embodiment]
FIG. 14 is a diagram illustrating a memory cell array according to the fifth embodiment. In the memory cell array 10 of FIG. 14, internal power supply circuits 1301 and 1303 for generating a high potential internal voltage VBLH and an overdrive voltage VOD are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. A high potential internal voltage VBLH and an overdrive voltage VOD are supplied to each sense amplifier driver 102 via power supply wirings 1302 and 1304, respectively. The leftmost unused bit line DBL1 and the rightmost unused bit line DBL2 are connected to the internal power supply wiring 1302 of the leftmost internal power supply circuit 1301, and the leftmost unused bit line DBL3 and the rightmost unused bit line DBL4 are connected to the rightmost end. Are connected to the internal power supply wiring 1304 of the internal power supply circuit 1303. With this configuration, the wiring capacity of the unused bit lines DBL1 and DBL2 is charged to the high potential internal voltage VBLH from the internal power supply circuit 1301 via the internal power supply wiring 1302, and operates as a power supply capacitor of the high potential internal voltage VBLH. Absorbs power supply noise of internal voltage VBLH. Also, the wiring capacity of the unused bit lines DBL3 and DBL4 is charged to the overdrive voltage VOD from the internal power supply circuit 1303 via the internal power supply wiring 1304, and operates as a power supply capacitor of the overdrive voltage VOD. Absorbs power supply noise.

  In this way, by connecting the internal power supply circuit and the unused bit lines at both ends, the power supply stabilization capacity of the unused bit lines and unused cells can be detected even for sense amplifier groups near the internal power supply circuit. Thus, the internal voltage VBLH and VOD can be prevented from dropping.

  Note that the arrangement of the unused bit lines DBL1 to DBL4 is not limited to FIG. In FIG. 14, the unused bit lines DBL1 and DBL3 at the left end of the memory cell array 10 are alternately sub-word lines SWL with DBL3, BL, DBL1, BL, DBL3, BL, DBL1,. It intersects but is not limited to this. For example, DBL1, BL, DBL1, BL, DBL3, BL, DBL3, etc. are arranged so that the unused bit lines DBL2 and DBL3 are switched every other number, or in the row direction (vertical direction) of the memory cell array 10. It is also possible to arrange an unused bit line DBL3 in the upper half and an unused bit line DBL1 in the lower half. The same can be said for the unused bit lines DBL2 and DBL4 at the right end.

  Furthermore, the combination of the connection between the internal power supply circuit and the unused bit line is not limited to the arrangement shown in FIG. For example, the leftmost internal power supply circuit 1301 is connected to the rightmost unused bit line DBL2, the rightmost internal power supply circuit 1303 is connected to the leftmost unused bitlines DBL1 and DBL3, and the rightmost unused bitline DBL4. The power supply stabilization capacity on the overdrive voltage VOD side of the internal power supply circuit 1303 can be increased and the power supply noise can be further reduced.

[Sixth Embodiment]
FIG. 15 is a diagram showing a memory cell array in the sixth embodiment. FIG. 15 is obtained by replacing the internal power supply circuit 1303 that generates the overdrive power supply VOD of FIG. 14 with an internal power supply circuit 1403 that generates the low potential internal voltage VBLL.

  With this configuration, the wiring capacity of the unused bit lines DBL1 and DBL2 is charged to the high potential internal voltage VBLH via the internal power supply wiring 1402 from the internal power supply circuit 1401 that generates the high potential internal voltage VBLH. It operates as a power supply capacitor and absorbs power supply noise of the high potential internal voltage VBLH. Also, the wiring capacity of the unused bit lines DBL3 and DBL4 is charged to the low potential internal voltage VBLL from the internal power supply circuit 1403 that generates the low potential internal voltage VBLL via the internal power supply wiring 1404. It operates as a capacitor and absorbs power supply noise of the low potential internal voltage VBLL.

  Therefore, as in the fifth embodiment, by connecting the internal power supply circuit and the unused bit lines at both ends, the unused bit lines and the sense amplifier groups near the internal power supply circuit are also connected. There is an effect of power supply stabilization capacity of unused cells, and power supply noise of the internal voltages VBLH and VBLL can be prevented.

  Note that the arrangement of the unused bit lines DBL1 to DBL4 and the combination of the connection between the internal power supply circuit and the unused bit line are not limited to those in FIG. 15 as in the fifth embodiment.

[Seventh Embodiment]
FIG. 16 is a diagram illustrating a memory cell array according to the seventh embodiment. In the memory cell array 10 of FIG. 16, internal power supply circuits 1501 and 1503 for generating a high potential internal voltage VBLH are arranged at both ends in the column direction (horizontal direction) of the memory cell array 10 shown in FIG. The high potential internal voltage VBLH is supplied to each sense amplifier driver 102 through the. The unused bit line DBL1 at the left end and the unused bit line DBL2 at the right end are both connected to the internal power supply lines 1502 and 1504. With this configuration, the wiring capacity of the unused bit lines DBL1, DBL2 is charged to the high potential internal voltage VBLH from the internal power supply circuits 1501, 1503 via the internal power supply wirings 1502, 1504, and operates as a power supply capacitor of the high potential internal voltage VBLH. Then, the power supply noise of the high potential internal voltage VBLH is absorbed.

  Therefore, in the seventh embodiment, for example, the power supply noise of the high potential internal voltage VBLH is larger than those of the other internal power supplies VOD and VBLL, and the opposite ends of the internal power supply circuit and the internal power supply circuit as shown in FIG. The power supply noise cannot be reduced only by connecting to the unused bit line, and is suitable when a large amount of power stabilization capacitance is required for the high potential internal voltage VBLH.

[Eighth Embodiment]
FIG. 17 shows a memory cell array according to the eighth embodiment. FIG. 17 is obtained by replacing the internal power supply circuits 1501 and 1503 of FIG. 16 with internal power supply circuits 1601 and 1603 for generating the low potential internal voltage VBLL. With this configuration, the wiring capacity of the unused bit lines DBL1 and DBL2 is charged to the low potential internal voltage VBLL from the internal power supply circuits 1601 and 1603 via the internal power supply wirings 1602 and 1604, and operates as a power supply capacitor of the low potential internal voltage VBLL. The power supply noise of the low potential internal voltage VBLL is absorbed.

  Therefore, in the eighth embodiment, for example, the power supply noise of the low-potential internal voltage VBLL is larger than those of the other internal power supplies VBLH and VOD, and the end on the opposite side of the internal power supply circuit and the internal power supply circuit as shown in FIG. The power supply noise cannot be reduced simply by connecting to the unused bit line, and this is suitable when a large amount of power stabilization capacitance is required for the low potential internal voltage VBLL.

[Ninth Embodiment]
FIG. 18 is a diagram showing a memory cell array in the ninth embodiment. FIG. 18 is obtained by replacing the internal power supply circuits 1501 and 1503 of FIG. 16 with internal power supply circuits 1701 and 1703 that generate the overdrive voltage VOD. With this configuration, the wiring capacity of the unused bit lines DBL1, DBL2 is charged to the overdrive voltage VOD from the internal power supply circuits 1701, 1703 via the internal power supply wirings 1702, 1704, and operates as a power supply capacitor of the overdrive voltage VOD. Absorbs power supply noise of overdrive voltage VOD.

  Therefore, in the ninth embodiment, for example, the power supply noise of the overdrive voltage VOD is larger than that of the other internal power supplies VBLH and VBLL, and the internal power supply circuit and the internal power supply circuit at the opposite end as shown in FIG. The power supply noise cannot be reduced only by connecting to an unused bit line, which is suitable when a large amount of power stabilization capacitance is required for the overdrive voltage VOD.

[Tenth embodiment]
In the first to ninth embodiments described above, the unused bit line is connected to the internal power supply wiring, and the unused bit line is used as the power stabilization capacitor. However, in a stress test performed before the shipment of DRAM, unused bit lines at both ends in the column direction (horizontal direction) of the memory cell array 10 are detected according to the test case in order to detect a short-circuit portion between the bit lines. It is also required to be able to drive with voltage. Therefore, in the tenth embodiment, a switch circuit is arranged between the unused bit line and the internal power supply wiring, and the connection between the unused bit line and the internal power supply wiring is released at an arbitrary voltage during the stress test. Be able to drive.

  FIG. 19 is a diagram showing a memory cell array according to the tenth embodiment. The memory cell array 10 of FIG. 19 is configured by arranging switch circuits SW1 and SW2 at both ends in the column direction (horizontal direction) of the memory cell array shown in FIG. Switch circuits SW1 and SW2 connect internal power supply wirings 1804 and 1802 to unused bit lines DBL1 and DBL2. Therefore, when the switches of the switch circuits SW1 and SW2 are ON, the unused bit lines DBL1 and DBL2 operate as power capacitors of the internal voltages VOD and VBLH, and absorb power noise of the internal voltages VOD and VBLH. On the other hand, when performing a test such as a stress test, the switch circuits SW1 and SW2 release the connection between the internal power supply wirings 1804 and 1802 and the unused bit lines DBL1 and DBL2, and test the unused bit lines DBL1 and DBL2. Drive with a voltage according to the case.

  FIG. 20 is a diagram illustrating a switch circuit according to the tenth embodiment. The switch circuit of FIG. 20 includes a NOR gate 1901, NAND gates 1902-1904, inverters 1905, 1906, P-type transistors TR191, TR192, and N-type transistors TR193, TR194. The switch circuit SW1 of FIG. Appears. The sources of the P-type transistors TR191 and TR192 are connected to an internal power supply circuit that generates an overdrive voltage VOD and a high potential internal voltage VBLH, and the sources of the N-type transistors TR193 and TR194 are a precharge voltage generation circuit, a low potential The internal voltage VBLL is connected to an internal power supply circuit for generating. The test signal TEST controls the connection between the unused bit line DBL1 and the internal power supply wiring 1804, and the test voltage selection signals TS1 and TS2 are not used when the connection between the unused bit line DBL1 and the internal power supply wiring 1804 is released. The drive voltage of the used bit line DBL1 is controlled to any one of the high potential internal voltage VBLH, the precharge voltage VBLP, and the low potential internal voltage VBLL.

  For example, when the unused bit line DBL1 is used as a power supply stabilization capacitor, the test signal TEST is set to L level, the P-type transistor TR191 is turned on, and the unused bit line DBL1 is connected to the overdrive voltage VOD. In the stress test, the test signal TEST is set to H level to turn off the P-type transistor TR191 in order to release the connection between the unused bit line DBL1 and the internal power supply wiring 1804. When the test voltage signals TS1 and TS2 are set to H level and L level, respectively, the unused bit line DBL1 is driven by the high potential internal voltage VBLH. If the test voltage signals TS1 and TS2 are both at the L level, the unused bit line DBL1 is driven by the precharge voltage VBLP. If the test voltage signals TS1 and TS2 are at the L level and the H level, the low potential internal voltage is set. Drive with VBLL.

  As described above, the switch circuit SW1 connects the unused bit lines to the internal power supply wiring of the internal power supply circuit that generates the overdrive voltage VOD, and at the time of the stress test, the unused bit lines are connected to the internal voltages VBLH, VBLP, VBLL. Either can be driven.

  Also for the switch circuit SW2, by using a switch circuit similar to that of FIG. 19, not only the unused bit line DBL2 is used as a power supply stabilization capacitor, but also the unused bit line DBL2 is used according to the test case during the stress test. It can be driven by voltage.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of sense amplifiers connected to a pair of bit lines extending on both sides in the column direction, arranged in a row direction orthogonal to the column direction;
A plurality of sense amplifier groups are arranged in the column direction, and a plurality of bit lines connected to the respective sense amplifier groups adjacent to each other in the column direction are arranged in parallel to each other, and the sense amplifier groups are arranged at both ends in the column direction. A plurality of unused bit lines arranged in parallel to a plurality of bit lines at both ends in the column direction of the pair of bit lines connected to each other, a plurality of word lines are wired in a row direction, A memory cell array in which memory cells are arranged at intersections of a plurality of bit lines and the plurality of unused bit lines and the plurality of word lines;
An internal power supply circuit disposed at one end of the memory cell array in the column direction and supplying an internal power supply to the plurality of sense amplifier groups via an internal power supply line;
A semiconductor memory device in which a plurality of unused bit lines arranged at the other end in the column direction of the memory cell array are connected to the internal power supply wiring.

(Appendix 2)
In Appendix 1,
The word lines alternately cross the bit lines connected to two adjacent sense amplifier groups sandwiching the word lines, and are connected to the bit lines and unused bit lines at both ends in the column direction of the memory cell array. A semiconductor memory device that crosses alternately.

(Appendix 3)
In Appendix 1 or 2,
First and second internal power supply circuits for generating first and second internal power supplies are respectively disposed at first and second ends at both ends in the column direction of the memory cell array, and the plurality of the first ends are provided. The unused bit lines are connected to the second internal power supply wiring of the second internal power supply circuit, and the plurality of unused bit lines at the second end are connected to the first internal power supply circuit of the first internal power supply circuit. A semiconductor memory device connected to internal power supply wiring.

(Appendix 4)
In Appendix 3,
The first internal power supply is higher than a precharge voltage of the bit line, the second internal power supply is lower than the precharge voltage,
The pair of bit lines are precharged to the precharge voltage, and are driven by the first or second internal power supply when the sense amplifier is driven.

(Appendix 5)
In Appendix 3,
The first and second internal power supplies are higher than the precharge voltage of the bit line, the first internal power supply is higher than the second internal power supply,
A third internal power supply circuit for generating a third internal power supply lower than the precharge voltage;
The pair of bit lines are precharged to the precharge voltage, driven to the first or third internal power source when the sense amplifier is driven, and then driven to the first internal power source. The bit line of the semiconductor memory device is driven by a second internal power supply.

(Appendix 6)
In Appendix 1 or 2,
A first internal power supply circuit that generates a first internal power supply at the first end of both ends of the memory cell array in the column direction, and a second and a third that generate second and third internal power supplies at the second end. And a part of the plurality of unused bit lines at the first end is connected to a second internal power supply line of the second internal power supply circuit, and the rest is the third power supply line. A semiconductor memory device connected to a third internal power supply wiring of an internal power supply circuit, wherein the plurality of unused bit lines at the second end are connected to a first internal power supply wiring of the first internal power supply circuit.

(Appendix 7)
In Appendix 6,
The first internal power supply is lower than the precharge voltage, the second and third internal power supplies are higher than the precharge voltage of the bit line, the second internal power supply is higher than the third internal power supply,
The pair of bit lines are precharged to the precharge voltage, driven to the first or second internal power source when the sense amplifier is driven, and then driven to the second internal power source. The bit line of the semiconductor memory device is driven by a third internal power supply.

(Appendix 8)
In Appendix 1 or 2,
Furthermore, in addition to a plurality of unused bit lines arranged on the other side of the memory array in the column direction, a plurality of unused bit lines arranged at one end are connected to the internal power supply wiring .

(Appendix 9)
In Appendix 8,
A first internal power supply circuit is disposed at a first end of each end of the memory cell array in the column direction, a second internal power supply circuit is disposed at a second end, and a plurality of first and second power supplies are disposed at the first end. An unused bit line is arranged, and a plurality of third and fourth unused bit lines are arranged at the second end, and the first and third unused bit lines are connected to the second internal power supply circuit. A semiconductor memory device connected to a second internal power supply line, wherein the second and fourth unused bit lines are connected to a first internal power supply line of the first internal power supply circuit.

(Appendix 10)
In Appendix 9,
Same as Appendix 4.

(Appendix 11)
In Appendix 9,
Same as Appendix 5.

(Appendix 12)
In Appendix 1 or 2,
The internal power supply circuit is disposed at a first end and a second end at both ends of the memory cell array in the column direction, and the unused bit lines at the first end and the second end are both connected to the first end and the second end. A semiconductor memory device connected to the internal power supply wiring of the internal power supply circuit at the second end.

(Appendix 13)
In Appendix 12,
The pair of bit lines are precharged to a precharge voltage, and when the sense amplifier is driven, the pair of bit lines are driven to a first internal power supply higher than the precharge voltage or a third internal power supply lower than the precharge voltage. And then the bit line driven to the first internal power source is driven to a second internal power source that is higher than the precharge voltage and lower than the first internal power source,
The semiconductor memory device in which the first, second or third internal power supply is generated by the internal power supply circuit.

(Appendix 14)
In Appendix 1 or 2,
A semiconductor memory device having a switch circuit that connects the unused bit line and the internal power supply wiring during normal operation, and connects the unused bit line to a test voltage during testing.

(Appendix 15)
In Appendix 14,
A precharge voltage generation circuit for generating a precharge voltage; a first internal power supply circuit for generating a first internal power supply higher than the precharge voltage of the bit line; and the first internal power supply higher than the precharge voltage. A second internal power supply circuit for generating a lower second internal power supply, and a third internal power supply circuit for generating a third internal power supply lower than the precharge voltage,
The internal power supply wiring is an internal power supply wiring of the first, second or third internal power supply circuit;
The test voltage is an internal power supply circuit excluding an internal power supply circuit connected to the internal power supply wiring among the first, second and third internal power supply circuits, or a semiconductor memory device which is the precharge voltage generation circuit .

BL, / BL: Bit line DBL: Unused bit line SWL: Sub word line SA: Sense amplifier unit SAD: Sense amplifier driver SWD: Sub word decoder VBLH: High potential internal voltage VBLL: Low potential internal voltage VBLP: Precharge voltage VOD: Overdrive voltage

Claims (10)

A plurality of sense amplifiers connected to a pair of bit lines extending on both sides in the column direction, arranged in a row direction orthogonal to the column direction;
A plurality of sense amplifier groups are arranged in the column direction, and a plurality of bit lines connected to the respective sense amplifier groups adjacent to each other in the column direction are arranged in parallel to each other, and the sense amplifier groups are arranged at both ends in the column direction. A plurality of unused bit lines arranged in parallel to a plurality of bit lines at both ends in the column direction of the pair of bit lines connected to each other, a plurality of word lines are wired in a row direction, A memory cell array in which memory cells are arranged at intersections of a plurality of bit lines and the plurality of unused bit lines and the plurality of word lines;
Supplying said arranged in said column direction of one end of the memory cell array, via the internal power supply wiring to the arranged extends to a column direction of the other end of said memory cell array internal power supply from said one end to said plurality of sense amplifier groups An internal power supply circuit
The semiconductor memory device of the plurality of unused bit lines arranged in the other end is connected at the position of the other end to the internal power supply line. In claim 1,
The word lines alternately cross the bit lines connected to two adjacent sense amplifier groups sandwiching the word lines, and are connected to the bit lines and unused bit lines at both ends in the column direction of the memory cell array. A semiconductor memory device that crosses alternately. In claim 1 or 2,
First and second internal power supply circuits for generating first and second internal power supplies are respectively disposed at first and second ends at both ends in the column direction of the memory cell array, and the plurality of the first ends are provided. The unused bit lines are connected to the second internal power supply wiring of the second internal power supply circuit, and the plurality of unused bit lines at the second end are connected to the first internal power supply circuit of the first internal power supply circuit. A semiconductor memory device connected to internal power supply wiring. In claim 3,
The first internal power supply is higher than a precharge voltage of the bit line, the second internal power supply is lower than the precharge voltage,
The pair of bit lines are precharged to the precharge voltage, and are driven by the first or second internal power supply when the sense amplifier is driven. In claim 3,
The first and second internal power supplies are higher than the precharge voltage of the bit line, the first internal power supply is higher than the second internal power supply,
A third internal power supply circuit for generating a third internal power supply lower than the precharge voltage;
The pair of bit lines are precharged to the precharge voltage, driven to the first or third internal power source when the sense amplifier is driven, and then driven to the first internal power source. The bit line of the semiconductor memory device is driven by a second internal power supply. In claim 1 or 2,
A first internal power supply circuit that generates a first internal power supply at the first end of both ends of the memory cell array in the column direction, and a second and a third that generate second and third internal power supplies at the second end. And a part of the plurality of unused bit lines at the first end is connected to a second internal power supply line of the second internal power supply circuit, and the rest is the third power supply line. A semiconductor memory device connected to a third internal power supply wiring of an internal power supply circuit, wherein the plurality of unused bit lines at the second end are connected to a first internal power supply wiring of the first internal power supply circuit. In claim 6,
Said first internal power supply is lower than the precharge voltage of the bit line, the second and third internal supply is higher than the precharge voltage, said second internal power supply is higher than the third internal power supply,
The pair of bit lines are precharged to the precharge voltage, driven to the first or second internal power source when the sense amplifier is driven, and then driven to the second internal power source. The bit line of the semiconductor memory device is driven by a third internal power supply. In claim 1 or 2,
In addition to the plurality of unused bit line that is disposed on the other end in the column direction of the memory cell array, a semiconductor plurality of unused bit lines arranged in one end, which is connected to the internal power supply line Storage device. In claim 1 or 2,
A semiconductor memory device having a switch circuit that connects the unused bit line and the internal power supply wiring during normal operation, and connects the unused bit line to a test voltage during testing. In claim 9,
A precharge voltage generation circuit for generating a precharge voltage; a first internal power supply circuit for generating a first internal power supply higher than the precharge voltage of the bit line; and the first internal power supply higher than the precharge voltage. A second internal power supply circuit for generating a lower second internal power supply, and a third internal power supply circuit for generating a third internal power supply lower than the precharge voltage,
The internal power supply wiring is an internal power supply wiring of the first, second or third internal power supply circuit;
The test voltage is an internal power supply circuit excluding an internal power supply circuit connected to the internal power supply wiring among the first, second and third internal power supply circuits, or a semiconductor memory device which is the precharge voltage generation circuit .

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