JP5761944B2 - Error check circuit and error check method - Google Patents

Description

  The present invention relates to an error check circuit and an error check method.

  Large data of several gigabytes is transmitted at high speed between data processing devices or between LSI (Large Scale Integration). In order to evaluate the reliability of such data transmission, a large amount of test data is transmitted at high speed to check whether the data has been transmitted correctly.

  A checksum check is known as a method for evaluating the reliability of data transmission. In the check using the checksum, the checksum of the data is calculated in the transmission device, and is added to the data and transmitted. Thereafter, in the receiving apparatus, a checksum generated from the received data is calculated, the transmitted checksum is compared with the checksum of the received data, and the comparison result is evaluated.

  As another method for evaluating the reliability of data transmission, a check by a cyclic redundancy check (hereinafter referred to as CRC) is known. In the check by CRC, the CRC code generated in the CRC generation circuit of the transmission apparatus is added to the data and transmitted. Thereafter, the CRC check circuit of the receiving apparatus compares the CRC code generated from the received data with the transmitted CRC code, and evaluates the comparison result.

  Further, as a method for evaluating the reliability of other data transmission, a check by comparison is known. In the check by comparison, the data transmitted from the transmission device is received, the received data is compared with the expected value stored in advance in the storage device, and the comparison result is evaluated.

  In the internal data management / confirmation method, there are an area for storing the management symbol for confirming the identity of the rewritable device displayed on the display device, and an area for confirming the validity by the control program at the time of writing. When the write signal is received from the personal computer, the value is compared with the value calculated by the control program, and when the validity is confirmed, the program or data is stored in the write area of the rewritable device, and the management symbol of the program or data is Means for writing in the management symbol storage area have been proposed.

  Further, in the test method of the CRT display control circuit, the CRT display control circuit, the parity bit generation circuit for generating parity bits of a plurality of signals output from the CRT display control circuit, and the clock of the CRT display control circuit are synchronized. There have been proposed a synchronous clock generation circuit for generating a clock, a CRC calculation circuit for performing CRC calculation of a parity bit string output from the parity bit generation circuit in accordance with the synchronous clock, and the like.

  Further, in the multiplex communication apparatus, a second error detection for detecting an error in the transmission content data with respect to the content data separately from the error detection data such as a CRC check code added for each packet at the time of transmission. Data is added and transmitted, and the content of the received data field is determined using the second error detection data included in the data field to determine whether or not the read data is error-free. Means for detecting data corruption due to noise on the parallel bus or the like have been proposed.

JP 2003-196114 A JP-A-61-107286 JP 2000-293442 A

  For example, as shown in FIG. 7A, the apparatus 101A transmits the test data stored in the transmission data file 102 to the apparatus 101B via the high-speed serial signal transmission path 105. The device 101B stores the test data received from the device 101A in the received data file 103, and evaluates the reliability of data transmission. In other words, as shown in FIG. 7B, after a large-capacity data transmission process 201 is executed, some kind of comparison check process 202 is executed. For example, when the reliability of data transmission is evaluated using the above-described comparison check, the apparatus 101B receives the test data received and stored in the received data file 103 and the expectation stored in the expected value file 104 in advance. Compare the value.

  However, in the check by checksum, the checksum added to the test data and the checksum generated from the received data are different from each other in spite of being originally different values. May match. In this case, an error that should originally be detected is not detected. Further, it is necessary for the transmitting apparatus 101A to add a checksum as check-dedicated data to the test data. Also, the transmitted checksum itself may not be transmitted correctly.

  In the check by CRC, for example, when evaluating the reliability of data transmission for test data having a large bit width such as 64 bits, the scale of the CRC check circuit in the receiving-side apparatus 101B becomes considerably large. Not realistic. In other words, the size of the CRC check circuit becomes large, and the CRC check circuit may not be mounted on an FPGA (Field Programmable Gate Array). Further, it is necessary for the transmitting apparatus 101A to add a CRC code as check-only data to the test data.

  Further, in the check by comparison, as shown in FIG. 7A, an expected value file 104 for storing an expected value for the comparison check process 202 is necessary. When the data size is as large as several gigabytes, a large storage area for storing the expected value is required. In other words, the cost increases only for evaluating the reliability of data transmission and cannot be adopted. Further, when the data size is large, the comparison check process 202 takes time. Therefore, during the execution of the received data comparison check process 202, the newly received data cannot be checked. In other words, as a result of the time for the comparison check process 202 being different from the actual operation time of the apparatus 101B, it is not appropriate as an evaluation of the reliability of data transmission in the actual operation of the apparatus 101B.

  It is an object of the present invention to provide an error check circuit that can confirm the validity of data transmission with a small circuit without adding check-dedicated data to transmitted data.

The disclosed error check circuit includes a reception circuit, a plurality of parity calculation units, a plurality of CRC error detection units, a checksum error detection unit, a detection circuit, and a cycle control unit . The receiving circuit receives communication data. The plurality of parity calculation units generate parity bits for each of the plurality of unit data obtained by dividing the communication data. The plurality of CRC error detection units are provided corresponding to the plurality of parity calculation units, generate CRC codes using the parity bits output from the corresponding parity calculation units, and execute error detection using the CRC codes. Checksum error detection unit generates a checksum about the communication data, performs error detection using the checksum. The detection circuit detects an error in communication data based on a result of error detection using a CRC code in each of a plurality of CRC error detection units and a result of error detection using a checksum in a checksum error detection unit To do. The cycle control unit controls the plurality of CRC error detection units and the checksum error detection unit to repeatedly execute error detection using a CRC code and error detection using a checksum for communication data. The reception circuit repeatedly receives the same communication data, and the checksum error detection unit, according to the control of the cycle control unit, checks the checksum of the current communication data and the checksum of the previous communication data. The error detection using the checksum is performed by comparing the CRC codes of the current communication data and the communication immediately before the current communication data according to the control of the cycle control unit. By comparing the data with the CRC code, error detection using the CRC code is executed.

According to the error check circuit disclosed, and a check using a combination of parity bits and CRC codes, by a check using the checksum, without adding a check only data in the data to be transmitted, small circuit Can confirm the validity of data transmission.

It is explanatory drawing about an example of a structure of a data processor, etc. It is a figure which shows an example of a structure of an error check circuit. It is a figure which shows an example of a structure of a parity calculating part. It is a figure which shows an example of a structure of a CRC calculating part. It is explanatory drawing of the error detection process of data. It is explanatory drawing of the error detection process of data. It is explanatory drawing of the data transmission in a data processor.

  FIG. 1 is an explanatory diagram of an example of the configuration of the data processing apparatus.

  As shown in FIG. 1A, the data processing device includes a first device 1A, a second device 1B, and a cable 15 connecting them. The first device 1A and the second device 1B are, for example, data processing devices that execute large-scale signal processing. The first device 1A and the second device 1B may be a semiconductor device such as an FPGA on which a circuit that performs large-scale signal processing is mounted. The cable 15 is, for example, a cable that performs serial transmission.

  In FIG. 1A, the first device 1A transmits a signal to the second device 1B, and the second device 1B receives the signal transmitted from the first device 1A. In other words, FIG. 1 shows a case where the first device 1A is a transmitting device and the second device 1B is a receiving device.

  Note that the first device 1A and the second device 1B may transfer data to each other. In this case, the cable 15 is, for example, a cable that performs serial transmission in both directions. In this case, both the first device 1A and the second device 1B are transmission / reception devices that transmit and receive signals. Therefore, the first device 1A includes the same configuration as the second device 1B.

  The second device 1B includes a receiving circuit 2, an error check circuit 3, and a signal processing circuit 4. The receiving circuit 2 receives the signal transmitted from the first device 1 </ b> A via the cable 15 and inputs it to the error check circuit 3 and the signal processing circuit 4. The error check circuit 3 executes an error detection process for the input signal. The signal processing circuit 4 performs data processing on the signal input from the receiving circuit 2.

  As illustrated in FIG. 1B, the reception circuit 2 repeatedly receives a plurality of data transmission processes # 1 to # 3 from the apparatus 1A at a predetermined test cycle. In other words, each data transmission process # 1 to # 3 is a test cycle. Accordingly, the lengths of the data transmission processes # 1 to # 3 are equal. The error check circuit 3 repeatedly executes the check processes # 1 to # 3 at a predetermined test cycle in response to reception of the plurality of data transmission processes # 1 to # 3. As will be described later, since the check processes # 1 to # 3 are actually executed in parallel with the data transmission processes # 1 to # 3, the period of the check processes # 1 to # 3 can be ignored, and the data transmission process The check process is not executed after.

  The error check circuit 3 may output the result of the check process every time the check process is performed. Even in this case, the output of the check process result can be executed in parallel with the data transmission process.

  FIG. 2 is a diagram mainly showing an example of the configuration of the error check circuit.

  The receiving circuit 2 receives a serial signal as a communication signal from the outside of the second device 1B, in other words, from the first device 1A via the cable 15. The receiving circuit 2 converts the serial signal into a parallel signal in the serial-parallel conversion circuit. The parallel signal has a predetermined bit width, for example, a 64-bit width. The bit width of the parallel signal is not limited to 64 bits. The reception circuit 2 inputs a 64-bit parallel signal to the data reception buffer 5 of the error check circuit 3.

  The receiving circuit 2 may receive an optical signal (serial signal) via an optical fiber cable, and the OE conversion circuit may convert the optical signal (serial signal) into an electric signal (serial signal). In this case, the serial signal converted into an electric signal is converted into a parallel signal.

  The receiving circuit 2 receives a test start signal from the first device 1A via the cable 15 prior to receiving communication data. The test start signal is, for example, a signal that instructs the start of a test, in other words, the start of transmission of communication data. The test start signal determines the test start timing, in other words, the position of the communication data. As a result, the receiving circuit 2 can sequentially convert the received plurality of communication data into a parallel signal having a 64-bit width and store it in the data receiving buffer 5 in the order of reception.

  Note that a frame signal may be used as the test start signal. The frame signal is, for example, a signal that instructs the start of a frame, in other words, the start of transmission of communication data. The frame signal determines the start position of the frame, in other words, the position of the communication data. Thereby, not only when the communication data is test data, error detection can be performed on data transmitted between the devices 1A and 1B during operation. In this case, as described above, the check processes # 1 to # 3 are executed in parallel with the data transmission processes # 1 to # 3, and the check process is not executed after the data transmission process. There is no obstacle to communication between the device 1A and the device 1B. Therefore, even during operation of the data processing apparatus of FIG. 1, the validity of the communication data can be checked in parallel with the transmission / reception of the communication data.

  The error check circuit 3 includes a data reception buffer 5, a plurality of parity calculation units 6, a plurality of CRC error detection units 7, a checksum error detection unit 10, and a detection circuit 14. Each of the plurality of CRC error detection units 7 includes a CRC calculation unit 8 and a CRC result holding comparison unit 9. The checksum error detection unit 10 includes a sum calculation unit 11 and a sum result holding comparison unit 12.

  The data reception buffer 5 divides the communication data received by the reception circuit 2 into a plurality of unit data, and outputs the data to a plurality of parity calculation units 6. For example, since the bit width of the communication data is 64 bits, the communication data is divided into 8 pieces of 8-bit data in the example of FIG. Therefore, the bit width of the unit data is 8 bits, and 8 parity operation units 6 are provided. The bit width of the unit data is not limited to 8 bits, and the number of parity operation units 6 is not limited to 8. For each parity calculation unit 6, input unit data, in other words, a bit position in 64-bit communication data is determined in advance.

  Each of the plurality of parity calculation units 6 is a circuit that executes a parity calculation, and generates a parity bit for each of a plurality of unit data obtained by dividing communication data. In the example of FIG. 2, the parity operation unit 6 is an operation circuit that executes 8-bit even parity operation and outputs one parity bit.

  FIG. 3 is a diagram illustrating an example of the configuration of the parity calculation unit.

  The parity calculation unit 6 includes seven 2-input exclusive OR circuits (hereinafter referred to as XOR gates) 61A to 61G. The 8-bit data from the 0th bit (bit0) to the 7th bit (bit7) output from the data reception buffer 5, and the data corresponding to the parity calculation unit 6 is a parity calculation as shown in FIG. Input to unit 6.

  Specifically, bit0 and bit1 are input to the XOR gate 61A, and bit2 and bit3 are input to the XOR gate 61B. Bit 4 and bit 5 are input to the XOR gate 61C, and bit 6 and bit 7 are input to the XOR gate 61D. The outputs of the XOR gate 61A and the XOR gate 61B are input to the XOR gate 61E, and the outputs of the XOR gate 61C and the XOR gate 61D are input to the XOR gate 61F. Further, the outputs of the XOR gate 61E and the XOR gate 61F are input to the XOR gate 61G.

  By the combination of the exclusive OR operations as described above, an even parity for 8-bit data from the 0th bit (bit0) to the 7th bit (bit7) is obtained as the output of the XOR gate 61. The even parity output from the parity calculation unit 6 is 1 bit. The parity calculation unit 6 inputs 1-bit even parity to the CRC calculation unit 8 of the corresponding CRC error detection unit 7. In other words, the parity generated by the parity calculation unit 6 is not for parity check but is data obtained by compressing received communication data in consideration of information indicating the presence or absence of an error.

  The parity calculation unit 6 may generate odd parity. Further, the parity calculation unit 6 may generate parity bits for unit data having a bit width other than 8-bit unit data. Further, the parity calculation unit 6 may generate a parity bit including a plurality of bits.

  Returning to FIG. 2, the plurality of CRC error detection units 7 are provided corresponding to the plurality of parity calculation units 6, generate CRC codes using the parity bits output from the corresponding parity calculation units 6, and generate CRC codes. Perform error detection using. Thus, the CRC code is generated in the second device 1B which is a receiving device. Accordingly, the first device 1A, which is a transmission device, does not need to generate a CRC code, add it to communication data, and transmit it, and does not need to include a CRC code generation circuit. The CRC code is generated using parity bits obtained by compressing communication data in consideration of information indicating the presence / absence of an error. Therefore, the circuit scale of the CRC error detection unit 7 can be reduced, and a CRC code can be generated based on data including information indicating the presence or absence of an error.

  Each of the plurality of CRC error detection units 7 includes a CRC calculation unit 8 and a CRC result holding comparison unit 9. The CRC calculation unit 8 generates a CRC code using the parity bits output from the corresponding parity calculation unit 6. In the example of FIG. 2, the CRC calculation unit 8 is a calculation circuit that executes a calculation of CRC-16-CCITT, as shown in FIG. 4. The CRC result holding / comparing unit 9 performs error detection using a CRC code.

  FIG. 4 is a diagram illustrating an example of the configuration of the CRC calculation unit.

  The CRC calculation unit 8 includes three 2-input XOR gates 81A to 81C, five flip-flop circuits (hereinafter referred to as FF circuits) 82A, seven FF circuits 82B, and four FF circuits 82C. Including. The initial value of each of the FF circuits 82A to 82C is “1”.

  Specifically, a first shift register is provided corresponding to the XOR gate 81A. The first shift register includes five FF circuits 82A. A second shift register is provided corresponding to XOR gate 81B. The second shift register includes seven FF circuits 82B. A third shift register is provided corresponding to the XOR gate 81C. The third shift register includes four FF circuits 82C.

  The 1-bit even parity output from the parity calculation unit 6 is input to the XOR gate 81A of the CRC calculation unit 8, as shown in FIG. The XOR gate 81A is supplied with the output of the third shift register, in other words, bit 15 described later.

  The output of the XOR gate 81A is input to the five FF circuits 82A, in other words, the first shift register. The output of the XOR gate 81A is input to the XOR gate 81B and the XOR gate 81C. The output of the first shift register, in other words, bit4 described later is input to the XOR gate 81B. The output of the second shift register, in other words, bit 11 described later is input to the XOR gate 81C.

  A 16-bit CRC code is obtained by the above operation. Specifically, the output of each digit of the first shift register, in other words, the outputs of the five FF circuits 82A are output as bits 0 to 4 of the CRC code. The output of each digit of the second shift register, in other words, the outputs of the seven FF circuits 82B are output as bits 5 to 11 of the CRC code. The output of each digit of the third shift register, in other words, the outputs of the four FF circuits 82C are output as bits 12 to 15 of the CRC code.

As a result, the CRC calculation unit 8 calculates X ¹⁶ + X ¹² + X ⁵ +1 and obtains a 16-bit CRC code. The CRC calculation unit 8 outputs a 16-bit CRC code to the corresponding CRC result holding comparison unit 9.

  The CRC calculation unit 8 may include a circuit that generates a 16-bit CRC code by another calculation. The CRC calculation unit 8 may be a calculation circuit that generates another CRC code.

  Returning to FIG. 2, the CRC result holding / comparing unit 9 receives the 16-bit CRC code output from the corresponding CRC calculation unit 8 as it is. Thus, the CRC result holding / comparing unit 9 does not receive the new CRC code, in other words, the latest 16-bit CRC code, instead of the CRC code fetched immediately before the new CRC code. Entered. The latest 16-bit CRC code is input to, for example, a comparison circuit. The CRC result holding / comparing unit 9 may fetch the new CRC code each time a new CRC code is input from the CRC calculation unit 8.

  Even if the CRC code fetched prior to the latest CRC code is not retained, the latest CRC code inherits all the CRC codes generated before that. In other words, the latest CRC code does not have a correct value unless all CRC codes generated before that are correct. Therefore, by inputting the latest CRC code to the CRC result holding / comparing unit 9, error detection using the CRC code can be executed for communication data corresponding to the latest CRC code and communication data before that. .

  Further, the CRC result holding / comparing unit 9 captures and holds the latest CRC code input at that time in a register in a predetermined test cycle in accordance with an instruction from the cycle control unit 13. The CRC code held in the register is compared with the latest CRC code at that time at the end of the next test period. In other words, the CRC code held in the register is the CRC code one cycle before the current test cycle.

  The CRC code held in the register is the last CRC code in the test cycle one cycle before the current test cycle. Therefore, for example, when the test cycle corresponds to a period for transmitting 10,000 pieces of communication data, a CRC code generated based on the last piece of communication data is held in the register. The CRC code generated based on the remaining 9999 pieces of communication data is not directly used for error detection. However, as described above, unless the 9999 pieces of communication data are correct, the CRC code generated based on the last piece of communication data is not a correct value. Therefore, an error can be detected by using a CRC code generated based on the last piece of communication data.

  The test period is predetermined. In the data transmission processes # 1 to # 3 shown in FIG. 1B, a plurality of communication data are continuously transmitted. As described above, the communication data has a fixed length of 64 bits, for example. The number of communication data transmitted in one test cycle is predetermined, for example, 10,000 to 100,000. In other words, a period in which a predetermined number of communication data is continuously transmitted is one test cycle.

  When 10,000 pieces of communication data are transmitted in each of the data transmission processes # 1 to # 3, the 10,000 pieces of communication data transmitted in each of the data transmission processes # 1 to # 3 are the same. . Thereby, in the check processes # 1 to # 3, communication data errors can be detected by comparing the CRC code of the current test cycle with the CRC code of the test cycle one cycle before.

  Further, the CRC result holding / comparing unit 9 follows the instruction from the cycle control unit 13 with the latest CRC code inputted at that time and the CRC code fetched and held in the register in the test cycle. The comparison is made in the comparison circuit. In other words, the latest CRC code of the current test cycle is compared with the CRC code of the previous test cycle.

  Actually, the CRC result holding / comparing unit 9 follows the instruction from the cycle control unit 13 and the latest CRC code inputted at that time and the test cycle one cycle before being held in the register. The CRC code is compared, and the result is output from the comparison circuit to the detection circuit 14. Thereafter, the CRC result holding / comparing unit 9 captures the latest CRC code inputted at that time into the register. As a result, the contents of the register are overwritten.

  Each CRC result holding / comparing unit 9 detects the coincidence signal when the latest CRC code inputted at that time coincides with the CRC code of the previous test period held in the register. Output to. Each CRC result holding / comparing unit 9 does not match if the latest CRC code input at that time does not match the CRC code of the previous test period fetched and held in the register. The signal is output to the detection circuit 14.

  On the other hand, the checksum error detection unit 10 generates a checksum for each piece of communication data, and executes error detection using the checksum. Thereby, the checksum is generated in the second device 1B which is a receiving device. Therefore, the first device 1A, which is a transmission device, does not need to generate a checksum, add it to communication data, and transmit it, and does not need to include a checksum generation circuit.

  The checksum error detection unit 10 includes a sum calculation unit 11 and a sum result holding comparison unit 12. The sum calculator 11 generates a checksum for each piece of communication data. The sum result holding / comparing unit 12 performs error detection using a checksum.

  Specifically, the sum calculator 11 captures a plurality of unit data output from the data reception buffer 5 to the plurality of parity calculators 6. Specifically, eight pieces of 8-bit data are taken into the sum calculator 11. As a result, the sum calculator 11 obtains 64-bit communication data input to the data reception buffer 5. Note that the sum calculator 11 may fetch 64-bit communication data from the data reception buffer 5.

  The sum calculator 11 divides the plurality of unit data taken into two, and adds the divided partial data. Specifically, the sum calculation unit 11 divides the plurality of unit data taken into two so as to correspond to the upper 32 bits and the lower 32 bits of the 64-bit communication data, and adds them. Then, the sum calculation unit 11 divides the addition result into two, discards the upper 32 bits of the addition result, and outputs the lower 32 bits as a checksum to the sum result holding / comparing unit 12.

  Note that the sum calculation unit 11 may generate a checksum by another calculation. Further, the sum calculator 11 may generate a checksum having a bit length other than the 32-bit checksum.

  Each time a new checksum is output from the corresponding sum calculation unit 11, the sum result holding / comparing unit 12 adds a new checksum to the checksum held up to that point in the adder circuit. Then, the sum result holding / comparing unit 12 divides the addition result of the two check sums into two, discards the upper 32 bits of the addition result, and holds the lower 32 bits as the latest check sum in the adder circuit.

  As a result, the checksum held prior to the latest checksum is destroyed. However, the latest checksum inherits all checksums generated before that time. In other words, the latest checksum will not be the correct value unless all previously generated checksums are correct. Therefore, by holding the latest checksum in the sum result holding / comparing unit 12, error detection using the checksum can be executed for communication data corresponding to the latest checksum and communication data before that. .

  Further, the sum result holding / comparing unit 12 takes the latest checksum held in the adder circuit at that time into the register and holds it in the test cycle according to the instruction from the cycle control unit 13. The checksum held in the register is compared with the latest checksum at that time at the end of the next test period. In other words, the checksum held in the register is a checksum one cycle before the current test cycle.

  The checksum held in the register is the final checksum in the test cycle one cycle before the current test cycle. Therefore, for example, when the test cycle corresponds to a period for transmitting 10,000 pieces of communication data, a checksum generated based on the addition of the last piece of communication data is held in the register. The checksum generated based on the remaining 9999 pieces of communication data is not directly used for error detection. However, as described above, unless the 9999 pieces of communication data are correct, the checksum generated based on the addition of the last piece of communication data is not a correct value. Therefore, an error can be detected by using a checksum generated based on the addition of the last piece of communication data.

  In accordance with an instruction from the cycle control unit 13, the sum result holding / comparing unit 12 includes the latest checksum held in the adder circuit at that time in the test cycle, and the checksum fetched and held in the register. Compare In other words, the latest checksum of the current test cycle is compared with the checksum of the previous test cycle.

  Actually, the sum result holding / comparing unit 12 follows the instruction from the cycle control unit 13 and the latest checksum held in the adder circuit at that time, and the previous cycle that is taken in and held in the register. The checksum of the test period is compared, and the result is output from the comparison circuit to the detection circuit 14. Thereafter, the sum result holding / comparing unit 12 takes the latest checksum held in the adder circuit at that time into the register. As a result, the contents of the register are overwritten.

  When each sum result holding comparison unit 12 matches the latest checksum held in the adder circuit at that time with the checksum of the previous test period fetched and held in the register, The coincidence signal is output to the detection circuit 14. Further, each sum result holding comparison unit 12 does not match the latest checksum held in the adder circuit at that time with the checksum of the previous test cycle fetched and held in the register. In the case, the mismatch signal is output to the detection circuit 14.

  When the error detection result using the CRC code is output from each of the plurality of CRC error detection units 7, the detection circuit 14 captures these as they are. Further, when the error detection result using the checksum is output from the checksum error detection unit 10, the detection circuit 14 captures this as it is. And the detection circuit 14 is based on the result of error detection using the CRC code in each of the plurality of CRC error detection units 7 and the result of error detection using the checksum in the checksum error detection unit 10. An error of a plurality of communication data received in the test cycle is detected.

  Specifically, when the detection circuit 14 receives the coincidence signal from all the CRC error detection units 7 and also receives the coincidence signal from the checksum error detection unit 10, the coincidence flag is set in advance in the register. Store in bits. In addition, the detection circuit 14 sets a match flag in advance in the register when any one of the CRC error detection units 7 receives a mismatch signal or when it receives a mismatch signal from the checksum error detection unit 10. Do not store in the specified bit. The detection circuit 14 outputs a register match flag to the outside of the device 1B in accordance with a predetermined control signal.

  Instead of storing the match flag, the mismatch flag may be stored in a predetermined bit of the register. Further, the detection circuit 14 may output the error detection result by means other than storing the coincidence flag in the register.

  The cycle control unit 13 controls the plurality of CRC error detection units and the checksum error detection unit to execute error detection using a CRC code and error detection using a checksum for communication data.

  Specifically, the cycle control unit 13 controls the plurality of CRC calculation units 8 and the sum calculation unit 11 to generate a CRC code and a checksum for the communication data. The cycle control unit 13 supplies a first control signal to the plurality of CRC calculation units 8. Thereby, the plurality of CRC calculation units 8 take in the parity bits at the timing when the parity bits are generated from the unit data output from the data reception buffer 5. The cycle control unit 13 supplies the first control signal to the sum calculation unit 11. As a result, the sum calculator 11 takes in the plurality of unit data at the timing when the plurality of unit data is output from the data reception buffer 5.

  For this purpose, for example, the cycle control unit 13 counts the number of communication data input to the data reception buffer 5 and forms a first control signal every time one communication data is input. To the CRC calculator 8 and the sum calculator 11. Note that the cycle control unit 13 may count an operation clock with which communication data is synchronized.

  The plurality of CRC calculation units 8 and the sum calculation unit 11 are controlled at the same timing. Therefore, in practice, the sum calculator 11 takes in a plurality of unit data at the timing when the parity bit is generated behind the timing at which the plurality of unit data is output from the data reception buffer 5. Thus, the plurality of CRC calculation units 8 and the sum calculation unit 11 generate a plurality of CRC codes and checksums for the same communication data, respectively.

  The cycle control unit 13 controls the plurality of CRC result holding / comparing units 9 and the sum result holding / comparing unit 12 to detect and check errors using a CRC code for each of a plurality of predetermined communication data. Error detection using the thumb is executed. The cycle control unit 13 supplies the second control signal to the plurality of CRC result holding comparison units 9. Thereby, the plurality of CRC result holding / comparing units 9 compare the latest CRC code of the current test cycle with the CRC code of the test cycle of the previous cycle held in the register in the test cycle, and the two match. In the case, a coincidence signal is output. Further, the cycle control unit 13 supplies the second control signal to the thumb result holding / comparing unit 12. As a result, the sum result holding / comparing unit 12 compares the latest checksum of the current test cycle with the checksum of the previous test cycle held in the register in the test cycle, and if both match, Outputs a coincidence signal.

  For this purpose, for example, the cycle control unit 13 counts the number of fixed-length communication data input to the data reception buffer 5, and each time a predetermined number, for example, 10,000 communication data is input. The second control signal is formed and supplied to the plurality of CRC calculation units 8 and the sum calculation unit 11. Note that the cycle control unit 13 may count an operation clock with which communication data is synchronized.

  The plurality of CRC result holding / comparing units 9 and the sum result holding / comparing unit 12 are controlled at the same timing. For example, the plurality of CRC result holding / comparing units 9 and the sum result holding / comparing unit 12 execute the comparison process with a delay of a predetermined time from the timing at which the current test cycle ends. As a result, the comparison process can be executed at the timing when the CRC code and the checksum of the current test cycle are reliably input and in parallel with the test cycle one cycle later. As a result, the plurality of CRC result holding / comparing units 9 and the sum result holding / comparing unit 12 respectively change the CRC code for the communication data of the same current test cycle and the communication data of the same previous test cycle. The error detection used and the error detection using the checksum can be executed.

  FIG. 5 is an explanatory diagram of data error detection processing, and particularly shows error detection processing using a CRC code.

  The 64-bit data from the 63rd bit (bit 63) to the 0th bit (bit 0) output from the reception circuit 2 is divided by the data reception buffer 5 every 8 bits. Accordingly, eight unit data are obtained. Eight pieces of 8-bit unit data are input to eight predetermined parity operation units 6, respectively.

  Each of the eight parity calculation units 6 generates even parity of 1 bit. The 1-bit even parity is input to the corresponding CRC calculation unit 8 according to the first control signal from the cycle control unit 13.

  The eight CRC calculation units 8 generate a CRC code based on the input from the corresponding parity calculation unit 6. By generating a CRC code based not on communication data but on parity bits, the circuit scale of the CRC calculation unit 8 can be reduced. The CRC code is input to the corresponding CRC result holding / comparing unit 9 in accordance with the second control signal from the cycle control unit 13.

  The eight CRC result holding / comparing units 9 compare the latest CRC code of the current test cycle with the CRC code of the previous test cycle held in the register according to the second control signal from the cycle control unit 13. If they match, a match signal is output. In FIG. 5, the CRC codes of the test cycle one cycle before held in the registers of the eight CRC result holding comparison units 9 are indicated by hatching.

  Accordingly, the eight CRC result holding / comparing units 9 need only hold eight 16-bit CRC codes in the register. Thereby, the data can be stored in the register without providing a storage area for holding the CRC code. In addition, the eight CRC result holding / comparing units 9 need only compare two 8-bit CRC codes. Thereby, the circuit scale of the comparison circuit for comparing CRC codes can be reduced.

  FIG. 6 is an explanatory diagram of data error detection processing, and particularly shows error detection processing using a checksum.

  The 64-bit data from the 63rd bit (bit63) to the 0th bit (bit0) output from the receiving circuit 2 is input to the sum calculator 11 through the data receiving buffer 5 as described above.

  The sum calculator 11 divides 64-bit communication data, in other words, eight unit data into two parts, and adds the two divided partial data. Then, the sum calculator 11 divides the addition result into two, discards the upper 32 bits of the addition result, and sets the lower 32 bits as a checksum. The checksum is output to the sum result holding / comparing unit 12 in accordance with the second control signal from the cycle control unit 13.

  The sum result holding / comparing unit 12 compares the latest checksum of the current test cycle with the checksum of the previous test cycle held in the register according to the second control signal from the cycle control unit 13, If they match, a match signal is output. In FIG. 6, the checksum of the previous test period held in the register of the sum result holding / comparing unit 12 is indicated by hatching.

  Therefore, the sum result holding comparison unit 12 only needs to hold a 32-bit checksum in the register. Thereby, it is possible to store in the register without providing a storage area of several gigabytes for holding the expected value of the checksum. The sum result holding / comparing unit 12 only needs to compare two 32-bit checksums. Thereby, the circuit scale of the comparison circuit for comparing the checksums can be reduced.

  As can be seen from FIGS. 5 and 6, a check using a combination of a parity bit and a CRC code and a check using a sum check can be performed with a small-scale circuit without adding dedicated check data to transmitted data. Validity of data transmission can be confirmed. Specifically, by generating parity bits of communication data, the size of data that is a source of CRC code generation can be reduced, and the circuit can be reduced. In addition, error detection can be performed accurately with a small circuit by executing error detection using a CRC code. On the other hand, in order to cope with the use of parity bits for CRC code generation, error detection using checksums is performed in accordance with error detection using CRC codes, thereby increasing the accuracy of error detection. Can do. Furthermore, the error detection accuracy can be further increased by executing error detection using the checksum in the same test cycle as the error detection using the CRC code.

2 reception circuit 3 error check circuit 4 signal processing circuit 5 data reception buffer 6 parity calculation unit 7 CRC error detection unit 8 CRC calculation unit 9 CRC result holding comparison unit 10 checksum error detection unit 11 sum calculation unit 12 sum result holding comparison unit 13 Period Control Unit 14 Detection Circuit

Claims (7)

A receiving circuit for receiving communication data;
A plurality of parity calculators for generating parity bits for each of a plurality of unit data obtained by dividing the communication data;
A plurality of CRC error detection units that are provided corresponding to the plurality of parity calculation units, generate a CRC code using the parity bits output from the corresponding parity calculation unit, and execute error detection using the CRC code When,
A checksum error detector that generates a checksum for the communication data and performs error detection using the checksum;
Based on a result of error detection using the CRC code in each of the plurality of CRC error detection units and a result of error detection using the checksum in the checksum error detection unit, errors in the communication data are determined. A detection circuit to detect;
Period control for repeatedly executing error detection using the CRC code and error detection using the checksum for the communication data by controlling the plurality of CRC error detection units and the checksum error detection unit Including
The receiving circuit repeatedly receives the same communication data,
The checksum error detection unit compares the checksum of the current communication data with the checksum of the previous communication data of the current communication data according to the control of the cycle control unit, thereby calculating the checksum. Perform the error detection used,
The plurality of CRC error detection units compare the CRC code of the current communication data with the CRC code of the previous communication data of the current communication data according to the control of the cycle control unit. An error check circuit characterized by executing error detection using the. The error check circuit further comprises:
The error check circuit according to claim 1, further comprising: a buffer circuit that divides the communication data received by the receiving circuit into the plurality of unit data and outputs the divided data to the plurality of parity calculation units. Each of the plurality of CRC error detection units generates a CRC code using the parity bits output from the corresponding parity calculation unit, and holds a CRC result for performing error detection using the CRC code The error check circuit according to claim 1, further comprising a comparison unit. The checksum error detection unit includes a sum calculation unit that generates a checksum for each of the communication data, and a sum result holding and comparison unit that performs error detection using the checksum. The error check circuit according to Item 1. Each of the plurality of CRC error detection units generates a CRC code using the parity bits output from the corresponding parity calculation unit, and holds a CRC result for performing error detection using the CRC code A comparison section,
The checksum error detection unit includes a sum calculation unit that generates a checksum for each of the communication data, and a sum result holding comparison unit that performs error detection using the checksum,
The cycle control unit controls the plurality of CRC calculation units and the sum calculation unit to generate the CRC code and the checksum for the communication data. Error check circuit. The cycle control unit controls the plurality of CRC result holding / comparing units and the sum result holding / comparing unit to detect errors using the CRC code for each of a plurality of predetermined communication data. The error check circuit according to claim 5, wherein error detection using a checksum is executed. Receiving communication data of a predetermined number of bits;
Generating a parity bit for each of a plurality of unit data obtained by dividing the communication data;
Generating a CRC code using the parity bits generated for each of the plurality of unit data, and performing error detection using the CRC code;
Generating a checksum for the communication data and performing error detection using the checksum;
Result of the error detection using the previous SL checksums, based on the result of the error detection using the previous SL CRC code, detecting an error of the communication data,
Repeating the error detection using the CRC code and the error detection using the checksum for the communication data,
In the step of receiving the communication data, the same communication data is repeatedly received,
Wherein in the step of performing error detection using the checksum, by comparing the checksum of the one previous communication data checksum and the current communication data of the communication data of current, use the checksum Error detection that was
In the step of performing error detection using the CRC code, by comparing the CRC code of one previous communication data CRC code and the current communication data of the communication data of current, use the CRC code An error check method characterized by executing error detection.

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