JP5762116B2 - Asynchronous counter circuit and sampling correction method for asynchronous counter circuit - Google Patents

Description

  The embodiment referred to in this application relates to a counter circuit and a sampling correction method for the counter circuit.

  In recent years, the counter circuit is used in various systems, for example, as a clock for a wireless circuit system or a processor, or used in various systems that require a clock data recovery system or a reference frequency.

  The counter circuit is also used for circuit calibration and correction systems. Specifically, for example, in an all-digital PLL (ADPLL), in order to operate at a higher frequency, a high-frequency counter circuit corresponding thereto is indispensable.

  By the way, conventionally, various counter circuits have been proposed.

Japanese Patent Laid-Open No. 06-197012 JP 2007-215213 A JP 61-164332 A Japanese Patent Laid-Open No. 63-010914

  Conventionally, two types of counter circuits are known: a synchronous counter circuit and an asynchronous counter circuit.

  Since the output of the synchronous counter circuit is synchronized with the clock, there is no problem if the output is sampled with the synchronized clock.

  However, in the synchronous counter circuit, the longest signal path (critical path) extends according to, for example, the number of flip-flops to count, and thus is not suitable for high-frequency operation. Further, since all the clocks are driven by the clock having the highest frequency, the power consumption increases and the power supply noise also increases.

  On the other hand, in the asynchronous counter circuit, there is no problem in the synchronous counter circuit as described above. However, for example, since each stage (flip-flop) uses the output of the previous stage as a clock, the delay is integrated by each stage. As the delay increases, a race problem arises. When this race condition occurs, it becomes difficult to correctly sample the output of each stage.

According to an embodiment, there is provided an asynchronous counter circuit comprising: a counter unit that counts according to a counter clock and calculates a count value asynchronous with the counter clock ; a sampling unit; and a determination unit. The

  The sampling unit captures the count value with at least three sampling clocks. The determination unit determines at least three sampling values captured by the at least three sampling clocks based on timing shifts in the at least three sampling clocks.

  The disclosed counter circuit and the sampling correction method of the counter circuit have an effect that a correct count value can be output even if a delay is integrated and a race occurs.

It is a figure which shows an example of a synchronous counter circuit. FIG. 2 is a timing diagram for explaining the operation of the counter circuit of FIG. 1. It is a figure which shows an example of an asynchronous counter circuit. FIG. 4 is a timing chart for explaining the operation of the counter circuit of FIG. 3. It is a figure which shows the counter circuit of a present Example. FIG. 6 is a timing diagram (part 1) for explaining the operation of the counter circuit of FIG. 5; FIG. 6 is a timing diagram (part 2) for explaining the operation of the counter circuit of FIG. 5; It is a flowchart which shows an example of the sampling correction process in the counter circuit of a present Example. It is a flowchart which shows the other example of the sampling correction process in the counter circuit of a present Example. It is a flowchart which shows the further another example of the sampling correction | amendment process in the counter circuit of a present Example. It is a block diagram which shows an example of ADPLL to which the counter circuit of a present Example is applied.

  First, before describing embodiments of the counter circuit and the sampling correction method of the counter circuit in detail, the synchronous counter circuit and the asynchronous counter circuit and their problems will be described with reference to FIGS.

  FIG. 1 is a diagram showing an example of a synchronous counter circuit, and FIG. 2 is a timing diagram for explaining the operation of the counter circuit of FIG. In order to simplify the explanation, FIG. 1 shows Q0 to Q3, but FIG. 2 shows only Q0 to Q2.

  As shown in FIG. 1, the synchronous counter circuit includes a counter unit 111 and a sampler unit 112, and the sampler unit 112 samples and outputs the value counted by the counter unit 111.

  The counter unit 111 includes flip-flops U0, U1, U2, and U3, exclusive OR gates EXOR1, EXOR2, and EXOR3, and AND gates AND2 and AND3. Here, the counter clock CK-DCO is supplied to the clock input CK of the flip-flops U0 to U3.

  In the counter unit 111, the NQ output (inverted Q output) of the flip-flop U0 is supplied to the D input of the first flip-flop U0, and the EX input of the EXOR1 is supplied to the D input of the second flip-flop U1. Output is supplied. EXOR1 receives the Q output (Q0) of U0 and the Q output (Q1) of U1, and outputs an exclusive OR of them.

  Further, in the counter unit 111, the outputs of EXOR2 and EXOR3 are supplied to the D inputs of the third-stage and fourth-stage flip-flops U2 and U3, respectively. Each EXOR2, EXOR3 receives the Q output (Q2, Q3) of U2, U3 and the output of AND2, AND3, respectively, and outputs their exclusive OR.

  Here, AND2 receives the Q output (Q0) of U0 and the Q output (Q1) of U1, and outputs a logical product of them, and AND3 receives the output of AND2 and the Q output (Q2) of U2. , Output the logical product of them.

  The sampler unit 112 includes flip-flops V0, V1, V2, and V3. The Q outputs (Q0, Q1, Q2, and Q3) of the flip-flops U0, U1, U2, and U3 of the counter unit 111 are converted into corresponding flip-flops. Received at D input of V0, V1, V2, V3.

  Here, the sampling clock Ref-CK is supplied to the clock input CK of V0 to V3, Q0 to Q3 are taken in by the Ref-CK, and the sampling outputs S0 to S3 are output from the Q outputs of V0 to V3. It is like that.

  In the counter unit 111 of FIG. 1, the path of the counter clock CK-DCO for each of the flip-flops U0 to U3 indicated by the thick solid line indicates a delay path necessary for passing through the counting flip-flop in order to perform sampling correctly.

  A path U0 → AND2 → AND3 → EXOR3 → U3 indicated by a broken line corresponds to a critical path of the data signal, and needs to reach the final stage flip-flop U3 within one cycle of the sampling clock Ref-CK.

  Further, the path indicated by the alternate long and short dash line indicates the earliest signal path through which the counter clock CK-DCO is supplied to the final flip-flop U3. In the sampler unit 112, a path indicated by a two-dot chain line indicates a path of the sampling clock Ref-CK to the flip-flop V3 at the final stage.

  As shown in FIG. 1, in the synchronous counter circuit, the counter clock CK-DCO is supplied to all the clock inputs CK of the flip-flops U0 to U3 in the counter unit 111.

  Therefore, as shown in FIG. 2, for example, when the Q outputs (Q0 to Q2) of U0 to U2 are taken in at the rising timing of the sampling clock Ref-CK, “0, 0, 0” from the most significant bit (MSB) Sampling outputs S0 to S2 are obtained.

  However, in the synchronous counter circuit, the longest signal path (critical path: the path U0 → AND2 → AND3 → EXOR3 → U3 shown by the broken line in FIG. 1) extends according to the number of flip-flops to be counted, and therefore has a high frequency. Not suitable for operation.

  That is, the critical path indicated by a broken line in FIG. 1 needs to reach the final flip-flop U3 within one cycle of Ref-CK. However, when the number of flip-flops increases, the critical path is within one cycle of Ref-CK. Will not reach the final flip-flop.

  Furthermore, since the synchronous counter circuit drives all clocks with the highest frequency clock, there is a problem that power consumption increases and power supply noise also increases.

  FIG. 3 is a diagram showing an example of the asynchronous counter circuit, and FIG. 4 is a timing diagram for explaining the operation of the counter circuit of FIG. In order to simplify the explanation, FIG. 3 shows Q0 to Q3, but FIG. 4 shows only Q0 to Q2.

  As shown in FIG. 3, the asynchronous counter circuit includes a counter unit 211 and a sampler unit 212, and the sampler unit 212 samples and outputs the value counted by the counter unit 211.

  The counter unit 211 includes flip-flops U0, U1, U2, and U3, and the sampler unit 212 includes flip-flops V0, V1, V2, and V3.

  Here, in the counter unit 211, the counter clock CK-DCO is supplied to the clock input CK of the first flip-flop U0, and the NQ output of the previous flip-flop U0 is supplied to the clock input CK of the flip-flop U1. Have been supplied.

  Similarly, the NQ output of the preceding flip-flop U1 is supplied to the clock input CK of the flip-flop U2, and the NQ output of the preceding flip-flop U2 is supplied to the clock input CK of the flip-flop U3. .

  Here, in the flip-flops U0 to U3 of each stage, the NQ outputs of the flip-flops U0 to U3 are supplied to the D input.

  Similar to the sampler unit 112 in FIG. 1, the sampler unit 212 outputs the Q outputs (Q0, Q1, Q2, Q3) of the flip-flops U0, U1, U2, U3 of the counter unit 211 to the corresponding flip-flops V0, V1. , V2 and V3 are received by D input.

  The sampling clock Ref-CK is supplied to the clock input CK of V0 to V3, and Q0 to Q3 are taken in by the Ref-CK, respectively, and the sampling outputs S0 to S3 are output from the Q outputs of V0 to V3. It has become.

  In the counter unit 211 of FIG. 3, the path of the counter clock CK-DCO for each of the flip-flops U0 to U3 indicated by thick solid lines indicates a delay path necessary for passing through the counting flip-flop in order to perform sampling correctly.

  That is, this delay path becomes a path from each NQ output of the preceding flip-flops U0, U1, U2 to each clock input CK of U1, U2, U3 in the second and subsequent flip-flops U1, U2, U3. .

  The path from the NQ output of the flip-flop U0 to the D input of the U0 indicated by a broken line corresponds to a critical path of the data signal, and the NQ output of the flip-flop U0 is connected to the D input within one cycle of the sampling clock Ref-CK. Need to reach. This path is formed in each flip-flop U0-U3.

  Further, the path indicated by the alternate long and short dash line indicates the earliest signal path through which the counter clock CK-DCO is supplied to the clock input CK of the first-stage flip-flop U0. In the sampler unit 212, a path indicated by a two-dot chain line indicates a path of the sampling clock Ref-CK to the flip-flop V3 at the final stage. Thus, in the asynchronous counter circuit, there is no problem in the synchronous counter circuit as described above.

  As shown in FIG. 3, in the asynchronous counter circuit, in the counter unit 211, the clock input CK-DCO is supplied to the clock input CK of the first stage flip-flop U0, but the clock inputs of U1 to U3 in the second and subsequent stages. The NQ outputs of U0 to U2 in the previous stage are supplied to CK.

  That is, since each stage (flip-flop) uses the output of the previous stage as a clock, the delay is integrated (added in order) by each stage. Therefore, when the delay increases, a race problem occurs. When this race condition occurs, it becomes difficult to correctly sample the output of each stage.

  Here, the delay time td of each stage is sequentially added by the flip-flops U0 to U2. Specifically, for example, the Q output (Q0) of the flip-flop U0 includes a delay of td, but the Q output (Q1) of U1 includes a delay of 2td, and further, the Q output (Q2) of U2 Will include a delay of 3 td.

  That is, as shown in FIG. 4, when the flip-flops V0 to V2 of the sampler unit 212 take in Q0 to Q2 at the rising timing of Ref-CK, the delay times td, 2td, and 3td are added in order. The correct count value cannot be imported.

  This is because there is more delay integrated from the flip-flop far from the input clock, and therefore there is usually a high possibility that an error will occur in the output of the flip-flop far from the input clock. That is, in the example of FIGS. 3 and 4, for example, the flip-flop U2 of the counter unit 211 is farther than U0 and U1 to which CK-DCO is input, so that the integrated delay increases and the output Q2 However, a race is more likely to occur than the outputs Q0 and Q1.

  Specifically, in the case of FIG. 4, the sampling outputs S0 to S2 to be “0, 0, 0” from the MSB are “1, 1, 0”. This is because the delay is integrated by each stage to cause a race, and the sampling outputs S0 to S2 are incorrect.

  Hereinafter, embodiments of a counter circuit and a sampling correction method of the counter circuit will be described in detail with reference to the accompanying drawings. FIG. 5 is a diagram showing the counter circuit of this embodiment. In FIG. 5, reference numeral 11 indicates a counter unit, 12 indicates a sampler unit, and 13 indicates a determination unit.

  As shown in FIG. 5, the counter circuit of the present embodiment is an asynchronous counter circuit, and includes a counter unit 11, a sampler unit 12, and a determination unit 13, and the counter unit 11 includes flip-flops U0 and U1. , U2, ..., UN-1.

  Here, the counter clock CK-DCO is supplied to the clock input CK of the first flip-flop U0, and the NQ output of the previous flip-flop U0 is supplied to the clock input CK of the flip-flop U1.

  Similarly, the NQ outputs of the preceding flip-flops U1, U2,..., UN-2 are supplied to the clock inputs CK of the flip-flops U2, U3,. Here, in the flip-flops U0 to UN-1 of each stage, the NQ outputs of the flip-flops U0 to UN-1 are supplied to the D input.

  The sampler unit 12 includes flip-flops W0, W1, and W2, VA0 to VAN-1, VB0 to VBN-1, and VC0 to VCN-1. Here, the flip-flops W0, W1, and W2 are for generating sampling clocks Ref-CK [0], Ref-CK [1], and Ref-CK [2].

  That is, the sampling clock Ref-CK is supplied to the D input of the flip-flop W0, and the counter clock CK-DCO is supplied to the clock input CK of W0.

  Further, the Q output of the flip-flop W0 is supplied to the D input of the flip-flop W1, and the Q output of the flip-flop W1 is supplied to the D input of the flip-flop W2. A counter clock CK-DCO is supplied to the clock inputs CK of W1 and W2.

  Here, the Q output of the flip-flop W0 is used as the first sampling clock Ref-CK [0] for the flip-flops VA0 to VAN-1, and the Q output of W1 is the second sampling for the VB0 to VBN-1. Used as clock Ref-CK [1]. Further, the Q output of W2 is used as the third sampling clock Ref-CK [2] for VC0 to VCN-1.

  Note that the first, second, and third sampling clocks Ref-CK [0], Ref-CK [1], and Ref-CK [2] are continuous with rising timings synchronized with the cycle of the counter clock CK-DCO. There are three sampling clocks.

  That is, the timing (rise timing) of the first sampling clock Ref-CK [0] and the second sampling clock Ref-CK [1] is shifted by one cycle of the counter clock CK-DCO. The timings of the second sampling clock Ref-CK [1] and the third sampling clock Ref-CK [2] are also shifted by one cycle of the counter clock CK-DCO.

  As described above, the sampler unit 12 includes the first to third sampler units (flip-flops) VA0 to VAN-1 in which the first to third sampling clocks Ref-CK [0] to [2] are supplied to the clock input CK. , VB0 to VBN-1, and VC0 to VCN-1.

  The sampler units VA0 to VAN-1, VB0 to VBN-1, VC0 to VCN-1 correspond to the sampler units 112 and 212 shown in FIGS. 1 and 3, respectively, and are respectively flip-flops U0 to UN of the counter unit 11. -1 Q output (Q1 to QN-1) is captured.

  That is, the D inputs of VA0 to VAN-1 in the first sampler unit are connected to the Q outputs of U0 to UN-1 of the counter unit 11, and the data Q1 to Q1 at the rising timing of the first sampling clock Ref-CK [0]. Capture QN-1.

  In addition, the D inputs of VB0 to VBN-1 in the second sampler unit are connected to the Q outputs of U0 to UN-1 of the counter unit 11, and the data Q1 to Q2 at the rising timing of the second sampling clock Ref-CK [1]. Capture QN-1.

  Further, the D inputs of VC0 to VCN-1 in the third sampler unit are connected to the Q outputs of U0 to UN-1 of the counter unit 11, and the data Q1 to Q1 are output at the rising timing of the third sampling clock Ref-CK [2]. Capture QN-1.

  Note that the first sampling clock Ref-CK [0], the second sampling clock Ref-CK [1], and the third sampling clock Ref-CK [2] are three consecutive in synchronization with the cycle of the counter clock CK-DCO. Sampling clock.

Determining unit 13, a sampling output SA ₀ -SA _N-1 of the first sampler unit, the sampling output SC ₀ to SC _N-1 sampling output SB ₀ to SB _N-1 and the third sampler unit of the second sampler unit The output OUT is output after performing the determination described later.

Note that the determination unit 13 performs sampling as described later with reference to FIG. 7 in addition to the sampling outputs SA _{0 to} SA _N−1 , SB _{0 to} SB _N−1, and SC _{0 to} SC _N−1 . The outputs SD _{0 to} SD _N-1 may be received.

  Here, with respect to the flip-flop U0 to which the counter clock CK-DCO is input, a farther flip-flop (a flip-flop closer to UN-1: a flip-flop on the most significant bit (MSB) side) or an integrated delay Will increase. Therefore, an error (race) is likely to occur in the output of the flip-flop on the MSB side.

  In general, since the asynchronous counter is a binary counter, the probability that the output of the flip-flop on the MSB side changes is smaller. The change probability of the output (Q0 to QN-1) of this flip-flop is 1 / 2k in the case of binary. Here, k is the position of the flip-flop in the counter unit 11.

  Further, for example, even if a race occurs, the values of all output data are not wrong, and the value of the output data must not change at the sampling instant in the sampler unit 12 regardless of the integrated delay. No problem even if there is a race.

  Specifically, in the example of FIG. 6 to be described later, the values of Q2 and Q3 of cycle “0”, Q2 of cycle “4”, Q2 and Q3 of cycle “8”, and Q2 of cycle “12” are erroneously set. Yes. That is, it can be seen that all these errors are caused by the timing at which the values of Q2 and Q3 change due to the integrated delay.

  Therefore, in this embodiment, the output (Q0 to QN-1) of the counter unit 11 is not captured by the sampler unit 12 with one sampling clock, but is captured with a plurality of sampling clocks (at least three times). The correct count value is calculated.

  In FIG. 5, three sampler units controlled by three sampling clocks are provided. However, this may supply a plurality of sampling clocks at different timings to one sampler unit. Of course.

  6 and 7 are timing charts for explaining the operation of the counter circuit of FIG. Although the counter circuit of FIG. 5 processes N bits, FIGS. 6 and 7 show only 4 bits of Q0 to Q3 in order to simplify the description.

  As shown in FIG. 5, for example, the Q outputs (Q0 to Q3) of the flip-flops U0 to U3 are taken into three sampler units (VA0 to VA3, VB0 to VB3, VC0 to VC3), and are respectively used as sampling outputs. Is output.

  In the example of FIG. 6, in three consecutive cycles “8”, “9”, and “10”, outputs Q0 to Q3 are output by three sampler units by sampling clocks Ref-CK [0], [1], and [2]. Capture.

That is, as shown in FIG. 6, the sampling outputs SA _{3 to} SA ₀ of the first sampler unit become Q outputs of the flip-flops VA3 to VA0 and become “ ₀ , ₁ , ₀ , ₀ ” from the MSB.

Further, the sampling outputs SB _{3 to} SB ₀ of the second sampler unit become Q outputs of the flip-flops VB _{3 to} VB ₀ and become “1, ₀ , ₀ , ₁ ” from the MSB. Further, the sampling outputs SC _{3 to} SC ₀ of the third sampler unit become Q outputs of the flip-flops VC _{3 to} VC ₀ and become “1, ₀ , ₁ , ₀ ” from the MSB.

  By the way, as described above, the delay time td is sequentially added (integrated) as the output of the counter (flip-flop) in the subsequent stage increases the delay, but even if a race occurs, all signals (sampling) The output is not wrong.

Specifically, in the three sampling outputs by the above-described three consecutive sampling clocks Ref-CK [0], [1], [2], the sampling outputs SB _{3 to} SB _{0 of} “1, 0, 0, 1”. The sampling outputs SC _{3 to} SC ₀ of “1, _0, 1, _0” are continuous.

That is, “1, ₀ , ₀ , 1” of sampling outputs SB _{3 to} SB ₀ plus “1” becomes “1, ₀ , 1, ₀ ” of sampling outputs SC _{3 to} SC _0. Yes. Therefore, in this case, it is determined that “ ₀ , ₁ , ₀ , ₀ ” of the sampling outputs SA _{3 to} SA ₀ includes errors due to the race, and the sampling outputs SB _{3 to} SB ₀ and SC _{3 to} SC _{0 are} detected. Use the value from as the correct count value.

Specifically, since the value "1, 0, 0, 1" is correct count value of the sampling output SB ₃ to SB _0, for example, as the value of the correct sampling output SA ₃ -SA _0, the value of SB ₃ to SB ₀ " “1,0,0,0” obtained by subtracting “1” from “1,0,0,1” is output.

Here, different from the values shown, for example, SA ₃ -SA ₀ is "1,0,0,0", SB ₃ to SB ₀ is "0,0,0,1", SC ₃ to SC ₀ Is “1, 0, 1, 0”, Ref-CK [0] and [2] are shifted by two cycles of CK-DCO, and thus are determined to be correct count values.

That is, “ ₁ , ₀ , ₀ , ₀ ” of sampling outputs SA _{3 to} SA ₀ plus “2” becomes “ ₁ , ₀ , ₁ , ₀ ” of sampling outputs SC _{3 to} SC _0. Therefore, the values of SA _{3 to} SA ₀ and SC _{3 to} SC ₀ are used as correct count values. At this time, the values “ ₁ , ₀ , ₀ , ₀ ” of the sampling outputs SA _{3 to} SA ₀ are output.

  Here, in the example of FIG. 5 and FIG. 6, the case where the sampling is performed three times is shown, but the number of times of the sampling is defined by, for example, a guaranteed delay range. However, when sampling is performed a plurality of times, in order to obtain at least two correct sampling outputs, it is preferable to set the number of samplings to at least three.

Next, as shown in FIG. 7, the sampling outputs SA _{3 to} SA ₀ of the first sampler unit become the Q outputs of the flip-flops VA3 to VA0 and become “ ₀ , 1, 1, ₀ ” from the MSB.

Further, the sampling outputs SB _{3 to} SB ₀ of the second sampler unit become Q outputs of the flip-flops VB _{3 to} VB ₀ and become “1, ₀ , ₀ , ₁ ” from the MSB. Further, the sampling outputs SC _{3 to} SC ₀ of the third sampler unit become Q outputs of the flip-flops VC _{3 to} VC ₀ and become “1, ₀ , ₁ , ₀ ” from the MSB.

In FIG. 7, a fourth sampler unit (not shown) driven by the fourth sampling clock Ref-CK [3] is further considered, and sampling outputs (SD _{3 to} SD ₀ ) of the fourth sampler unit are shown. ing. Specifically, the sampling outputs SD _{3 to} SD ₀ of the fourth sampler unit are Q outputs of the flip-flops (VD3 to VD0), and become “1, 0, 1, 1” from the MSB.

Accordingly, in the four sampling outputs by the four consecutive sampling clocks Ref-CK [0] to [3] described above, “1, 0, 0, 1”, “1, 0, 1, 0” and “1, It can be seen that the sampling output of “0, 1, 1” is the correct count value. That is, the values based on the sampling outputs SB _{3 to} SB ₀ , SC _{3 to} SC ₀ and SD _{3 to} SD ₀ are used as correct count values.

  Here, in the example of FIG. 7, the values of Q0, Q1, Q2, and Q3 of cycles “0”, “1”, “4”, “8”, and “12” are incorrect.

That is, since the values “1, ₀ , ₀ , 1” of the sampling outputs SB _{3 to} SB ₀ are correct count values, for example, as the values of the correct sampling outputs SA _{3 to} SA ₀ , the values “1, ₃ of SB _{3 to} SB ₀ are set. “1,0,0,0” obtained by subtracting “1” from “0,0,1” is output.

For example, when the values of SA _{3 to} SA _{0 and} the values of SC ₃ to SC ₀ are shifted by “2” corresponding to two cycles of CK-DCO, or the values of SA _{3 to} SA ₀ and SD ₃ When the value of .about.SD ₀ is shifted by “3” corresponding to three cycles of CK-DCO, it is determined that the count value is correct.

  Here, the sampling clock Ref-CK does not necessarily need to change every cycle of the counter clock CK-DCO. For example, when the sampling clock Ref-CK changes every two cycles of the counter clock CK-DCO, it is determined that the count value taken by the successive sampling clocks is different by “2” as the correct count value.

Specifically, in FIG. 6, when the rising timings of Ref-CK [1] and [2] are shifted by two cycles of CK-DCO, SB _{3 to} SB ₀ are changed to “1, _{0, 0, 1} If SC _{3 to} SC ₀ are “1, ₀ , 1, 1” from the MSB, it is determined that the count value is correct. That is, it is correct if it is shifted by “2”.

At this time, since the values “1, ₀ , ₀ , 1” of the sampling outputs SB _{3 to} SB ₀ are correct count values, for example, as the values of the correct sampling outputs SA _{3 to} SA ₀ , the values “1” of SB _{3 to} SB ₀ are set. , 0, 0, 1 ”minus“ 1 ”is output.

  As described above, the number of sampling clocks Ref-CK for capturing the count output (Q0 to QN-1) of the counter unit 11 may be three or more, and the interval of Ref-CK is an arbitrary value of CK-DCO. Period may be sufficient. Note that the sampling value taken in by Ref-CK is determined to be a correct count value when it has a difference in count value defined by the interval of Ref-CK.

FIG. 8 is a flowchart showing an example of processing in the counter circuit of this embodiment. Here, the reference symbol SA corresponds to the sampling outputs SA _{0 to} SA _N-1 in FIG. 5 or SA _{0 to} SA ₃ in FIGS. 6 and 7, and SB is SB _{0 to} SB in FIG. _N-1 or SB _{0 to} SB ₃ in FIGS. 6 and 7. Furthermore, reference signs the SC, SC ₀ to SC _N-1 in FIG. 5, or, corresponding to the SC ₀ to SC ₃ in FIGS.

  As shown in FIG. 8, when an example of the sampling correction processing of the counter circuit starts, it is determined in step ST11 whether SA and SB are continuous. That is, for example, when the SA sampling clock Ref-CK [0] and the SB Ref-CK [1] have a difference of one cycle of the counter clock CK-DCO, “1” is subtracted from the SB. Determine if the thing is SA.

  If it is determined in step ST11 that SA and SB are continuous, the process proceeds to step ST12, and the value of SA is output (OUT = SA). If it is determined in step ST11 that SA and SB are not continuous, the process proceeds to step ST13 to determine whether SC-SA is “2”.

  That is, in step ST13, for example, when Ref-CK [0] of SA and Ref-CK [2] of SC have a difference of two cycles of CK-DCO, “2” is subtracted from SC. Determine if the thing is SA.

  If it is determined in step ST13 that SC-SA = 2, the process proceeds to step ST12, and the value of SA is output (OUT = SA). If it is determined in ST13 that SC-SA = 2 is not satisfied, the process proceeds to step ST14.

  In step ST14, it is determined whether SB and SC are continuous. That is, whether or not SB and SC are continuous is determined in the same manner as the determination of whether SA and SB are continuous in step ST11 described above.

  If it is determined in step ST14 that SB and SC are continuous, that is, if it is determined that the value obtained by subtracting "1" from SC is SB, the process proceeds to step ST15, and "1" is subtracted from SB. Output (OUT = SB-1).

  If it is determined in step ST14 that SB and SC are not continuous, the process proceeds to step ST16, where the output is set to a default value (OUT = DefVal) and the process is terminated. Normally, the design is such that the process ends at step ST12 or ST15 and does not proceed to step ST16.

  FIG. 9 is a flowchart showing another example of the sampling correction process in the counter circuit of this embodiment, which corresponds to a generalized process of FIG. Here, SA, SB, and SC in FIG. 8 described above correspond to, for example, S [0], S [1], and S [2].

  As shown in FIG. 9, when another example of the sampling correction processing of the counter circuit starts, it is determined in step ST21 whether Mod (S [n] -S [ni], N) = i is satisfied. .

  That is, in step ST21, it is determined whether or not the remainder obtained by dividing S [n] -S [n-i] by N is equal to i. Here, Mod (fun, N) is Mod (fun, N) = fun if fun ≧ 0, and Mod (fun, N) = N + fun if fun <0.

Here, the value of Mod (fun, N) always exists between 0 and N. As initial conditions, n = 1 and i = 1. Further, N is the maximum count value of the counter. For example, in the example of FIG. 7, N = 2 ⁴ = 16 incremented one by one in 0 to 15 cycles.

  Specifically, in step ST21, if the initial conditions are n = 1, i = 1, and N = 16 as an example, the counter output S [0] = 16, S [1] = 1, so Mod (S [ n] −S [ni], N) is Mod (S [1] −S [0], N) = Mod (1-16, 16) = 1 = i.

  In this case, in step ST21, it is determined that Mod (S [n] −S [ni], N) = i is established, and the process proceeds to step ST22 to output the value of Mod (S [n] −n, N). (OUT = Mod (S [n] -n, N)).

  On the other hand, if it is determined in step ST21 that Mod (S [n] −S [n−i], N) = i is not satisfied, the process proceeds to step ST23, where it is determined whether n = N−1 is satisfied.

  If it is determined in step ST23 that n = N−1 is not satisfied, n is incremented by “1” (n = n + 1), and the process returns to step ST21 described above. That is, in step ST21, for example, it is determined whether Mod (S [2] −S [1], N) is “1”.

  On the other hand, if it is determined in step ST23 that n = N−1 is established, the process proceeds to step ST24, where it is determined whether i = N−1 is established, and if i = N−1 is not established, As i = i + 1 and n = i, the process returns to the above-described step ST21. That is, in step ST21, for example, it is determined whether Mod (S [2] −S [0], N) is “2”.

  If it is determined in step ST24 that i = N−1 is established, the process proceeds to step ST25, where the output is set to the default value (OUT = DefVal), and the process is terminated. Normally, the design is such that the process ends at step ST22 and does not proceed to step ST24.

  FIG. 10 is a flowchart showing still another example of the sampling correction process in the counter circuit of the present embodiment. In the sampling correction process of FIG. 9 described above, a process for determining whether the count value is correct only kmat times. It corresponds to the added one.

  That is, in the example of FIG. 10, even when a plurality of errors are accidentally overlapped in the sampling output, a more correct result is obtained by adding a condition that the count value is determined to be correct only kmat times. It is.

  In other words, the example of FIG. 9 changes the value of i or n, and if either condition is satisfied, the result is output, whereas in the example of FIG. 10, the condition is satisfied by kmat times. Otherwise, the result will not be output.

  As shown in FIG. 10, when yet another example of the sampling correction processing of the counter circuit starts, it is determined in step ST31 whether Mod (S [n] −S [ni], N) = i is satisfied. To do. Here, n = 1, i = 1, and k = 0 are set as initial conditions. Therefore, in step ST31, it is determined whether Mod (S [1] −S [0], N) = i is satisfied.

  If it is determined in step ST31 that Mod (S [n] −S [n−i], N) = i is established, the process proceeds to step ST32 to determine whether k is equal to kmat (k = kmat). That is, it is determined whether Mod (S [n] −S [n−i], N) = i in step ST31 is established kmat times.

  If it is determined in step ST32 that k = kmat is not satisfied, that is, kmat times have not yet been satisfied, n = n + 1 is set, and the process returns to step ST31. That is, in step ST31, for example, it is determined whether Mod (S [2] −S [1], N) = i is satisfied.

  If it is determined in step ST32 that k = kmat is established, the process proceeds to step ST33, and the value of Mod (S [n] −n, N) is output (OUT = Mod (S [n] −n, N). )

  On the other hand, if it is determined in step ST31 that Mod (S [n] −S [n−i], N) = i is not satisfied, the process proceeds to step ST34, and it is determined whether n = N−1 is satisfied. Here, N is the maximum count value of the counter as described with reference to FIG.

  If it is determined in step ST34 that n = N−1 is not satisfied, n is incremented by “1” (n = n + 1), and the process returns to step ST31 described above. That is, in step ST31, for example, it is determined whether Mod (S [2] −S [1], N) is “1”.

  On the other hand, if it is determined in step ST34 that n = N−1 is established, the process proceeds to step ST35, where it is determined whether i = N−1 is established, and if i = N−1 is not established, As i = i + 1 and n = i, the process returns to the above-described step ST31. That is, in step ST31, for example, it is determined whether Mod (S [2] −S [0], N) is “2”.

  If it is determined in step ST35 that i = N−1 is established, the process proceeds to step ST36, where the output is set to the default value (OUT = DefVal), and the process is terminated. Normally, the design is such that the process ends at step ST33 and does not proceed to step ST36.

  As described above, the sampling correction processing of the counter circuit shown in FIG. 10 is such that Mod (S [n] −S [ni], N) = i is kmat compared to the sampling correction processing of the counter circuit shown in FIG. This corresponds to the addition of step ST32 for determining whether or not the number of times is satisfied.

  Then, according to the sampling correction process of FIG. 10, for example, even if a plurality of errors are accidentally overlapped, it is determined whether or not kmat times are satisfied, thereby outputting a more correct count value than the sampling correction process of FIG. It becomes possible to do.

  FIG. 11 is a block diagram showing an example of an ADPLL to which the counter circuit of this embodiment is applied. In FIG. 11, reference numeral 2 indicates a calibration unit, and 3 indicates an all-digital PLL (ADPLL: All Digital Phase-Locked Loop).

  Here, the counter circuit of this embodiment corresponds to the calibration unit 2 and the counter 31 in the ADPLL 3. The counter clock CK-DCO corresponds to an output clock of a digitally controlled oscillator (DCO) 36, and the sampling clock Ref-CK corresponds to a clock supplied to the counter 31 and the TDC 32.

  As shown in FIG. 11, the calibration unit 2 includes a differentiation circuit 21, a digital loop filter 22, a memory 23, an adder 24, and a determination circuit 25. The ADPLL 3 includes a counter 31, a TDC (Time to Digital Converter) 32, a decoder 33, an adder 34, a digital loop filter 35, and a DCO 36.

  The differentiating circuit 21 differentiates the output C [n], C [n-1] of the counter 31 (for example, corresponding to S [n], S [n-1] described above) (ModB (C [n] -C [n-1]) The digital loop filter 22 averages the differentiated output, stores it in the memory 23, and supplies it to the adder 24.

  The adder 24 subtracts the second value output from the digital loop filter 22 from the first value stored in the memory 23, and the determination circuit 25 determines the output (subtraction result) of the adder 24. The

  Here, in the initial state, for example, the calibration unit 2 locks the ADPLL 3 with the maximum number of times of sampling, and if the value stored in the memory 23 and the output of the digital loop filter 22 match, Reduce.

  That is, in the output of the adder 24 supplied to the determination circuit 25, if the difference is small, the number of times of sampling is reduced. Conversely, if the difference is large, the number of times of sampling is increased and the calibration process of the calibration unit 2 is performed. To stop.

  In the ADPLL 3, the TDC 32, the decoder 33, the adder 34, the digital loop filter 35, and the DCO 36 can be applied as they are conventionally known, and as a result, are all digitized phase locked loops (PLL). Is configured.

  In the above, the counter circuit of the present embodiment is not limited to the application to the ADPLL as shown in FIG. 11, and is applied to various circuits as, for example, a clock for a frequency synthesizer or a processor of a wireless circuit system. be able to.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A counter unit that counts according to a counter clock to calculate a count value;
A sampling unit that captures the count value with at least three sampling clocks;
A determination unit that determines at least three sampling values captured by the at least three sampling clocks based on a timing shift in the at least three sampling clocks;
A counter circuit comprising:

(Appendix 2)
The at least three sampling clocks are continuous clocks having timings synchronized with a cycle of the counter clock.
The counter circuit according to appendix 1, wherein:

(Appendix 3)
The determination unit
When the first and second sampling values in the at least three sampling values correspond to a timing shift in the first and second sampling clocks that have captured the first and second sampling values, the first sampling value is , And determine and output a correct count value in the counter unit,
The counter circuit according to Supplementary Note 1 or Supplementary Note 2, wherein:

(Appendix 4)
The timing shift in the first and second sampling clocks is an arbitrary first period of the counter clock,
The first and second sampling values are shifted by a count value corresponding to the first period of the counter clock.
The counter circuit according to appendix 3, wherein:

(Appendix 5)
The difference in timing between the first and second sampling clocks is one cycle of the counter clock,
The first and second sampling values are shifted by a count value “1”.
The counter circuit according to appendix 4, wherein:

(Appendix 6)
The determination unit
Correspondence and determination between the first and second sampling values and the timing shift in the first and second sampling clocks that have taken in the first and second sampling values are performed a plurality of times for different first sampling values. Do,
6. The counter circuit according to any one of appendix 3 to appendix 5, wherein

(Appendix 7)
An all-digital PLL comprising the counter circuit according to any one of appendix 1 to appendix 6.

(Appendix 8)
Count according to the counter clock to calculate the count value,
Capturing the count value with at least three sampling clocks;
Determining and correcting at least three sampling values captured by the at least three sampling clocks by a timing shift in the at least three sampling clocks;
A sampling correction method for a counter circuit.

(Appendix 9)
The at least three sampling clocks are continuous clocks having timings synchronized with a cycle of the counter clock.
The sampling correction method for a counter circuit according to appendix 8, wherein

(Appendix 10)
The determination and correction are performed.
When the first and second sampling values in the at least three sampling values correspond to a timing shift in the first and second sampling clocks that have captured the first and second sampling values, the first sampling value is The correction is performed by determining the correct count value in the counter unit.
The sampling correction method for a counter circuit according to appendix 8 or appendix 9, wherein

(Appendix 11)
The timing shift in the first and second sampling clocks is an arbitrary first period of the counter clock,
The first and second sampling values are shifted by a count value corresponding to the first period of the counter clock.
The sampling correction method of the counter circuit according to appendix 9, wherein

2 Calibration section 3 ADPLL
11, 111, 211 Counter unit 12, 112, 212 Sampler unit 13 Judgment unit 21 Differentiating circuit 22, 35 Digital loop filter 23 Memory 24, 34 Adder 25 Judgment circuit 31 Counter 32 TDC (Time to Digital Converter)
33 Decoder 36 DCO (Digitally Controlled Oscillator)

Claims (9)

A counter unit that counts according to a counter clock and calculates a count value asynchronous to the counter clock ;
A sampling unit that captures the count value with at least three sampling clocks;
A determination unit that determines at least three sampling values captured by the at least three sampling clocks based on a timing shift in the at least three sampling clocks;
An asynchronous counter circuit characterized by comprising: The at least three sampling clocks are continuous clocks having timings synchronized with a cycle of the counter clock.
The asynchronous counter circuit according to claim 1, wherein: The determination unit
When the first and second sampling values in the at least three sampling values correspond to a timing shift in the first and second sampling clocks that have captured the first and second sampling values, the first sampling value is , And determine and output a correct count value in the counter unit,
The asynchronous counter circuit according to claim 1, wherein the asynchronous counter circuit is provided. The counter unit includes n flip-flops, where n and m are integers of 2 or more and n ≧ m,
The counter clock is supplied to the clock input of the first flip-flop of the first stage in the n flip-flops,
The inverted output of the m−1th flip-flop of the preceding stage is supplied to the clock input of the mth flip-flop of the mth stage in the n flip-flops,
In each flip-flop of each of the n flip-flops, an inverted output of the flip-flop of that stage is supplied to each data input.
The asynchronous counter circuit according to any one of claims 1 to 3, wherein: The sampling unit
Including at least three sampler units that capture the count value with the at least three sampling clocks;
Each of the sampler units
N flip-flops corresponding to the n flip-flops in the counter unit and receiving the output of each flip-flop in the counter unit at a data input,
The asynchronous counter circuit according to claim 4, wherein: All-digital PLL, characterized in that it comprises an asynchronous counter circuit according to any one of claims 1 to 5. Counting according to the counter clock, calculating a count value asynchronous to the counter clock ,
Capturing the count value with at least three sampling clocks;
Determining and correcting at least three sampling values captured by the at least three sampling clocks by a timing shift in the at least three sampling clocks;
A sampling correction method for an asynchronous counter circuit. The count value is calculated by using n flip-flops where n and m are integers of 2 or more and n ≧ m.
Supplying the counter clock to the clock input of the first flip-flop of the first stage in the n flip-flops;
Supplying the inverted output of the m-1st flip-flop of the preceding stage to the clock input of the mth flip-flop of the mth stage in the n flip-flops;
In each flip-flop of each of the n flip-flops, an inverted output of the flip-flop of that stage is supplied to each data input, and a count value asynchronous with the counter clock is calculated.
The sampling correction method for an asynchronous counter circuit according to claim 7. To capture the count value,
The at least three sampler units capture the count value with the at least three sampling clocks,
Each of the sampler units
N flip-flops corresponding to the n flip-flops in the counter unit and receiving the output of each flip-flop in the counter unit at a data input,
The sampling correction method for an asynchronous counter circuit according to claim 8.

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