JP5762154B2 - Information processing apparatus, information processing method, and program - Google Patents

Description

  The present invention relates to a technique for facilitating a debugging operation of a control program.

≪Regarding target area≫
Today, in FA (factory automation) systems and PA (process automation) systems, programmable CPU devices, that is, programmable controllers (PLCs, sequencer devices) are used as devices for sequence control.
FA system control programmers (system integrators, component manufacturers of FA system components, etc.) create (cross-develop) control programs for sequencer devices on FA dedicated engineering environment software that runs on a personal computer. Is common.
The engineering environment software compiles the control program created by the programmer into an intermediate language program that can be interpreted in the sequencer device, and downloads it to the sequencer device.
The sequencer device having the intermediate language program downloaded operates the FA / PA system by controlling sensors and motors via various input / output units and networks according to the control program.
The control program for the FA / PA system is different from a normal embedded system in that the programming is performed by the general end user, not the manufacturer of the sequencer device, and the control program is controlled in the user's FA system. That it is a macro element, that is, the control target can be a meaningful unit in the entire FA / PA system.
This meaningful unit of control target (variable, device) is sometimes called a label or a system label.

≪Control program operation≫
The control program created by the programmer includes five languages defined in the international standard IEC61131-3, instruction list (IL), ladder (LD), structured text (ST), function block diagram (FBD), and sequential function chart (SFC). It is often described by.
It may also be written in a general-purpose programming language such as C or C ++.
The FA / PA system is an embedded system, and the control target is usually a physical machine.
For this reason, not only debugging the control program on the desk, but also checking the operation timing etc. by combining the control program and the actual machine system to be controlled at the final stage of program creation or at the stage of starting up the line at the factory. It is necessary to make fine adjustments.
Also, it is not uncommon for FA / PA systems to operate for decades due to their nature.
However, the control program is not not changed over the long term.
For example, in the case of a factory production line, etc., the control program may be modified little by little as the specifications of the product to be manufactured change.
In these correction processes, engineering terminals are often connected to sequencer equipment during line operation, and changes are often made on the spot.
This adjustment or change may be performed by a low-level language at a machine language level that corresponds to an intermediate language, such as a ladder (LD) or an instruction list (IL).
This is because it is not a control programmer (device manufacturer) that performs this work, but is often an expert (end user) of the machine or production line. This is because this procedure is omitted because it takes time to change the upstream design (high-level language) for correction.
For this reason, unless a planned backup operation is performed, a “master program” that is consistent with the control program that operates the actual machine system in operation may not be stored in an office or the like.
In the first place, there are not a few users who consider the intermediate language program stored in the sequencer device of the operating real system as the “master program”.
Therefore, in the FA / PA system, it is necessary to consider that the control program targeted particularly at the time of maintenance is written in a machine language level language such as IL or LD.

≪About the difficulty of debugging / maintenance work≫
In the FA / PA system, “structuring support at the control program design stage”, “improvement of debugging efficiency at the control program test stage”, and “rapid recovery at the time of failure in the actual system operation stage” are major issues.
There are many engineering environments that support the standardization and structuring of control programs using function blocks (FB) defined in IEC 61131-3, but users who can effectively use FB (especially end users) The fact is that there are not many.
The reason why structured programming using FB is hindered is that it is difficult to design in advance before programming which part of the control program should be cut out and structured and defined as a reusable program part. One is considered.
For faults that occur during the operation of the actual system and stop the production line of the factory, the time spent for recovery becomes the line stop time as it is, which is directly linked to the loss of the end user. Recovery is necessary. In order to shorten the time spent investigating the cause of the failure, a highly readable control program is required.
However, when a control program for the FA / PA system is created by LD or IL, a “roll” program having thousands of lines is described. Programs written in LD or IL are difficult to have a structure, and these are difficult to put comments in language specifications, and thus tend to be difficult to understand when viewed by others. In order to correctly interpret a program written in LD or IL in a short time, it is necessary to be skilled in the LD, IL language, and control program.
For example, paying attention to a device that has failed during maintenance of the actual system, search the control program for the rung (LD language circuit block) in which this device is a coil (output), and use that rung as a condition. Identify the contact (input condition) device (usually multiple) being used, and search for the rung that is the coil. . . Thus, it is possible to comprehensively check devices and processes that have an influence on a device in which a failure has become apparent.
However, in this method, the search tree is branched every time it goes back from the coil to the contact point, so the user needs to memorize the intermediate state.
Also, it is necessary to check from time to time whether the contacts and the coil are circulating (whether there is no repetition in the search tree).
Note that the control programmer usually describes the processing based on the device appearing in the coil.
That is, the double coil (the same coil output appears at a plurality of locations in the program) is often not preferred.
However, the ladder language contact-coil relationship defines ON / OFF of the device written on the coil at the same time depending on the contact device condition, which is understandable for users who are used to general-purpose programming languages such as C language. There is a difficult point.
For this reason, an increasing number of programmers explicitly write device ON / OFF by a SET command or a RESET command.
That is, in this case, the width of each branch in the coil-> contact device search increases, which imposes a further burden on the user.

≪About prior art≫
As techniques for facilitating debugging of a control program, several techniques have been disclosed so far for visually providing the analysis result and monitor result of the control program to the user using a GUI (Graphical User Interface).
For example, in Patent Document 1, as a method for monitoring a control program for debugging, a flow diagram such as an SFC language expression of the control program is displayed on the screen, and the activation / inactivation state of the block of the control program is displayed on this screen. A method is disclosed in which a monitor result is visibly expressed, for example, by displaying.
Further, Patent Document 2 discloses a method of converting a control block call relationship into a tree structure and displaying the control program in a form corresponding to the original control program for a control program structured by the FB language or the like. .
In Patent Document 3, the control program is scanned and an output command part is extracted, and by creating an outline indicating where the output of the used device is executed in the entire control program, debugging is facilitated. Disclosed is a method to realize.
In Patent Document 4, in order to increase the amount of information in the LD language format that can be displayed in one screen in order to identify a device that causes a failure, a control program is displayed in a simplified format in the LD language display, A method for displaying related detailed information in another detail screen is disclosed.
As described above, the control program itself and the device search result in the control program are displayed in the SFC language, LD language format or similar outline format, thereby facilitating debugging of the control program. Technology.

A general program analysis technique is a “flow graph”.
This is a directed graph showing the dependency between processes (controls) in a program used in the program slicing technology (Non-patent Document 1) or the like.

JP 2001-154711 A JP 2004-303217 A JP 2006-318504 A Japanese Patent Laid-Open No. 2003-084811

"Program Slicing Technology and Applications", ISBN4-320-02743-4, Takao Shimomura, Kyoritsu Shuppan, 1995

As described above, due to the nature of the control program, a machine language level code operating in the actual machine system is often considered as a master program. In addition, there is no guarantee that a user can have a more readable advanced language program or internal specification that is consistent with the intermediate code at the machine language level.
Therefore, when targeting the FA / PA system, it is necessary to assume that the control program is written in the LD or IL language.
On the other hand, skillful techniques are required to program machine language level codes such as LD and IL, and to use only these codes to perform debugging and investigate the cause of failure in a short time. is there.
In other words, the FA / PA system has the problem of "targeting machine language level languages such as LD and IL, while enabling non-expert users to debug and investigate failure factors in a short time." There is.

  The main object of the present invention is to solve such a problem, and it is a main object of the present invention to generate a graph that visualizes a control algorithm defined in a control program in an easily understandable format.

An information processing apparatus according to the present invention includes:
From a control program in which a plurality of devices are described and dependencies between the devices are described, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependencies between the devices. A device extractor for extracting the description;
A dependency extraction unit that extracts a description of the dependency between devices from the control program;
Based on the description of the device extracted by the device extraction unit and the description of the dependency relationship between the devices extracted by the dependency relationship extraction unit, the node represents the device, the directed edge represents the dependency relationship between the devices, And a graph generation unit that generates a directed directed graph of a circuit representing a control algorithm defined by the control program as a connection between a node and a directed edge.

According to the present invention, a directed directed graph in which a control algorithm defined in a control program is represented by a connection between a node and a directed edge is generated.
For this reason, the control algorithm defined in the control program can be visualized in a format that is easy to understand, and debugging of the control program can be facilitated.

FIG. 3 is a diagram illustrating a configuration example of an information processing device according to first to third embodiments. FIG. 3 is a flowchart of graph display operation of the information processing apparatus according to the first embodiment. FIG. 6 is a flowchart of a corresponding control partial program display operation of the information processing apparatus according to the first embodiment. FIG. 3 is a flowchart of a specific device specification output operation of the information processing apparatus according to the first embodiment. FIG. 3 is a flowchart of an influence range illustrating operation of the information processing apparatus according to the first embodiment. FIG. 3 is a flowchart of an unused part detection operation of the information processing apparatus according to the first embodiment. FIG. 3 is a flowchart of a circulation definition detection operation of the information processing apparatus according to the first embodiment. FIG. 4 is a flowchart of device value monitoring operation of the information processing apparatus according to the first embodiment. FIG. 6 is a flowchart of a failure possibility factor illustrating operation of the information processing apparatus according to the first embodiment. The figure which shows the example of the control program by LD language concerning Embodiment 2. FIG. The figure which shows the graph display example 1 (schematic diagram) of the control program which concerns on Embodiment 2. FIG. FIG. 10 shows an example of a node structure according to the second embodiment. FIG. 6 shows an example of an edge structure according to the second embodiment. FIG. 10 is a diagram illustrating an example of connection information according to the second embodiment. The figure which shows the graph display example 2 (schematic diagram) of the control program which concerns on Embodiment 3. FIG. FIG. 10 is a diagram showing a graph display example (schematic diagram) illustrating an influence range according to the third embodiment. The figure which shows the graph display example (schematic diagram) of the circulation definition detection which concerns on Embodiment 3. FIG. FIG. 10 is a diagram showing an IL language expression of a control program example according to the second embodiment. FIG. 3 is a diagram illustrating a hardware configuration example of the information processing apparatus according to the first to third embodiments.

Embodiment 1 FIG.
≪Overview≫
First, an outline of the operation of the information processing apparatus according to the present embodiment will be described, and then a configuration example and details of an operation procedure will be described.

The information processing apparatus according to the present embodiment has a control program by extracting a variable (device) controlled by the control program as a node and extracting an interaction between devices as a dependency to obtain an edge. By holding the structure as a closed-circuit directed graph, it helps to improve the efficiency of user work and shorten the work time when designing or maintaining a control program.
Further, the information processing apparatus according to the present embodiment, for example, visually displays the relationship between devices used in the control program at the time of designing the control program, or displays the GUI at the time of control program maintenance. It has functions such as monitoring the device value on the dependency graph visually displayed.

  Here, a ladder (LD) language will be described as one of the languages targeted by the information processing apparatus according to the present embodiment, and an example of generating a closed-circuit directed graph from a control program written in the LD language will be described. To do.

Ladder (LD) language is a language that models electrical circuits.
In the LD language, one meaningful process is usually described in units of rungs (circuit blocks) between left and right buses.
In the circuit block, variables (devices) necessary for the processing appear in the form of contacts and coils.
Therefore, the LD language can be considered as a “processing-oriented language” that enumerates the processes between devices.
In the instruction list (IL) language, the constituent instructions can basically correspond one-to-one with the elements of the LD language.
However, the purpose of the control program is basically instructions to an actual physical device such as driving a physical machine or applying a voltage to an electronic device.
For example, suppose that it is necessary to control with the following specifications in a certain production line.
1) When the sensor A is ON and the push button B1 is pressed, the motor of the belt conveyor C rotates forward. 2) When the sensor A is ON and the push button B2 is pressed, the motor of the belt conveyor C rotates reverse. In this case, a ladder language (processing-oriented language) describes the above sentence 1) and sentence 2).
In the LD language, the sentences (processing) 1) and 2) are expressed as rungs, and each rung has A, B1, C (forward rotation) and A, B2, C (reverse rotation) as follows: The relationship between the three devices is described.
Sensor A: affects the forward / reverse rotation of the belt conveyor C. Push button B1: affects the forward rotation of the belt conveyor C. Push button B2: affects the reverse rotation of the belt conveyor C. Belt conveyor C ( Forward rotation): affected by sensor A and push button B1 Belt conveyor C (reverse rotation): affected by sensor A and push button B2

As described above, the concept of the display format according to the present embodiment expresses the relationship between the devices to be controlled, and in this embodiment, a method of holding it as a closed-circuit directed graph structure is used.
As described above, the purpose of the control program of the FA / PA system is to control a specific “device”.
Most of the control programs described in the LD language or IL language are described in a combination of “contact → coil”, and the unit processing itself is simple.
In addition, the FA / PA system control program has few features that use indirect addressing (pointer) or the like as an operation for the device.
Basically, since each device is defined as corresponding to a physically existing device, there are not many examples in which the device is used as a pointer or an index.

There is a “flow graph” as a general program analysis technique similar to the method of the present embodiment.
As described above, this is a directed graph showing the dependency relationship between processes (controls) in a program used in the program slicing technique (Non-patent Document 1) or the like.
The flow graph can be applied to all general programs, and can also be defined for the control program of the FA / PA system targeted by the information processing apparatus according to the present embodiment.
However, the flow graph is an abstract representation of the structure of the program, and does not correspond to anything specific to each graph element (node, edge).
In addition, the nodes of the flow graph itself include some processing, and the dependency of the processing itself is expressed as an edge.
However, the control program of the FA / PA system usually has a shallow control structure.
In other words, there is almost no structure such as an IF statement or a loop statement.
This is also due to repeated execution by cyclic calculation.
In the present embodiment, there are few reasons for expressing the dependency relationship between processes, but rather, it is considered that a user clearly understands that a variable (device) and a process are clearly separated in visualization.
As described above, visualization based on node and edge definitions such as a flow graph is not suitable for at least the control program of the FA / PA system.
In the first place, in the case of a general program, the variables themselves used are abstract, and pointers and arrays are frequently used, so the substance (memory area) of the variables is often not fixed.
For this reason, it is difficult to construct a graph structure as disclosed in the present embodiment.
However, when the target is limited to the control program of the FA / PA system, it is possible to construct a graph in more detailed device units.
In other words, the image is fixed by expressing the device as a node, and the displayed directed directed graph of a closed circuit is close to the image of the element group constituting the real machine system.
This embodiment is based on this feature of the control program of the FA / PA system.
I think that visualization by graph display helps the user to understand the control program intuitively.

This embodiment is characterized in that all the relationships between devices in a control program are once analyzed and visualized in a form of a directed graph in an intuitively understandable form.
For example, the relationship between the contact and coil used in LD and IL languages “A⇒B” (result B if condition A) is the simplest way to represent with a directed edge when the contact and coil are nodes. There is no simpler and more effective visualization method.
The directed graph with closed circuit disclosed in the present embodiment is useful in the design phase and maintenance phase of the control program of the FA / PA system.
For the former, analysis of the target control program helps support the structuring and reuse of the program. For the latter, monitoring on the graph makes it possible to visually perform debugging work, and it is easy to find the problem part (bug) in the entire control program with the minimum procedure. Therefore, it becomes a support for prompt investigation of the cause when a failure occurs.

<Description of configuration>
Hereinafter, a configuration example of the information processing apparatus 100 according to the present embodiment will be described with reference to FIG.

In FIG. 1, a control program intermediate code storage unit 101 is a memory in which a control program for the FA / PA system is stored.
The source code of the control program stored in the control program intermediate code storage unit 101 may be described in any language.
The intermediate code of the control program stored in the control program intermediate code storage unit 101 is expressed as a control program intermediate code 1010.
This control program intermediate code 1010 is the result of compiling a source code created by user programming in the engineering development environment of the FA / PA system.
As will be described later, this control program may be being created or may be completely completed.
Normally, this control program intermediate code 1010 is a compilation product of the engineering environment and is also a target to be downloaded to the sequencer device.
As described above, in the control program intermediate code 1010, a plurality of devices are described and dependency relationships between the devices are described, and a control algorithm for the plurality of devices is described based on the description of the plurality of devices and the description of the dependency relationship between the devices. Is defined.

The device extraction unit 102 extracts a description of a device used in the control program.
The extracted device is a contact device or a coil device when the control program is in the LD language, and a source device or a destination device specified as an operand when the control program is in the IL language.
The device extracted by the device extraction unit 102 is stored in the node structure storage unit 104 as node information.
For example, in the design stage of a control program, the device may be extracted every time a user creates a control program and creates a meaningful unit (for example, a rung in the LD language). In the maintenance stage, the entire control program that is in operation may be collectively performed when a failure occurs.

The dependency relationship extraction unit 103 extracts a description of dependency relationships between devices in the control program.
When the control program is in the LD language, for example, the dependency relationship between the device A specified by the contact and the device B specified by the coil, or the dependency between the comparison condition C and the operation target D is used. It is a relationship.
The dependency relationship extracted by the dependency relationship extraction unit 103 is stored in the edge structure storage unit 105 as edge information.
For example, in the design stage of the control program, the dependency relationship may be extracted every time a user creates a control program and creates a meaningful unit (for example, rung in LD language). In the system maintenance stage, the entire control program in operation may be collectively performed at the stage where a failure occurs.

The node structure storage unit 104 is an area for storing device information extracted by the device extraction unit 102.
Information stored in the node structure storage unit 104 is expressed as a node structure 1040.
In the node structure 1040, a device name or a label name named by the user is stored for the device.
The node structure 1040 is also provided with a storage area for the current value of the device for monitoring.

The edge structure storage unit 105 is an area for storing the dependency relationship between devices extracted by the dependency relationship extraction unit 103.
There are several types of dependencies between devices.
Taking the LD language as an example, for example, a contact A-coil relationship (D1⇒D2), a contact B-coil relationship (D1⇒D2), an arithmetic expression relationship (D2 = D1 + 1), and a conditional expression relationship (IF D1). > 0THEN D2 = 1).
In all these examples, device D2 is dependent on device D1.
The dependency relationship extraction unit 103 extracts combinations of these dependency relationships and two or more target devices.
The type of dependency relationship is stored as an edge structure 1050.
The combination of target devices is stored as an edge structure 1050 or connection information 1060 described later.

The connection information storage unit 106 is a storage area that holds a connection relationship between a node structure 1040 that stores devices and an edge structure 1050 that stores dependency relationships between devices.
The information stored in the connection information storage unit 106 is referred to as connection information 1060.
The connection information 1060 is information that associates the node structure 1040 and the edge structure 1050, that is, the device extracted by the device extraction unit 102 with the dependency extracted by the dependency extraction unit 103.

The graph generation unit 112 generates a closed circuit directed graph based on the description of the device extracted by the device extraction unit 102 and the description of the dependency relationship between devices extracted by the dependency relationship extraction unit 103.
More specifically, the graph generation unit 112 uses the node structure 1040, the edge structure 1050, and the connection information 1060, and uses the node structure 1040 device and the edge structure according to the association indicated in the connection information 1060. A cycle directed graph is generated by combining 1050 dependency relationships.
The directed circuit directed graph is a graph in which a node represents a device, a directed edge represents a dependency between devices, and a control algorithm defined by a control program is represented by a connection between the node and the directed edge.
An example of a directed circle directed graph will be described later.

The condition input unit 107 is a means for the user to input a condition for searching for an element in the graph and a condition for filtering through the GUI with respect to the closed-circuit directed graph generated by the graph generation unit 112.
For example, a node is specified by designating an arbitrary node on a graph displayed by the GUI.
Alternatively, the device group is selected by selecting an arbitrary region with respect to the graph.

The graph analysis unit 108 is an engine part that performs a graph analysis of the closed-circuit directed graph according to the application.
For example, the range of devices that can be influenced by the device group “selected” selected by the condition input unit 107 (all nodes that can be reached from the device group via the directed edge), or conversely, the condition input unit 107 For example, a range that can affect the designated device “at” (a node that can be reached from the device via the directed edge in the reverse direction) is extracted step by step.
In addition, the clustering of the entire graph is measured, and the degree of coupling between devices in the control program is calculated.
The graph analysis unit 108 can also use general graph analysis logic.

The result output unit 109 is a means for displaying the entire graph or the partial graph filtered by the graph analysis unit 108 to the user through the GUI.
Since the number of devices and the number of processes used in the control program of the FA / PA system can be enormous, the directed circle directed graph disclosed in the present embodiment may be large.
Therefore, the result output unit 109 has a graph enlargement / reduction display function, a function to display only the selected device / dependency, or a function to reduce the selected device group and display it as a single virtual device. Can have.
As a partial function of the result output unit 109, a general complex graph display technique or tool can be used.
The result output unit 109 is an example of a display unit.

The link management unit 110 is a means for associating the code of the control program with the elements (node: device, edge: rung (in the case of LD)) of the closed circuit directed graph obtained by converting the control program code.
The link management unit 110 is used to associate the graph displayed to the user through the GUI with the original control program code.
For example, when a node of the graph is selected, a corresponding device is searched from the original control program code, and all rungs (in the case of LD) in which the device is used are displayed in a list. When an edge is selected, a corresponding rung (in the case of LD) is displayed.
The link management unit 110 is used to realize these functions.
The link management unit 110 is an example of a program code extraction unit.

The online monitor unit 111 is means for communicating with an actual sequencer device and acquiring a current value of the device.
The device value acquired here is displayed on the GUI via the result output unit 109 when the current value is monitored using the graph display.
Many engineering development environments for general FA / PA systems realize an online monitoring function of devices on an existing programming language editor.
Therefore, the online monitor unit 111 may divert the device value acquisition function part used in this online monitor function.
The online monitor unit 111 is an example of a measurement value input unit.

≪Description of operation≫
<< 1. Graph display >>
The procedure for visually displaying the relationship between devices used in the control program on the GUI will be described below with reference to FIG.

First, in process 202, the user inputs a control program.
Subsequently, in process 203, compilation is executed.
However, if the input of the compilable unit is not completed, the process returns to the process 202 again and waits for the input of the control program.
When the input in the compilable unit is completed, the control program intermediate code 1010 is created by the compiling operation.
The processing up to this point can utilize the functions of a general FA / PA system engineering environment.

Subsequently, in process 204, the device extraction unit 102 extracts a device from the control program intermediate code 1010.
As a result, a list of devices used in the whole or part of the target control program can be acquired.
Such device information is stored in the node structure storage unit 104 as a node structure 1040.
At this time, various information about the device (for example, device type and label name) is also stored.
Similarly, in processing 205, the dependency relationship extraction unit 103 extracts dependency relationships from the control program intermediate code 1010.
As a result, the dependency relationship between the devices being processed in the whole or part of the target control program is extracted.
These pieces of information are stored in the edge structure storage unit 105 as the edge structure 1050.
As described later, the edge structure 1050 also stores positive logic / negative logic information and the like for use in graph analysis.
Again, various information about the edge (for example, the type of edge) is also stored.
Similarly, in processing 206, the dependency relationship extraction unit 103 constructs connection information 1060 from the control program intermediate code 1010 and the edge structure 1050.
Next, in process 207, the graph generation unit 112 uses the connection information 1060 representing the connection relationship between the node structure 1040 and the edge structure 1050 and the node structure 1040 and the edge structure 1050 linked to the connection information 1060 to direct the closed-circuit directed graph. Is generated and displayed by the result output unit 109.
These processes are repeated between the process 201 and the process 208.
This loop is repeated until the creation of the control program is completed.

In addition to the above flow, it is also possible to take a method of starting the device extraction process 204 triggered by the completion of compilation of the control program.
It is also possible to use a method that uses the timing when the control program is saved and the timing when it is downloaded to the sequencer device as a trigger.
Further, when the process 203 is compiled, it is possible to perform the difference drawing process by comparing with the previous compilation result and performing the process after the process 204 only for the corrected part.

≪2. Corresponding control program display >>
A procedure for displaying the search result of the element of the corresponding original control program by selecting the element (node / edge) of the graph visualized by the GUI will be described below with reference to FIG.

First, in the process 301, at the stage of constructing a graph (connection information 1060 construction), the device extraction unit 102 and the dependency relationship extraction unit 103 determine whether each element of the original control program and each element (node / edge) of the graph. Create a link.
Link information between the nodes of the graph and the device of the original control program is stored in the node structure 1040 as an element of the structure.
Also, link information between the graph edge and the original control program processing (Lang in LD language) is stored in the edge structure 1050 as an element of the structure.
As a result, each element of the displayed graph is associated with the element of the original control program.
By processing 302, the user selects an element of the graph displayed on the GUI.
Then, in process 303, the graph analysis unit 108 determines whether the graph element is a node or an edge.
If it is a node, in the process 304, the link management unit 110 performs all processes using the device represented by the corresponding node from the node structure 1040 and the control program intermediate code 1010 that has followed the link (LD language). Then rung) is searched.
In the case of an edge, in processing 305, the link management unit 110 performs processing represented by the corresponding edge from the edge structure 1050 and the control program intermediate code 1010 that has followed the link (the rung in the case of LD language). Extracted.
Finally, in process 306, the result output unit 109 displays the control program intermediate code 1010 extracted in process 304 or process 305.
For example, the graph and the control program intermediate code 1010 may be displayed side by side.

  After the corresponding elements on the graph are specified by the processing 304 and the processing 305 and the corresponding elements in the control program intermediate code 1010 are specified, the correspondence is performed using the search result display function realized in a general engineering environment. The control program search result display processing 306 to be performed can also be performed.

≪3. Specific device specification output >>
A procedure for displaying the specification of the node in Japanese (an example of a natural language) by selecting a specific node of the graph visualized by the GUI will be described below with reference to FIG.

First, in process 401, a target node is selected from the graph displayed on the GUI by the user.
Next, in process 402, the graph analysis by the graph analysis unit 108 extracts a subgraph including nodes and edges that constitute all paths to the designated node.
That is, the graph analysis unit 108 extracts all nodes and edges that may affect the designated node.
This process can be executed by tracing all directed edges backward from the target node, adding the found nodes and edges to the subgraph, and continuing until no new nodes are found.
For this, general graph analysis logic may be used.
In process 403, the graph analysis unit 108 extracts only nodes that represent input / output devices in the created subgraph.
This means that when a specific device specification is output, a user-friendly device is displayed as an interface with the actual system.
However, the present invention is not limited to input / output devices, and may be executed for internal devices.
In order to perform this process, it is necessary to store the corresponding device type information in the node structure 1040 in advance.
In order to perform processing for each input / output device, loop processing is performed from processing 404 to processing 407.
Inside, in step 405, the graph analysis unit 108 converts the directed edge from the target input / output device into Japanese.
For example, if the specific device is “motor C (forward rotation)”, the label name of the target input device is “sensor A”, and the type of the directed edge coming out from it is “A contact-coil”. An explanatory note “Motor C (forward rotation) depends on sensor A” is created.
Also, if the label of the other input device is “emergency stop button B” and the edge type is “B contact-coil”, the explanation is “Motor C (forward rotation) depends on emergency stop button B”. Is created.
In processing 406, these explanatory texts are presented to the user one sentence at a time by the result output unit 109.
In the process 405, only the edge adjacent to the input / output device is taken into consideration, in order to simplify the text of the output specification.
More strictly, it is possible to link all the paths from the input / output device to the specific device along the directed edge so that all are translated into Japanese.
On the other hand, there is a method in which the processing of 405 is omitted, and only an input / output device is provided and displayed as a simple specification.
In this case, the information on the edge adjacent to the input / output device is not used, and the description is uniformly “dependent on [input / output device]”.

<< 4. Range of influence >>
A procedure for illustrating the range of influence on the control program when a specific region of the graph visualized by the GUI is selected and the range is changed will be described with reference to FIG.

First, in a process 501, a target region (partial graph) is selected from a graph displayed on the GUI by the user.
Next, in process 502, the graph analysis unit 108 extracts a partial graph including nodes and edges that constitute all paths to the specified region by graph analysis.
This process continues for all nodes in the target area, tracing the directed edge adjacent to that node backwards, adding the found nodes and edges to the subgraph, and continuing until no new nodes are found. It can be executed with.
By this processing, the graph analysis unit 108 can extract the affected range affected by the change when the element (designated element) in the target area designated by the user is changed.
The extraction process of the influence range may use a general graph analysis logic.
In processing 503, the result output unit 109 highlights the created partial graph in the already displayed whole graph so that the affected range can be understood.

  Although only an example in which the result is illustrated on the graph is shown here, a method of displaying the processing in the control program intermediate code (Lang in LD language) can also be taken.

≪5. Unused part detection >>
A procedure for illustrating a device group (unused device group) that does not affect any output device in the control program on the graph visualized by the GUI will be described with reference to FIG.

First, in steps 601 to 603, the process is repeated for all output devices.
In process 602, the graph analysis unit 108 extracts a partial graph including nodes and edges constituting all paths to the output device by graph analysis.
This process can be performed for nodes representing output devices by tracing back the directed edge adjacent to that node, adding the found nodes and edges to the subgraph, and continuing until no new nodes are found. It is.
For this, general graph analysis logic may be used.
Moreover, the same algorithm as the above-mentioned influence range illustration can also be diverted to this part.
In addition to the output device, there may be a device that serves as an interface with an external system.
For these, the user may arbitrarily designate a device group or select a device type.
In process 604, the graph analysis unit 108 extracts all nodes (unused devices) and edges that are not included in the partial graph extracted in process 603 from the already displayed whole graph.
Since only unused devices are displayed in a list, elements extracted here may be limited to only nodes.
In step 605, the result output unit 109 highlights these subgraph groups.

  Although only an example in which the result is illustrated on the graph is shown here, a method of displaying the processing in the control program intermediate code (Lang in LD language) can also be taken.

≪6. Circular definition detection >>
Detects combinations of devices that may cause chattering by software (a phenomenon that a specific device repeats ON and OFF every cyclic time (a constant multiple)) in a control program on a graph visualized by GUI. The procedure for this will be described below with reference to FIG.
This phenomenon usually occurs when there is a cycle (a closed circuit considering the direction of an edge) in the directed graph expression disclosed in the present embodiment, and there are an odd number of negative logic circuits on the path of the cycle. there is a possibility.
However, timer devices, counter devices, and the like that have a delay from when the condition is satisfied until the coil is turned on are excluded.

First, in process 701, the graph analysis unit 108 sets an arbitrary bit device as a start point as a target node.
As described above, target nodes such as timers and counters that do not have a time delay from condition ON to coil ON due to their status are not targeted.
Next, in order to search for a node in the graph, the graph analysis unit 108 searches in the graph in processing 702 and processing 703 to processing 708.
The purpose here is not to include a timer or a counter, and in order to detect a cyclic definition in which negative logic appears an odd number of times, the number of edges (processes) corresponding to negative logic is counted in process 704.
Information regarding whether or not the edge is negative logic required at this time is stored in the edge structure 1050 in the above-described “extraction of dependency” process 205.
Next, in step 705, the graph analysis unit 108 checks whether or not the node that is being searched has reached the counter or timer.
When passing through a counter or timer, it is not extracted as a cyclic definition (because it is considered a normal operation because the device is switched on / off based on a user-defined value different from the cyclic time).
However, as a function to be implemented, the conditional branch processing 705 can be excluded after notifying the user that the circulation definition extraction result includes a counter and a timer.
Next, in process 706, the graph analysis unit 108 checks whether to form a cycle.
Since the circulation (closed circuit) exists when the node visited in the search route up to the present time is reached, the circulation path is recorded in processing 707.
Finally, in the process 709, the graph analysis unit 108 extracts, as a circulation definition, there is a risk that chattering by software may occur due to the circulation definition for the recorded number of negative logics of the circulation path.
In process 710, the result output unit 109 illustrates the corresponding path.

FIG. 7 is based on the premise that the target control program and the graph expressing it are connected.
When the control program is composed of several independent subgraphs, it is necessary to select one start node by the process 701 in each independent subgraph.
Note that the search procedure in the graph described from processing 702 to processing 708 is an example, and other graph analysis algorithms may be used.

≪7. Device value monitor >>
Figure 8 shows the procedure for specifying the device group that the user wants to monitor the current value on the graph visualized by the GUI, and monitoring the current value of those devices when connected to the sequencer device or control program simulator. Based on the following.

First, in process 801, an arbitrary device group that the user wants to monitor is selected on a graph visualized by the GUI.
However, when all devices in the control program or all devices displayed on the screen are targeted, designation from the user is unnecessary.
Next, processing 802 to processing 805 is repeated for the selected device.
In process 803, the online monitor unit 111 acquires the current value of the corresponding device from the sequencer device or the control program simulator for each target device and stores it in the node structure 1040.
In step 804, the result output unit 109 displays the current value of the device represented by the node as text on the node of the graph, by changing the shape of the node, changing the color of the node, or the like.

In addition, when performing monitoring regularly, it is realizable by repeating the process from the process 802 to the process 805 for every second, for example.
Further, if it is possible to obtain from the sequencer device or the control program simulator which process in the control program is executed as well as the current value of the device, the online monitor unit 111 is executing processing on the edge structure 1050. It can also be displayed on the graph by setting / releasing the flag.

≪8. Illustration of failure factors >>
When a failure occurs on the actual system or the control program simulator, a device on which the failure is manifested by the user on the graph visualized with the GUI in order to identify a bug in the control program that causes the failure, A procedure for illustrating a device or a process that causes a failure by specifying a device that operates completely normally will be described below with reference to FIG.

First, in process 901, the graph analysis unit 108 sets the factor area to be empty as an initial process.
The factor area is an area for storing elements shown on the graph as candidate fault factors.
Thereafter, processing 902 to processing 909 are repeatedly executed until the user specifies the failure factor.
In the process 903, when a failure occurs, the user designates a device in which the phenomenon directly appears or a device that definitely behaves abnormally, and inputs that it is an “abnormal” device.
In step 904, the graph analysis unit 108 extracts a partial graph obtained by merging all paths from the entire graph to the device node (abnormality device node) designated by the user.
That is, the graph analysis unit 108 extracts the directed edge connected to the abnormality-occurring device node from the directed directed graph of the closed circuit, and extracts the node (device) connected to the extracted directed edge.
This process is the same as the process 502 described above.
Next, in process 905, the graph analysis unit 108 checks normality / abnormality of the extracted device.
Normal / abnormal for each device is specified by the user.
For the device designated as “normal” by the user, the extracted subgraph is deleted from the current factor area in processing 906 (the node of the device designated as “normal” is connected to the node) Do not include edges in the factor area).
This is because, among the factor areas that may include a failure factor, an area that affects a device that is determined to be completely normal under all conditions can be excluded from the factor area.
On the other hand, for the device designated as “abnormal” by the user, in step 907, the extracted subgraph is added to the current factor area (the node of the device designated as “abnormal” is connected to the node). Included in the factor area).
This is because a factor area in which a failure factor may be included is expanded.
Here, since the failure factor is not necessarily one, the AND of the partial graph extracted in the processing of 907 and the factor area at that time is not taken.
Next, in process 908, the result output unit 109 highlights the factor area at that time on the graph.
This makes it possible to narrow down the devices and processes that are considered to be the cause of the failure.

In step 907, the portion corresponding to the AND area of the partial graph and the factor area at that time can be displayed separately from the entire factor area by color change or shape change.
Thereby, it is possible to narrow down an area where there is a high possibility that a factor exists.

Embodiment 2. FIG.
≪Example of graph display≫
Here, how the control program for the FA system written in the LD language is converted into a directed circle directed graph and displayed will be described with a specific example.

FIG. 10 shows an example of a control program for the FA system, which is written in the LD language.
This control program operates with the following specifications.
FIG. 18 describes the control program of FIG. 10 in the IL language.
a) When an input (start button) is pressed, an output (lamp) is turned on.
b) The output (lamp) is lit for 3 seconds.
c) When executed three times, the input (start button) does not respond.
d) Pressing the input (reset button) resets the device value and returns to the initial state.
e) The input (start button) does not need to be held down and the internal device will hold itself.

FIG. 10 showing the LD program will be described below.
1000 is an example of a control program that satisfies the specifications 1) to 5).

First, the coil 1004 of the internal device is defined in the first rung (circuit block).
The internal device 1004 is an intermediate device for directly defining an output (lamp).
As described in a) of the above specification, the internal device 1004 is turned on by pressing the input (start button), and therefore, the input (start button) A contact 1001 is a condition.
Next, when the button is pressed three times and the execution is completed three times as in specification c), or when the input (reset button) is pressed as in d), the coil 1004 of the internal device is In order to realize the OFF state, the B contact 1002 of the counter 1002 and the B contact 1003 of the input (reset button) are set as AND conditions.
As shown in e), since the internal device is self-holding, the A contact 1005 of the internal device is attached with the input (start button) and OR condition, but this self-holding continues only for 3 seconds from the specification of b). Timer B contact 1006 is added as an AND condition.
Next, the timer coil 1008 and the output (lamp) coil 1009 are defined.
Since these coils are all defined directly from the internal device, only the A contact 1007 of the internal device is a condition.
The coil 1008 of the timer is turned on when 3 seconds have passed with the internal device 1007 turned on. That is, the timer B contact 1006 is turned OFF when 3 seconds have elapsed.
Next, the counter coil 1012 is defined.
According to the specification c), the counter needs to count up when the input (start button) is pressed three times and the processing is completed. Therefore, the timer time-up timing (that is, timer A contact 1011) is used as a counter condition. The counter 1012 is turned on at the timing when the A contact 1011 of the timer is turned on from three times.
In the last rung, an input (reset button) 1013 is realized.
In order to realize the specification d), the RESET instruction 1014 is used to reset the counter that is counting up to 0 at the timing when the A contact 1013 of the input (reset button) is turned ON.

  The flow of graph display when the control program 1000 as described above is stored as the control program intermediate code 1010 in the system will be specifically described from the processing 204 in the graph display flow 200.

First, the device extraction unit 102 performs a device extraction process 204.
This is achieved by scanning the control program and extracting the devices being used.
In the example of the control program 1000, the device list 1200 (FIG. 12) is extracted as the node structure 1040.
In the device (label) name column of the node structure example 1200, a name that normally identifies the device is registered in the control program. Here, the device ID, label ID, variable name, and the like can be uniquely identified. You can register anything if you want.
The device type field stores device types that can be used by the target sequencer device and control program.

Next, the dependency relationship extraction unit 103 performs a dependency relationship extraction process 205.
This is realized by scanning the control program and extracting the relationship of “conditions → coils” for each rung.
In the example of the control program 1000, the dependency list 1300 (FIG. 13) is extracted as the edge structure 1050.
In the edge type of the edge structure example 1300, the processing type of the control program represented by the edge is registered.
For example, pay attention to the last rung of the control program 1000.
In this rung, there is a dependency between the input (reset button) A contact 1013 and the counter RESET 1014.
This part is expressed in the IL language as follows.
An example in which the control program 1000 is expressed in the IL language is shown in FIG.
As described above, generally, the LD language program element and the IL language program element can be associated one-to-one.
LOAD input (reset button) ――― 1013
RESET counter ―――――――――― 1014
In the example of the edge structure 1300, the IL language instructions are combined to form an edge type.
In the above example, “LOAD-RESET” represented by number 9 of the edge structure 1300 is the edge type.
With this edge type, it is possible to express an outline of the dependency between two devices.
Next, the logic column registers the logic (positive logic / negative logic) between the two devices connected by the edge.
The logic here indicates whether or not the processing expressed by the directed edge reverses ON / OFF of the device. For this reason, it is invalid when the device type is not a bit (when it is a word).

Next, the dependency relationship extraction unit 103 performs connection information construction processing 206.
This is a process of linking the node structure 1200 and the edge structure 1300 created in the process 204 and the process 205.
In the example of the control program 1000, connection information 1400 (FIG. 14) is constructed.
The edge column of the connection information 1400 indicates the edge number in the edge structure 1300 expressing the connection relationship.
Similarly, the source node column and the destination node column indicate the node numbers in the node structure 1200.
Since the edge represented by the connection information is always a directed graph, it is set separately in the source node column and the destination node column.
Since the number field of the normal edge structure 1300 and the edge field of the connection information 1400 correspond one-to-one, the edge structure 1300 and the connection information 1400 may be realized as the same table.

Finally, the graph generation unit 112 performs the generation / drawing processing 207 of the closed-circuit directed graph.
The node structure 1200, the edge structure 1300, and the connection information 1400, which are information for drawing a graph, are all created by the processing up to the processing 205 described above.
For this reason, the graph generation unit 112 generates and draws a directed circuit for a closed circle by combining the dependency relationship between the device of the node structure 1200 and the edge structure 1300 in accordance with the association indicated in the connection information 1400.

FIG. 11 schematically shows an example in which the control program 1000 is displayed by the graph display method according to the present embodiment.
Input devices and output devices are indicated by rectangles, and internal devices are indicated by circles.
Further, positive logic processing is indicated by a solid line, and negative logic processing is indicated by a broken line.
Also, (1) to (6) in the nodes of FIG. 11 represent the numbers shown in the node structure 1200 (FIG. 12), and (1) to (9) in the vicinity of the edges are the edge structures 1300. The numbers shown in FIG. 13 are shown.

Here, a procedure for drawing nodes and edges, which are elements constituting a graph, will be described.
For example, if it is desired to classify and display on the screen for each type of node (device), the same device types in the node structure 1200 are collected and displayed on the screen.
When an input device is acquired from the device type of the node structure 1200, the “bit input” becomes an input (start button) 1101 and an input (reset button) 1102.
Similarly, when an internal device is acquired from the device type of the node structure 1200, those that are “timer”, “counter”, and “bit internal” are the internal device 1103, the timer 1104, and the counter 1105.
Next, when an output device is acquired from the device type of the node structure 1200, what is “bit output” becomes an output (lamp) 1106.
Next, the source node column and the destination node column in the connection information 1400 table are checked, and the edge number and the edge type and logic of the edge structure 1300 are acquired.
As a result, the edge connected between the nodes displayed as a graph is known, and the line type of the edge is changed according to the edge type and logic.
As described above, in the example of FIG. 11, from the logical column of the edge structure 1300, the process (edge) is indicated by a solid line when the process is positive logic and by a broken line when the process is negative logic.
Looking at the first line of the connection information 1400, since the source node number is 1, the destination node number is 2 and the edge number is 1, an edge exists between the input (start button) 1101 and the internal device 1103, and the edge It can be seen that the edge type is “LOAD-OUT” and is positive logic.
Accordingly, a solid line edge 1110 is drawn as a directed edge between the input (start button) 1101 as a graph and the internal device 1103 on the screen.
Further, for example, as shown in the second line of the connection information 1400, the edge 1113 is displayed in the form of a loop in the case of an edge to its own node.
Thus, in the edge structure 1300 and the connection information 1400, the edge number 1 is a solid line edge 1110, the number 2 is a solid line loop edge 1113, the number 3 is a broken line edge 1116, the number 4 is a broken line edge 1118, and the number 5 is a broken line edge. Reference numeral 1111, number 6 corresponds to a solid line edge 1115, number 7 corresponds to a solid line edge 1114, number 8 corresponds to a solid line edge 1117, and number 9 corresponds to a broken line edge 1112.
In this way, the control program 1000 can display a graph as shown in FIG.

Since the graph of FIG. 11 is automatically displayed from the control program 1000, various methods can be used for the node placement algorithm of the graph of FIG.
As described above, there are a method of arranging the same type of nodes in the same area, a method of arranging the devices in order of numbers and names represented as nodes, and the order of nodes (number of edges entering and exiting from the nodes). Many orders are considered.
There is also a method of displaying two nodes connected by an edge closer to each other.
A general complex graph display algorithm can be used for the arrangement method of these nodes and edges.
In addition, the graph can be displayed not only on a two-dimensional plane but also on a three-dimensional space.
Further, the node and edge once displayed can be freely changed by the user.
In this case, the nodes and edges can be changed to the user's preferred arrangement by a method such as dragging and dropping with the mouse, in the same way as a function installed in a general graph drawing tool.

Embodiment 3 FIG.
≪Example of influence range illustration≫
FIG. 15 is an example in which a certain control program is displayed in a graph.
This control program consists of two input bit devices 1501 and 1502, three internal bit devices 1503, 1504 and 1505, and three output bit devices 1506, 1507 and 1508.
The solid line edge indicates that the process represented by the edge is positive logic, and the broken line edge indicates that the process represented by the edge is negative logic.

  An example of the influence range illustration will be described below using this graph.

Referring to FIG. 5 showing the flow of the influence range, the target area selection process 501 is first performed by the user.
In this example, it is assumed that the node 1506 of output 1 is selected by the user.
In the next process 502, the graph analysis unit 108 lists all nodes that reach the target area.
In the case of the example of FIG. 15, the adjacent directed edge that reaches the node 1506 that is the target area is only the edge 1515, and therefore this is first added as a path.
Next, attention is paid to the original node 1503 of the edge 1515.
Adjacent directed edges leading to this node are edge 1514 and edge 1510, so they are added as paths.
At this time, since the edge 1514 is a loop returning to the node 1503, the search for this path ends here.
Note the original node 1501 of the other edge 1510.
For this node 1501, since there is no adjacent directed edge leading to this node, the search ends here.
As a result, the highlighted portion in the processing of 503 is an area shown in FIG.
In other words, when the node 1606 of the output 1 is targeted, the range influencing this node includes the parts indicated by black and thick lines in FIG. 16, that is, the processing 1615, the internal 1 device 1603, the processing 1614, Processing 1610 and input device 1601 are obtained.

In this way, in the process 502 of the flow shown in the influence range, all paths can be extracted by performing a search for tracing the directed edge in the reverse direction.
A general graph search algorithm can be used as the search method at this time.
The search method may be depth-first search or breadth-first search.
However, since the graph is a closed graph, there is a restriction that a node that has already been visited is stored, and because the graph is a directed graph, the direction of the edge is searched in the reverse direction.

≪Example of circulation definition detection≫
Similarly, an example of cyclic definition detection will be described below using the graph of FIG.

Referring to FIG. 7 showing the flow of circular definition detection, first, in process 701, an arbitrary bit device is set as a target node.
Here, as an example, the node 1501 of input 1 is selected.
Next, in process 702, the graph analysis unit 108 selects an edge that has come out of the target node.
In the example of FIG. 15, the edge 1510 and the edge 1511 are targeted.
From here, the search in the graph is started in processing 703.
In the loop, the logic of the edge is checked by processing 704.
Since both the edge 1510 and the edge 1511 are positive logic, the count-up is not performed.
In step 705, the graph analysis unit 108 determines whether the next node is a counter or a timer.
Since the internal 1 node 1503 that is the node reached by the edge 1510 and the internal 2 node 1504 that is the node reached by the edge 1511 are not counters or timers, the processing directly proceeds to processing 706.
In the next process 706, only the first input node selected first is stored as “the node that has already passed” at this time, so the internal 1 node 1503 and the internal 2 node 1504 reached here are different. The condition 706 is not met.
Therefore, the process returns to the process 704.
Next, paying attention to the internal 1 node 1503, the edge 1514 and the edge 1515 coming out from this node are determined.
Since the edge 1514 is positive logic, the count-up is not performed in the process 705, but the edge 1514 is a loop edge, and therefore satisfies the condition 706.
In step 707, the set of the path and the negative logic count value “internal 1 node 1503, edge 1514, count 0” is saved as the cyclic definition.
The edge 1515 exiting from the internal 1 node 1503 reaches the output 1 node 1506 as it is, and there is no edge exiting from the node 1506, so the search for this branch ends here.
Next, the graph search is similarly continued for the internal two nodes 1504.
Then, it can be seen that there is a closed circuit such as “internal 2 node 1504, edge 1517, internal 3 node 1505, edge 1518, output 3 node 1508, edge 1519, count 1”.
Of the three edges constituting this closed circuit, only the edge 1519 represents a negative logic process.
As a result, in the process 709, this cycle corresponds to an odd number of negative logic among the circulation definition paths.
The previously extracted “internal 1 node 1503, edge 1514, count 0” is excluded from the target because the count is an even number.
Therefore, in the process 710, as shown in FIG. 17, the cyclic definition “internal 2 node 1704, edge 1717, internal 3 node 1705, edge 1718, output 3 node 1708, edge 1719, count 1” can be extracted.
Therefore, it can be seen that in the control program shown in FIG. 15 or FIG. 17, the three devices, internal 1, internal 2 and output 3, have a risk of chattering by software.

<< Effects of Embodiment >>
According to the method disclosed in the first to third embodiments, a variable (device) controlled by a control program is extracted as a node, and an interaction between devices is extracted as a dependency to be an edge. It is possible to visually display the relationship between the devices used in the control program as a directed cycle graph with a GUI.
If you focus on a particular node, or device, in the graph display, the control program represents all operations caused by that device as edges coming out of that node and has an effect on that device. Every operation you give will be represented as an edge entering that node.
Therefore, by confirming the graph display of the control program, it is possible to support understanding of the control program centered on the device even for an operator who is not skilled in the LD language or the IL language.
In addition, by displaying the control program as a directed circuit with closed circuit and designating a part of the visualized display, it is possible to illustrate the range of influence when the designated device group is changed.
As a result, for example, when a failure occurs in the FA / PA system in which the control program operates, the cause discovery can be supported in a shorter time than when the cause of the failure is investigated using only the LD language or the IL language.
In addition, by holding the control program in a data structure as a directed graph with cycles, it is possible to check for potential bugs in the program such as chattering by software. Therefore, when designing a control program, a simulator or actual FA / PA It is possible to know the potential bugs that can be found by connecting to the system and the danger of unstable operation by static checking of the program.
As a result, it is possible to help reduce the number of reworking steps in the control program design phase.

In the above first to third embodiments,
By extracting the variable (device) controlled by the control program as a node, extracting the interaction between devices as a dependency and making it an edge, by holding the control program in a data structure as a closed-circuit directed graph, A system that supports the following when designing a control program was explained.
1) The relationship between devices used in the control program is visually displayed on the GUI. 2) By specifying the visualized display part, the corresponding original control program part is displayed. ) For a specific device, display the specification showing the relationship with other devices in text 4) Illustrate the range of influence when the specified device group is changed 5) Unused in the control program Point out about devices 6) Point out potential bugs in programs such as chattering by software 7) Support the reuse of software parts by visualizing the same structure that appears in multiple places 8) Loosely coupled parts of devices 9) Supporting the division of the control program by analyzing An indication of the degree of coupling between devices.

In the first to third embodiments,
By extracting the variable (device) controlled by the control program as a node, extracting the interaction between devices as a dependency and making it an edge, by holding the control program in a data structure as a closed-circuit directed graph, A system that provides the following support during control program maintenance was described.
10) Monitor the device value on the dependency visually displayed on the GUI. 11) Designate a device group in which a failure has occurred, and illustrate a possible location.

The following configuration for realizing the above has also been described.
1) "Device extractor" that extracts devices used in the control program as nodes
2) “Dependency Extraction Unit” that extracts the dependency (process) between the described devices as an edge
3) “Condition input section” for entering analysis conditions and failure status
4) “Graph Analysis Unit” that analyzes the structure of a directed circuit with cycles
5) “Result output unit” for outputting analysis results
6) “Link management unit” that manages the correspondence between the control program and the directed directed graph
7) An “online monitor” that acquires the current value of the device by communicating with the actual device.

Furthermore, the data structure having the following characteristics for holding the directed graph with closed circuit constructed by the graph construction unit in the memory in the system has been described.
1) A device (label) is expressed as a node structure 2) A process is expressed as an edge structure having link information to the processing position of the original control program 3) Topology information that connects the node structure and the edge structure.

  In addition, for a control program stored in a control device on a network, etc., and divided into a plurality of control programs, by referring to the common device settings between the control programs, the plurality of control programs can be seamlessly converted into a single directed circle graph. The handling system, configuration and procedure were also explained.

<< Hardware configuration example >>
Finally, a hardware configuration example of the information processing apparatus 100 shown in the first to third embodiments will be described.
FIG. 19 is a diagram illustrating an example of hardware resources of the information processing apparatus 100 illustrated in the first to third embodiments.
Note that the configuration in FIG. 19 is merely an example of the hardware configuration of the information processing apparatus 100, and the hardware configuration of the information processing apparatus 100 is not limited to the configuration illustrated in FIG. Also good.

In FIG. 19, the information processing apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, a processing unit, a microprocessor, a microcomputer, and a processor) that executes a program.
The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices.
Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an SSD (Solid State Drive), an optical disk device, or a memory card (registered trademark) read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
The “˜storage unit” described in the first to third embodiments is realized by the RAM 914, the magnetic disk device 920, and the like.
A communication board 915, a keyboard 902, a mouse 903, a scanner device 907, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

The communication board 915 is connected to the network.
For example, the communication board 915 is connected to a LAN (local area network), the Internet, a WAN (wide area network), a SAN (storage area network), and the like.

The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924.
The programs in the program group 923 are executed by the CPU 911 using the operating system 921 and the window system 922.

The RAM 914 temporarily stores at least part of the operating system 921 program and application programs to be executed by the CPU 911.
The RAM 914 stores various data necessary for processing by the CPU 911.

The ROM 913 stores a BIOS (Basic Input Output System) program, and the magnetic disk device 920 stores a boot program.
When the information processing apparatus 100 is activated, the BIOS program in the ROM 913 and the boot program in the magnetic disk device 920 are executed, and the operating system 921 is activated by the BIOS program and the boot program.

  The program group 923 stores programs that execute the functions described as “˜unit” (except for “˜storage unit” in the following) in the description of the first to third embodiments. The program is read and executed by the CPU 911.

In the file group 924, in the description of the first to third embodiments, “extraction of”, “generation of”, “construction of”, “selection of”, “conversion of”, “setting of” ”,“ Registration of ”,“ acquisition of ”,“ input of ”,“ output of ”, etc., information, data, signal values, variable values, and parameters indicating the results of the processing are“ It is stored as each item of "~ file" and "~ database".
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory.
Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit.
The read information, data, signal value, variable value, and parameter are used for CPU operations such as extraction, search, reference, comparison, calculation, calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
In addition, the arrows in the flowcharts described in Embodiments 1 to 3 mainly indicate input and output of data and signals.
Data and signal values are recorded on a recording medium such as a memory of the RAM 914, a flexible disk of the FDD 904, a compact disk of the CDD 905, a magnetic disk of the magnetic disk device 920, other optical disks, a mini disk, and a DVD.
Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

In addition, what is described as “˜unit” in the description of the first to third embodiments may be “˜circuit”, “˜device”, “˜device”, and “˜step”, It may be “˜procedure” or “˜processing”.
That is, the “information processing method” according to the present invention can be realized by the steps, procedures, and processes shown in the flowcharts described in the first to third embodiments.
Further, what is described as “˜unit” may be realized by firmware stored in the ROM 913.
Alternatively, it may be implemented only by software, or only by hardware such as elements, devices, substrates, and wirings, by a combination of software and hardware, or by a combination of firmware.
Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD.
The program is read by the CPU 911 and executed by the CPU 911.
That is, the program causes the computer to function as “to part” in the first to third embodiments. Alternatively, the computer executes the procedure and method of “to part” in the first to third embodiments.

As described above, the information processing apparatus 100 described in the first to third embodiments includes a CPU that is a processing device, a memory that is a storage device, a magnetic disk, a keyboard that is an input device, a mouse, a communication board, and a display device that is an output device, a communication device, and the like. A computer including a board or the like.
Then, as described above, the functions indicated as “˜units” are realized using these processing devices, storage devices, input devices, and output devices.

  DESCRIPTION OF SYMBOLS 100 Information processing apparatus, 101 Control program intermediate code storage part, 102 Device extraction part, 103 Dependency extraction part, 104 Node structure storage part, 105 Edge structure storage part, 106 Connection information storage part, 107 Condition input part, 108 Graph analysis unit, 109 result output unit, 110 link management unit, 111 online monitor unit, 112 graph generation unit.

Claims (16)

From a control program in which a plurality of devices are described and dependencies between the devices are described, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependencies between the devices. A device extractor for extracting the description;
A dependency extraction unit that extracts a description of the dependency between devices from the control program;
Based on the description of the device extracted by the device extraction unit and the description of the dependency relationship between the devices extracted by the dependency relationship extraction unit, the node represents the device, the directed edge represents the dependency relationship between the devices, A graph generation unit for generating a directed directed graph of a circuit representing a control algorithm defined in the control program by connecting a node and a directed edge ;
A measurement value input unit that inputs measurement values measured by a predetermined device when control using the control program is performed on the plurality of devices;
An information processing apparatus comprising: a display unit configured to display a measurement value input by the measurement value input unit with respect to a node of a corresponding device in the directed circuit with closed circuit . From a control program in which a plurality of devices are described and dependencies between the devices are described, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependencies between the devices. A device extractor for extracting the description;
A dependency extraction unit that extracts a description of the dependency between devices from the control program;
Based on the description of the device extracted by the device extraction unit and the description of the dependency relationship between the devices extracted by the dependency relationship extraction unit, the node represents the device, the directed edge represents the dependency relationship between the devices, A graph generation unit for generating a directed directed graph of a circuit representing a control algorithm defined in the control program by connecting a node and a directed edge ;
When a failure occurs in any device, the directed directed graph is analyzed, and the directed edge connected to the failed device node representing the failed device is extracted from the directed directed graph and extracted. If a node connected to the directed edge is extracted, and it is determined that an abnormality has occurred in the device represented by the extracted node, extraction of the directed edge connected to the extracted node and If a node connected to the extracted directed edge is extracted and it is determined that an abnormality has occurred in the device represented by the extracted node, the directed node connected to the extracted node A graph analysis unit that repeats extraction of edges and extraction of nodes connected to the extracted directed edges;
An information processing apparatus comprising: a display unit configured to distinguish the faulty device node and a node representing a device determined to have an abnormality from the other nodes and display the same in the directed circle directed graph . The dependency extraction unit
Generating connection information that associates the description of the device extracted by the device extraction unit with the extracted description of the dependency relationship;
The graph generation unit
Using the description of the device extracted by the device extraction unit, the description of the dependency relationship between devices extracted by the dependency relationship extraction unit, and the connection information generated by the dependency relationship extraction unit, the closed circuit the information processing apparatus according to claim 1 or 2, characterized in that to generate a directed graph. The device extraction unit
A description of each device is extracted from a control program created in a language defined by the International Electrotechnical Commission (IEC) 61131-3 standard,
The dependency extraction unit
The information processing apparatus according to claim 1, wherein a description of a dependency relationship between devices is extracted from the control program created in a language defined in the IEC61131-3 standard. The display unit
The information processing apparatus according to claim 1 or 2, characterized in a Turkey to display chromatic directed acyclic graph generated by the graph generating unit by GUI (Graphical User Interface) scheme. The dependency extraction unit
As a dependency relationship between devices, a description of the dependency relationship between devices is extracted from a control program in which a starting device that is a starting point in one operation procedure and a dependent device whose operation state depends on the operation of the starting device are described. ,
The graph generation unit
3. The information processing apparatus according to claim 1, wherein a directed directed graph representing the control algorithm defined by the control program is generated using a directed edge from a source device toward a dependent device. 4. The dependency extraction unit
As a dependency relationship between devices, a description of the dependency relationship between devices is extracted from the control program in which the dependency relationship between positive logic and negative logic is described.
The graph generation unit
The information processing apparatus according to claim 1 or 2 , wherein a directed directed graph is generated in which a directed edge representing a positive logic dependency and a directed edge representing a negative logic dependency are distinguished. The information processing apparatus further includes:
An information input unit that inputs specified element information that specifies at least one of a specific device and a specific dependency described in the control program as a specified element;
The chromatic directed acyclic graph analyzes, and a graphic analysis unit for extracting a range of influence affected by the change in the event of a change to the specified elements is specified in the specified element information from said chromatic directed acyclic graph,
The display unit
The information processing apparatus according to claim 1, wherein the range of influence extracted by the graph analysis unit is displayed in the directed circle directed graph. The information processing apparatus further includes:
An information input unit that inputs specified element information that specifies at least one of a specific device and a specific dependency described in the control program as a specified element;
And a program code extraction unit for extracting a program code specified element specified by the specified element information is described from the control program,
The display unit
A chromatic directed acyclic graph generated by the graph generating unit, the information processing apparatus according to claim 1 or 2, characterized in a Turkey to display the program code extracted by said program code extraction unit. The information processing apparatus further includes:
Analyzing the directed circuit directed graph, and having a graph analyzing unit for extracting a circulation that may cause chattering from the directed circuit directed to the closed circuit ,
The display unit
The information processing apparatus according circulating extracted by the graph analysis unit in claim 1, wherein the benzalkonium be displayed in the chromatic directed acyclic graph. The information processing apparatus further includes:
An information input unit for inputting designated element information for designating a specific device described in the control program as a designated element;
Analyzing the directed circle directed graph, extracting a directed edge connected to a node representing a device designated as a designated element in the designated element information from the directed directed graph and connecting to the extracted directed edge Between the device specified as the specified element in the specified element information and the device represented by the extracted node based on the extracted directed edge and the node and a graphic analysis unit that generates a description for explaining the relationship in a natural language,
The display unit
The information processing apparatus according to claim 1, wherein the chromatic directed acyclic graph generated by the graph generation unit, and a benzalkonium displays a description generated by the graph analysis unit. The information processing apparatus further includes:
Analyzing the directed circuit directed graph, and having a graph analyzing unit that extracts a node representing a device not dependent on any device from the directed circuit graph as an unused device node;
The display unit
The information processing apparatus according to claim 1 unused device node extracted by the graph analysis unit, characterized by a Turkey be displayed in the chromatic directed acyclic graph separately from other nodes. From a control program in which a computer describes a plurality of devices and a dependency relationship between devices, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependency relationship between the devices, A device extraction step for extracting a description of each device;
A dependency extraction step in which the computer extracts a description of a dependency relationship between devices from the control program;
Based on the description of the device extracted by the device extraction step and the description of the dependency relationship between the devices extracted by the dependency relationship extraction step, the computer represents the device, and the directed edge is the dependency between the devices. A graph generation step for generating a closed-circuit directed graph that represents a relationship and represents a control algorithm defined in the control program by a connection between a node and a directed edge ;
When the control using the control program is performed on the plurality of devices, the computer inputs measurement values measured by a predetermined device; and
An information processing method comprising: a display step for displaying the measurement value input by the measurement value input step with respect to a node of a corresponding device in the directed circuit with closed circuit . From a control program in which a computer describes a plurality of devices and a dependency relationship between devices, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependency relationship between the devices, A device extraction step for extracting a description of each device;
A dependency extraction step in which the computer extracts a description of a dependency relationship between devices from the control program;
Based on the description of the device extracted by the device extraction step and the description of the dependency relationship between the devices extracted by the dependency relationship extraction step, the computer represents the device, and the directed edge is the dependency between the devices. A graph generation step for generating a closed-circuit directed graph that represents a relationship and represents a control algorithm defined in the control program by a connection between a node and a directed edge ;
When a failure occurs in any of the devices, the computer analyzes the directed directed graph, and extracts a directed edge connected to the failed device node representing the failed device from the directed directed graph. In addition, if a node connected to the extracted directed edge is extracted and it is determined that an abnormality has occurred in the device represented by the extracted node, the directed node connected to the extracted node When an edge is extracted and a node connected to the extracted directed edge is extracted, and it is determined that an abnormality has occurred in the device represented by the extracted node, the node is further connected to the extracted node. A graph analysis step that repeats extraction of a directed edge and extraction of a node connected to the extracted directed edge;
The computer includes a display step of displaying the faulty device node and a node representing a device determined to have an abnormality in the directed circuit graph so as to be distinguished from other nodes. Information processing method. From a control program in which a plurality of devices are described and dependencies between the devices are described, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependencies between the devices. A device extraction step to extract the description;
A dependency extraction step for extracting a description of the dependency between devices from the control program;
Based on the description of the device extracted by the device extraction step and the description of the dependency relationship between the devices extracted by the dependency relationship extraction step, the node represents the device, the directed edge represents the dependency relationship between the devices, A graph generation step of generating a directed directed graph of a circuit representing a control algorithm defined in the control program by connection of a node and a directed edge ;
When control using the control program is performed on the plurality of devices, a measurement value input step for inputting measurement values measured by a predetermined device;
A program for causing a computer to execute a display step of displaying a measurement value input by the measurement value input step with respect to a node of a corresponding device in the directed circuit with closed circuit . From a control program in which a plurality of devices are described and dependencies between the devices are described, and a control algorithm for the plurality of devices is defined by a description of the plurality of devices and a description of the dependencies between the devices. A device extraction step to extract the description;
A dependency extraction step for extracting a description of the dependency between devices from the control program;
Based on the description of the device extracted by the device extraction step and the description of the dependency relationship between the devices extracted by the dependency relationship extraction step, the node represents the device, the directed edge represents the dependency relationship between the devices, A graph generation step of generating a directed directed graph of a circuit representing a control algorithm defined in the control program by connection of a node and a directed edge ;
When a failure occurs in any device, the directed directed graph is analyzed, and the directed edge connected to the failed device node representing the failed device is extracted from the directed directed graph and extracted. If a node connected to the directed edge is extracted, and it is determined that an abnormality has occurred in the device represented by the extracted node, extraction of the directed edge connected to the extracted node and If a node connected to the extracted directed edge is extracted and it is determined that an abnormality has occurred in the device represented by the extracted node, the directed node connected to the extracted node A graph analysis step that repeats extraction of edges and extraction of nodes connected to the extracted directed edges;
A display step of causing the computer to execute a display step of displaying the failure occurrence device node and a node representing a device determined to be abnormal from the other nodes and displaying the same in the directed circuit with closed circuit is provided. program.

Images